Interfacing Analog To Digital Data Converters
Interfacing Analog To Digital Data Converters
• In most of the cases, the PPI 8255 is used for interfacing the analog to
digital converters with microprocessor.
• This section we will only emphasize the interfacing techniques of analog to
digital converters with 8255.
• The ADC is treated as an input device by the microprocessor, that sends an
initialising signal to the ADC to start the analogy to digital data
conversation process.
• The start of conversation(SOC) signal is a pulse of a specific duration.
• The process of analog to digital conversion is a slow process, and the
microprocessor has to wait for the digital data till the conversion is over.
• After the conversion is over, the ADC sends end of conversion (EOC)
signal to inform the microprocessor that the conversion is over and the
result is ready at the output buffer of the ADC.
• These tasks of issuing an SOC pulse to ADC, reading EOC signal from
the ADC and reading the digital output of the ADC are carried out by the
CPU using 8255 I/O ports.
Interfacing Analog to Digital Data Converters (cont..)
• The time taken by the ADC from the active edge of SOC pulse till the active
edge of EOC signal is called as the conversion delay of the ADC.
• It may range any where from a few microseconds in case of fast ADC to even
a few hundred milliseconds in case of slow ADCs.
• The available ADC in the market use different conversion techniques for
conversion of analog signal to digitals. Successive approximation techniques
and dual slope integration techniques are the most popular techniques used
in the integrated ADC chip.
• General algorithm for ADC interfacing contains the following steps:
1. Ensure the stability of analog input, applied to the ADC.
2. Issue start of conversion pulse to ADC
3. Read end of conversion signal to mark the end of conversion
processes.
4. Read digital data output of the ADC as equivalent digital output.
Interfacing Analog to Digital Data Converters (cont..)
• Analog input voltage must be constant at the input of the ADC right from the
start of conversion till the end of the conversion to get correct results.
• This may be ensured by a sample and hold circuit which samples the analog
signal and holds it constant for a specific time duration.
• The microprocessor may issue a hold signal to the sample and hold circuit.
• If the applied input changes before the complete conversion process is
over, the digital equivalent of the analog input calculated by the ADC may
not be correct.
ADC 0808/0809 :
• The analog to digital converter chips 0808 and 0809 are 8- bit CMOS, successive
approximation converters.
• This technique is one of the fast techniques for analog to digital conversion. The
conversion delay is 100µs at a clock frequency of 640 KHz, which is quite low as
compared to other converters.
• These converters do not need any external zero or full scale adjustments as they are
already taken care of by internal circuits.
• These converters internally have a 3:8 analog multiplexer so that at a time eight
different analog conversion by using address lines -
Interfacing Analog to Digital Data Converters (cont..)
• ADD A, ADD B, ADD C. Using these address inputs, multichannel data
acquisition system can be designed using a single ADC.
• The CPU may drive these lines using output port lines in case of
multichannel applications.
• In case of single input applications, these may be hardwired to select the
proper input. Address lines
Analog I/P
• There are unipolar analog to digital selected C B A
converters, i.e. they are able to convert
only positive analog input voltage to their I/P0 0 0 0
digital equivalent. I/P1 0 0 1
• These chips do no contain any internal I/P2 0 1 0
I/P4 1 0 0
I/P5 1 0 1
I/P6 1 1 0
I/P7 1 1 1
Interfacing Analog to Digital Data Converters (cont..)
• If one needs a sample and hold circuit for the conversion of fast signal into
equivalent digital quantities, it has to be externally connected at each of the
analog inputs.
• Vcc Supply pins +5V
• GND GND
• Vref + Reference voltage positive +5 Volts
• Vref _ maximum.
Reference
Analog inputsvoltage negative 0Volts
• I/P0 –I/P7
• ADD A,B,C
minimum.
Address lines for selecting analog inputs.
I/P1 EOC
Control and
I/P2 Timing
unit and
S.A.R.
I/P3 8 Channel
Analog
Multiplexer
I/P4
8-bit
O/P O/P
Latch
I/P5 256 R
Register
ladder and
I/P6 Switch tree
O/P
I/P7 Enable
V ref + V ref _
C B A
Address Lines
Block Diagram of ADC 0808 / 0809
CLOCK
START
ALE
EOC
OE
O/P
9
•MVI A, 98H ; Set Port A and Cupper as input, CLower as output
• When 8 bit digital number is applied at the input of DAC. Then DAC will convert this digital
binary number into proportional analog current I’A’. Using current to voltage converter analog
current I’A’ is converted into proportional analog voltage ‘Va’.
• If digital input=00H then Va=0V.If digital number applied at the input of DAC increased then
Va also increased. Finally when digital=FF H , then Va= maximum. So for obtaining sawtooth
waveform we have to transfer 8-bit digital number from 00-FF in increasing order.
• Bit control word to define port A as output in mode 0=10000000=80H.
1. MVI A, 80H
2. Out 23H
3. MVI B, OAH
4. MVI A,00H
5. L1։ Out 20H
6. INR A
7. JNZ L1
8.DCR B
9. JNZ L1
10. HLT
Control word and port Address are same as before.
MVI A, 80H
OUT 23H
MVI B,OAH