Government Engineering College, Khagaria

(Dept. of Science & Technology, Govt. of Bihar)

Affiliated to Bihar Engineering University, Patna

Department of Computer Science and Engineering

LAB FILE : Computer Organization And Architecture Lab

Paper Code : 105401P

Submitted to : Submitted by :
Mr. Nishant Kumar Name : Anjali kumari
(Asst Professor) Branch : CSE(IOT)
Dept. of CSE Reg. No. : 22155154023
 INDEX
S.No. Experiment Sign
1 Given a 4-variable logic expression, simplify it using
appropriate technique and simulate the same using
basic gates.
2 Design a 4 bit full adder and subtractor and simulate
the same using basic gates.
3 Design Verilog HDL to implement simple circuits
using structural, Data flow and Behavioural model.
4 Design Verilog HDL to implement Binary Adder-
Subtractor Half and Full Adder, Half and Full
Subtractor.
5 Design Verilog program to implement Different types of
multiplexer like 2:1, 4:1 and 8:1.
6 Design Verilog program for implementing various
types of Flip-Flops such as SR, JK and D.
7 Develop an ALP to multiply two 16-bit binary
numbers.
8 Design Verilog program for implementing various
types of Flip-Flops such as SR, JK and D.
9 Develop an ALP to multiply two 16-bit binary
numbers.
10 Develop an ALP to find the sum of first 10 integer
numbers.
11 Develop an ALP to find the largest/smallest number in
an array of 32 numbers.
12 Develop an ALP to count the number of ones and zeros
in two consecutive memory locations.
 1. Simplify a 4-variable logic expression and simulate using
basic gates.
Input: A 4 variable logic Expression, F(A,B,C,D) = ∑ m (2,4,5,7,10,11,14) + d(8,9,12,13,15)

Inputs Output
Decimal
Value A B C D Q

0 0 0 0 0 0

1 0 0 0 1 0

2 0 0 1 0 1

3 0 0 1 1 0

4 0 1 0 0 1

5 0 1 0 1 1

6 0 1 1 0 0

7 0 1 1 1 1

8 1 0 0 0 X

9 1 0 0 1 X

10 1 0 1 0 1

11 1 0 1 1 1

12 1 1 0 0 X

13 1 1 0 1 X

14 1 1 1 0 1

15 1 1 1 1 X

KMAP:

Minimal SOP Equation : A +BC’ +BD +B’CD’

Verilog Program :

Output:
1. A=0 B=0 C=0 D=0 Then Y=0

2. A=0 B=1 C=1 D=1 Then Y=1

 2. Design Verilog HDL to implement simple circuits using structural, Data flow and
Behavioural model.

Y=AB+CD
Verilog Program :
Structural Gate Level
Data Flow Model Behavioral Model
Model

module fig(A, B, C, module fig(A, B, C, module fig(A, B, C,

D, Y); D, Y); D, Y);
input A, B, C, D; input A, B, C, D; input A, B, C, D;
output Y; wire op1, output Y; output Y; reg Y;
op2; and g1(op1, A, assign always @(A or B or C or
B); and g2(op2, C,D); Y=(A&B)|(C&D); D) if((A = = 1) && (B = =
or g3(Y, op1, op2); endmodule 1)) Y=1;
endmodule else if((C = = 1) && (D =
= 1))
Y=1; else Y=0;
endmodule

Output :
1. A=1 B=1 C=1 D=1 Then Y=1
2. A=1 B=0 C=1 D=0 Then Y=0
 3.
Design Verilog HDL to implement Binary Adder-Subtractor – Half and Full Adder,
Half and Full Subtractor.
1. Half Adder Design :

Inputs Outputs
Carry Sum
A B
(Cout) (S)
0 0 0 0
0 1 0 1
1 0 0 1
1 1 1 0

S = A ̅ 𝐁 ̅ + 𝐀 ̅ 𝐁 , Cout = A B

The Sum equation can also be realized using XOR gate

S =A , Cout = A B
2. Full Adder Design :

Inputs Outputs

Carry in Carry out Sum

A B (Cin) (Cout) (S)

0 0 0 0 0

0 0 1 0 1

0 1 0 0 1

0 1 1 1 0

1 0 0 0 1

1 0 1 1 0

1 1 0 1 0

1 1 1 1 1
 Kmap

Simplified Equation for Sum can be written as S = A C

Cout = A B + A Cin + B Cin

3. Half Subtractor Design :

Inputs Outputs

Borrow Difference
X Y (Bout) (D)

0 0 0 0

0 1 1 1
 1 0 0 1

1 1 0 0

D = X 𝐘 ̅ + ̅ 𝐗 ̅ 𝐘, Bout = 𝐗 ̅ 𝐘

Simplified Equation for Difference can be written as, D = X Y

4. Full Subtractor Design :

Inputs Outputs

Borrow in Borrowout Diff

X Y (Bin) (Bout) (D)

0 0 0 0 0

0 0 1 1 1

0 1 0 1 1
0 1 1 1 0

1 0 0 0 1

1 0 1 0 0

1 1 0 0 0

Kmap
 Simplified Equation for Difference is

D=X Y Bin
Bout = ̅ 𝐗 ̅ 𝐁𝐢𝐧 + Y Bin + ̅ 𝐗 ̅ 𝐘

HALF ADDER AND SUBTRACTOR VERILOG CODE

module HalfAS(a,b,sum,car,dif,bw);
input a, b;
output sum, car, dif, bw;

//Half Adder assign sum = a ^ b;

assign car = a & b;

//Half Subtractor assign dif = a ^ b;

assign bw = ~a & b;
endmodule

Output:
FULL ADDER AND SUBTRACTOR VERILOG CODE
module FullAS(a,b,c,sum,car,dif,bw);
input a, b, c;
output sum, car, dif, bw;

//Full Adder assign sum = a ^ b ^ c;

assign car = (a & b) | (a & c) | (b & c);

//Full Subtractor assign dif = a ^ b ^ c;

assign bw = (~a & b) | (~a & c) | (b & c);
endmodule

Output:
 4.
Design a 4 bit full adder and subtractor and simulate the same
using basic gates.

module AS4bit(A, B, car, SUM, bw, DIF);

input [3:0]A;
input [3:0]B;
output car, bw;
output [3:0]SUM;
output [3:0]DIF;
wire c1,c2,c3,c4;
wire b1,b2,b3,b4;

FullAdd f1(A[0],B[0],0 ,SUM[0],c1);

FullAdd f2(A[1],B[1],c1,SUM[1],c2);
FullAdd f3(A[2],B[2],c2,SUM[2],c3);
FullAdd f4(A[3],B[3],c3,SUM[3],c4);
assign car = c4;
FullSub f5(A[0],B[0],0 ,DIF[0],b1);
FullSub f6(A[1],B[1],b1,DIF[1],b2);
FullSub f7(A[2],B[2],b2,DIF[2],b3);
FullSub f8(A[3],B[3],b3,DIF[3],b4);
assign bw = b4;
endmodule
module FullAdd(a,b,c,sum,car);
input a, b, c;
output sum, car;
//1-bit Full Adder
assign sum = a ^ b ^ c;
assign car = (a & b) | (a & c) | (b & c);
endmodule
module FullSub(a,b,c,dif,bw);
input a, b, c;
 output dif, bw;
//Full Subtractor
assign dif = a ^ b ^ c;
assign bw = (~a & b) | (~a & c) | (b & c);
endmodule

Output:
 5. Design Verilog HDL to implement Decimal adder.

module DecimalAdder(A,B,SUM);
input [3:0]A;
input [3:0]B;
output [4:0]SUM;
assign SUM = A + B;
endmodule

Output:
6.
Design Verilog program to implement Different types of multiplexer like 2:1, 4:1
and 8:1.

//8:1 mux
module MUX(S,D,Y);
input [2:0]S;
input [7:0]D;
output Y;
reg Y;
always @ (S or D)
case (S)
0: Y = D[0];
1: Y = D[1];
2: Y = D[2];
3: Y = D[3];
4: Y = D[4];
5: Y = D[5];
6: Y = D[6];
7: Y = D[7];
endcase
endmodule

//4:1 mux
module MUX(S,D,Y);
input [1:0]S;
input [3:0]D;
output Y; reg Y;
always @ (S or D)
case (S)
0: Y = D[0];
1: Y = D[1];
2: Y = D[2];
3: Y = D[3];
endcase
endmodule
`timescale 1ns / 1ps
//2:1 mux
module MUX(S,D,Y);
input [0:0]S;
input [1:0]D;
output Y;
reg Y;
always @ (S or D)
case (S)
0: Y = D[0];
1: Y = D[1];
endcase
endmodule

Output:
2:1 Mux

4:1Mux

8:1 Mux
 7.
Design Verilog program to implement types of De-Multiplexer.

module DEMUX(S,D,Y);
input [1:0]S;
input D;
output [3:0]Y;
reg [3:0]Y;
always @ (S or D)
begin
Y[3:0] = 0;
case (S)
0: Y[0] = D;
1: Y[1] = D;
2: Y[2] = D;
3: Y[3] = D;
endcase
end
endmodule

Output:
 8.
Design Verilog program for implementing various types of Flip-Flops such
as SR, JK and D

D Flip Flop:
module DFF(D,Q,QB,CLK,RST);
input D, CLK, RST;
output Q, QB;
reg Q, QB;
always @(posedge CLK)
begin
if(RST) Q <= 0; // for synchronous reset
else
begin
case(D)
0: Q <= 0;
1: Q <= 1;
endcase
end
assign QB = ~Q;
end
endmodule

SR Flip Flop:

module SRFF(S,R,Q,QB,CLK,RST);
input S, R, CLK, RST;
output Q, QB;
reg Q, QB;
always @(posedge CLK)
begin
if(RST) Q <= 0; // for synchronous reset
else
begin
case({S,R})
2'b00: Q <= Q; // No change
2'b01: Q <= 0;
2'b10: Q <= 1;
2'b11: Q <= 1'bx; // Invalid
endcase
end
assign QB = ~Q;
 end
endmodule

JK Flipflop:
module JKFF(J,K,Q,QB,CLK,RST);
input J, K, CLK, RST;
output Q, QB;
reg Q, QB;
always @(posedge CLK)
begin
if(RST) Q <= 0; // for synchronous reset
else
begin
case({J,K})
2'b00: Q <= Q; // No change
2'b01: Q <= 0;
2'b10: Q <= 1;
2'b11: Q <= ~Q; // Toggle
endcase
end
assign QB = ~Q;
end
endmodule
Output:
JK FLIP-FLOP

SR FLIP-FLOP

D FLIP-FLOP
 9. Develop an ALP to multiply two 16-bit binary
numbers.

AREA MULTIPLY, CODE, READONLY

ENTRY ; Mark first instruction to execute
START
MOV r1,#6400 ;STORE 6400 IN R1
MOV r2,#3200 ;STORE 3200 IN R1
MUL r3,r1,r2 ;THE RESULT STORED IN R3
NOP
NOP ;NO OPERATION
END

Output :
 10.
Develop an ALP to find the sum of first 10
integer numbers.
AREA SUM10, CODE, READONLY
ENTRY ; Define the entry point of the program
START ; Label for the start of the program
MOV r0,#10 ; Initialize register r0 with the value 10
MOV r1,r0 ; Copy the value of r0 to r1 (r1 = 10)
RPT ; Label for the start of the loop
SUBS r1,r1,#1 ; Decrement r1 by 1 (r1 = r1 - 1) and set flags
CMP r1,#0 ; Compare r1 with 0
BEQ STOP ; If r1 is equal to 0, branch to the STOP label
ADD r3,r0,r1 ; Add the values of r0 and r1 and store the result in r3
MOV r0,r3 ; Update r0 with the new sum (r0 = r3)
BNE RPT ; If the result of the subtraction (r1 - 1) is not zero, branch back
to RPT
NOP ; No operation (do nothing)
NOP
STOP
END ; End of the program

Output :

11. Simulate a program in ALP for ARM microcontroller

to find factorial of a number.
 AREA FACT,CODE,READONLY
ENTRY ; Define the entry point of the program
START ; Label for the start of the program
MOV R0,#7 ; Initialize register R0 with the value 7 (input for factorial
calculation)
MOV R1,R0 ; Copy the value of R0 to R1 (R1 = 7)
RPT ; Label for the start of the loop
SUBS R1,R1,#1 ; Decrement R1 by 1 (R1 = R1 - 1) and set flags
CMP R1,#0 ; Compare R1 with 0
BEQ STOP ; If R1 is equal to 0, branch to the STOP label (exit loop when
R1 reaches 0)
MUL R2,R0,R1 ; Multiply the values of R0 and R1 and store the result in
R2 (calculate factorial)
MOV R0,R2 ; Update R0 with the new result (R0 = R2, accumulate
factorial result)
BNE RPT ; If the result of the subtraction (R1 - 1) is not zero, branch back
to RPT (loop
until R1 reaches 0)
STOP
END ; End of the program

Output :
 12.
Develop an ALP to find the largest/smallest
number in an array of 32 numbers.

1) SMALLEST:
AREA SMALLEST, CODE,READONLY
ENTRY ; Define the entry point of the program
START ; Label for the start of the program
MOV R5,#6 ; Initialize register R5 with the value 6
(number of elements in the array)
LDR R1,=VALUE1 ; Load the address of the VALUE1 array into
register R1
LDR R2,[R1],#4 ; Load the first element of the array into
register R2 (initial smallest value)
LOOP ; Label for the start of the loop
LDR R4,[R1],#4 ; Load the next element of the array into
register R4
CMP R2,R4 ; Compare the current smallest value (R2) with the
new value (R4)
BLS LOOP1 ; If the new value is smaller, branch to LOOP1
(update smallest value)
MOV R2,R4 ; Update the smallest value (R2) with the new
value (R4)
LOOP1 ; Label for the continuation of the loop
SUBS R5,R5,#1 ; Decrement the counter (R5) by 1 and set
flags
CMP R5,#0 ; Compare the counter (R5) with 0
BNE LOOP ; If the counter is not zero, branch back to LOOP
(loop until all elements are
processed)
LDR R4,=RESULT ; Load the address of the RESULT variable
into register R4
STR R2,[R4] ; Store the smallest value (R2) into the RESULT
variable
BACK B BACK ; Infinite loop to prevent the program from
terminating (not necessary in
this case)

VALUE1 ; Label for the array of values

DCD 0X44444444
DCD 0X22222222
DCD 0X11111111
DCD 0X33333333
 DCD 0XAAAAAAAA
DCD 0X88888888
DCD 0X99999999 ; Define the array of values

AREA DATA2, DATA,READWRITE

RESULT DCD 0X0 ; Define the RESULT variable and initialize it to

0
END ; End of the program

MEMORY:-
*Memory before execution:
*Memory after execution :

2) LARGEST:
AREA LARGEST, CODE,READONLY
ENTRY ; Define the entry point of the program
START ; Label for the start of the program
MOV R5,#6 ; Initialize register R5 with the value 6 (number of
elements in the array)
LDR R1,=VALUE1 ; Load the address of the VALUE1 array into
register R1
LDR R2,[R1],#4 ; Load the first element of the array into register R2
(initial smallest value)
LOOP ; Label for the start of the loop
LDR R4,[R1],#4 ; Load the next element of the array into register R4
CMP R2,R4 ; Compare the current smallest value (R2) with the new
value (R4)
BHI LOOP1 ; If the new value is higher, branch to LOOP1 (update
largest value)
MOV R2,R4 ; Update the smallest value (R2) with the new value (R4)
LOOP1 ; Label for the continuation of the loop
SUBS R5,R5,#1 ; Decrement the counter (R5) by 1 and set flags
CMP R5,#0 ; Compare the counter (R5) with 0
BNE LOOP ; If the counter is not zero, branch back to LOOP (loop
until all elements are
processed)
LDR R4,=RESULT ; Load the address of the RESULT variable into
register R4
STR R2,[R4] ; Store the smallest value (R2) into the RESULT
variable
BACK B BACK ; Infinite loop to prevent the program from terminating (not
necessary in this case)

VALUE1 ; Label for the array of values

DCD 0X44444444
DCD 0X22222222
 DCD 0X11111111
DCD 0X33333333
DCD 0XAAAAAAAA
DCD 0X88888888
DCD 0X99999999 ; Define the array of values

AREA DATA2, DATA,READWRITE

RESULT DCD 0X0 ; Define the RESULT variable and initialize it to 0
END ; End of the program

MEMORY:-*Memory before execution:

*Memory after execution :