DEPARTMENT OF ELECTRICAL AND COMPUTER

ENGINEERING

Digital System Design LAB_6

LAB Report

Submitted by:
Name: Mohib Haroon
Reg # B20F0440EE030

Submitted to:

Name: Engineer Rafiullah

Date:
 Lab 06

Implementation of Combinational Circuit using Verilog

Objective

• To Implement and verify the operation of Combinational circuit using Verilog HDL

Software / Equipment Requirement

• Xilinx ISE

Task 1:
Implement Half adder module and then instantiate half adder module for implementation of Full
adder module. Write Test bench module and verify your output.

Circuit Diagram:

Verilog Code:

Half Adder

module half_adder (

input a,b,

output sum,carry

);

assign sum = a ^ b;

assign carry = a & b;

endmodule
Full Adder:

module full_adder(

input a,b,cin,

output sum,carry

);

wire c,c1,s;

half_adder ha0(a,b,s,c);

half_adder ha1(cin,s,sum,c1);

assign carry = c | c1 ;

endmodule

Output:

Synthesized Hardware:
Task 2:
Multiple full adder circuits can cascade in parallel to add an N-bit number. For an N- bit parallel
adder, there must be N number of full adder circuits. Implement 4-bit parallel adder using Verilog.
Write Test bench module and verify your output.

Circuit Diagram:

Verilog Code:

Full adder:

module full_adder(a,b,ic,o,oc);

input a,b,ic;

output o,oc;

assign o = (~ic & ((a & ~b) | (~a & b)) ) | (ic & ~((a & ~b) | (~a & b)) );
assign oc = (a & b) | (b & ic) | (ic & a);

endmodule

Parallel Adder:

module parallel_adder(in1,in2,ic,out,oc);

input [3:0]in1;

input [3:0]in2;

input ic;

output [3:0]out;

output [3:0]oc;

full_adder fa1(in1[0],in2[0],ic,out[0],oc[0]);

full_adder fa2(in1[1],in2[1],oc[0],out[1],oc[1]);

full_adder fa3(in1[2],in2[2],oc[1],out[2],oc[2]);

full_adder fa4(in1[3],in2[3],oc[2],out[3],oc[3]);

endmodule
Output:

Synthesized Hardware:

Task 3:
Design an Arithmetic and Logic Unit (ALU) that implements 8 functions as described in Table.

The 4-bit ALU has the following inputs:

• A: 4-bit input
• B: 4-bit input
• Cin: 1-bit input
• Output: 4-bit output
• Cout: 1-bit output
• Control: 3-bit control input.
The following points should be taken care of:
 • Use a case statement (or a similar ‘combinational’ statement) that checks the input
combination of “Code” and
• acts on A, B, and Cin as described in Table 1.
• The above circuit is completely combinational. The output should change as soon as the
code combination or
• any of the input changes.
• You can use arithmetic and logical operators to realize your design.
Simulate this circuit and verify the inputs and observe outputs on the waveform window by
writing test bench.

(Note* The ROL instruction shifts each bit to the left, with the highest bit copied in the Carry flag
and into the lowest bit. The ROR instruction shifts each bit to the right, with the lowest bit copied
in the Carry flag and into the highest bit.)

Output:

Note that rotate and shift operations are only applied on input A.

Verilog Code:

module ALU_4bit(input [3:0] A, input [3:0] B,input Cin,input [2:0] S, output reg [3:0]
Result,output reg Cout );

always @(*) begin

case (S)

3'b000: begin // Addition

Result = A + B + Cin;

Cout = Result[3];

end

3'b001: begin // Subtraction

Result = A - B - Cin;

Cout = ~Result[3]; //

end

3'b010: Result = A | B; // Logical OR

3'b011: Result = A & B; // Logical AND

3'b100: begin // Shift Left

Result = {A[2:0], 0}; // Shift A by 1 bit to the left

Cout = A[3]; // Carry-out is the MSB of A

3'b101: begin // Shift Right (Logical)

Result = {0, A[3:1]}; // Shift A by 1 bit to the right

Cout = A[0]; // Carry-out is the LSB of A

end

3'b110: begin // Rotate Left

Result = {A[2:0], A[3]}; // Rotate A by 1 bit to the left

Cout = A[3]; // Carry-out is the old MSB of A

end

3'b111: begin // Rotate Right

Result = {A[0], A[3:1]}; // Rotate A by 1 bit to the right

Cout = A[0]; // Carry-out is the old LSB of A

end

default: Result = 4'b0000; // Default to zero for other OP values

endcase

end

endmodule

Results:
Synthesized hardware:

Conclusion

In this laboratory session, we delved into the fundamental concepts of digital circuit design and
arithmetic logic, with a focus on the implementation of a parallel adder, full adder, and half
adder using instantiation in Verilog.
1. Parallel Adder Implementation: The construction of a parallel adder allowed us to
explore the efficient addition of multiple bits in parallel. This foundational concept is
crucial for understanding the design of more complex digital systems and processors.
2. Full Adder Using Half Adders: By implementing a full adder using instantiated half
adders, we gained insights into the modularity and reusability of digital components. This
hierarchical design approach not only simplified the full adder implementation but also
highlighted the significance of breaking down complex systems into manageable
subcomponents.
3. Arithmetic Logic Unit (ALU) Integration: The integration of the parallel adder, full
adder, and half adder within an Arithmetic Logic Unit (ALU) framework demonstrated the
practical application of these components in real-world digital systems. This hands-on
experience enhanced our understanding of ALU operations, including addition,
subtraction, logical operations, and bit manipulation