INDEX

Chapter Page No

ABSTRACT III
LIST OF FIGURES IV
LIST OF TABLES V
LIST OF ABBREVIATIONS VI
1. INTRODUCTION 1

1.1 INTRODUCTION 1

2. LITERATURE SURVEY 5

3. INTRODUCTION OF VLSI 7

3.1 OVERVIEW 7

3.2 WHAT IS VLSI 8

3.3 HISTORY OF SCALE INTEGRATION 8

3.4 ADVANTAGES OF INTEGRATED CIRCUITS OVER DISCRETE COMPONENTS 9

3.5 VLSI AND SYSTEMS 9

3.6 APPLICATIONS OF VLSI 10

4. THE XILINX IP CORE 12

5. FINITE IMPULSE RESPONSE FILTER 18

6 .FILTER DESIGN AND FILTER COEFFICIENT

6.1 FIR filter design

6.2. Acquisition of FIR filter coefficients

I
7. FIR FILTER IP CONFIGURATION

8. VERIFICATION AND ANALYSIS

9. CONCLUSION AND FUTURE SCOPE 44

CONCLUSION 44

FUTURE SCOPE 44

10. BIBILOGRAPHY 45

II
 ABSTRACT

In order to accurately calculate the effective value of voltage and current, it is necessary to filter out the
harmonics in voltage and current signals in the process of developing power RTU with Zynq-7000 series
FPGA. This discusses the use of the Xilinx FIR IP core to achieve this filtering function. Firstly, we use
FDA tool to design a 50 Hz band-pass filter, analyze the frequency characteristics of the filter, and then
quantize the FIR filter coefficients generated by MATLAB tool by calculating the quantization word length,
and then import the quantized filter coefficients into the FIR IP core.

Finally, the realization and Optimization of the IP core are completed by setting the relevant parameters.
This method simplifies the design process and makes the realization of the filter easier. The simulation
results of MATLAB and FPGA show that the filtering effect is consistent, and the FIR filter consumes
fewer resources than the Fourier Algorithm

This study focuses using the Zynq-7000 series FPGA for accurate calculation of voltage and current
effective values. To achieve this, we employ the Xilinx FIR IP core for harmonic filtering. Initially, a 50 Hz
band-pass filter is designed using an FDA tool, and its frequency characteristics are analyzed. The FIR filter
coefficients generated by MATLAB are quantized to determine the necessary word length for digital
representation. These quantized coefficients are then imported into the FIR IP core. Realization and
optimization of the IP core are performed by configuring relevant parameters. This approach streamlines the
design process and facilitates filter implementation. Simulation results from MATLAB and FPGA
demonstrate consistent filtering performance, with the FIR filter exhibiting lower resource consumption
compared to the Fourier Algorithm.

III
 LIST OF FIGURES

FIGURE NO FIGURE NAME

Figure 1 Design of FIR filter index

Figure 2 Frequency response of fir filter

Figure 3 Eight-bit coefficient of FIR low pass

filter
Figure 4 Twelve-bit coefficient of FIR low
Pass Filter

Figure 5 Sixteen-bit coefficient of FIR Low

Pass Filter
Figure 6 No quantified coefficient of FIR low
Pass Filter

Figure 7 FIR IP Core Configuration

Figure 8 Functional verification block Diagram

Figure 9 Modular design diagram

Figure 10 Logic analyzer signal capture diagram

Figure 11 SysGen FIR filter design diagram

Figure 12 SysGen simulation results

IV
 LIST OF TABLES

TABLE NO TABLE NAME

Table 1 Filter Coefficient

Table 2 Resourse Usage Results

V
 LIST OF ABBREVATIONS

ASCII : American standard code for information interchange

DRE : Direct recording electronic

EVM : Electronic voting machine

FPGA : Field programming gate array

IEBC : Independent electoral and Boundaries commision

LRM : Language reherence manual

OVS : Online voting system

OVI : Open verilog international

SSI : Small scale integration

VI
 CHAPTER 1
INTRODUCTION

1.1 Introduction

In order to monitor and control the operation of 10kV power supply system of high-speed railway, RTU

(remote terminal unit) is set along the railway to collect and calculate real-time data such as current, voltage

and power. With the rapid development of microelectronics technology, the Zynq series FPGA products

produced by Xilinx company are gradually becoming the mainstream of high-performance system

development and design. It is a high-performance chip with an FPGA+arm structure. In this paper, we

consider to develop a new generation of high-performance and high integration RTU with the Zynq-7000

chip.The power supply line transmits 50 Hz AC power frequency. Due to the existence of nonlinear load and

electromagnetic interference, the measured voltage and current waveforms will be distorted, making the measured

signal may contain a large number of harmonics multiple than 50 Hz, such as 150Hz, 250Hz, 350Hz, etc. [1][1].

According to the national electricity detection standard, the effective value of voltage and current is for the

fundamental wave of 50 Hz, and the existence of harmonics will produce great errors.

There are many methods to filter out harmonics, and the commonly used methods are fast Fourier

transform (FFT) and digital finite filter (FIR). Compared with the traditional algorithm based on CPU, FFT and FIR

implemented on FPGA can achieve fast time response performance. Considering that FFT takes up more hardware

resources, this paper mainly discusses the method of FIR filtering.Xilinx company provides a Vivado platform

for the development of Zynq series products. The system has a large number of Xilinx IP cores with

different uses. The FIRI and IP cores are used to filter out the fundamental wave signal. The development

process is simple and convenient. Next, the design process and operation results of the filter are discussed and

verified by MATLAB simulation.

1
2
 CHAPTER 2
LITERATURE REVIEW

Ashwini Baligatti , Ashwini Desai, Dr. Uday Wali,[1] Free Area Estimator for
Simulated Annealing of VLSI Floor Plans, International Journal of Innovative
Research in Computer Science and Technology (IJIRCST), 2, no. 4, pp. 52-55 (2014).

Manoj Ojha, Rishi Sikka.[2] An Overview on Applications of Micro controller

International Journal of Innovative Research in Engineering & Management(IJIREM),
8, 152 Innovative Research Publication International Journal of Innovative Research
in Engineering & Management (IJIREM) no.6 (November. 2021): 402-405
doi:10.55524/ijirem.2021.8.6.87.

Foster, I., Kesselman, C., Nick, J., Tuecke, S[3] The Physiology of the Grid: an
Open Grid Services Architecture for Distributed Systems Integration. Technical
report,Global Grid Forum (2002) .

N.S.N. LAKSHMI PATHI RAJU, A.PRAVIN, N.S.MURTHY SHARMA,

S.S.KIRAN[4] A Novel Proposal On Implementation Of Polling Percentage
Improvement System Through Embedded Based Integration Of electronic Voting
Machine And Other Methodologies – IJ ETA ETS ISSN: 0974-3588 | JULY ‟12 –
DECEMBER ‟12 | Volume 5 : Issue 2 pp 1-5

Jeremy Clark, Aleks Essex and Carlisle Adams[5] “Secure and Observable
Auditing of Electronic Voting Systems using Stock Indices” 0840-7789/07/$25.00
©2007 IEEE

Leyou Zhang, Yupu Hu, Xu’an Tian and Yang Yang[6] “Novel Identity based
Blind Signature for Electronic Voting System” 978-0- 7695-3987-4/10 $26.00 © 2010
IEEE DOI 10.1109/ETCS.2010.198 4.

3
Ying Qiu and HuafeiZhu[7] ”Somewhat Secure Mobile Electronic-voting Systems
Based on theCutand-Choose Mechanism” 978-0-7695-3931-7/09 $26.00 © 2009
IEEE DOI 10.1109/CIS.2009.39.

Arun kumar. N and Arunkumar.P.L[8] “Analysis, Design & Real-Time

Implementation of Electronic Voting Machine”. 6. J. Paul Gibson, Eric Lallet, and
JeanLuc Raffy “Engineering a Distributed eVoting System Architecture: Meeting
Critical Requirements” H. Giese (Ed.): ISARCS 2010, LNCS 6150, pp. 89– 108,
2010.c_Springer-Verlag Berlin Heidelberg 2010. 153 Innovative Research
Publication.

4
 CHAPTER 3
INTRODUCTION OF VLSI

ICs are made by putting together on a single chip hundreds of transistor-based

circuits (VLSI). Semiconductor and communication technologies were at their peak in
the 1970s. VLSI architecture was made. A VLSI device is a microprocessor. The term
has lost some of its due to the fact that modern chips can contain hundreds of millions
of transistors.
3.1 Overview
Each of the first semiconductor chips contained a single transistor. For each
new advancement in technology, there was an increase of transistors available,
allowing for the integration of more individual functions or systems over time Few
components, perhaps ten or more, were used in the first integrated circuits, One or
more logic gates might be built on a single component thanks to this development.
Technology breakthroughs have led to devices and systems with hundreds of logic
gates and at least a thousand logic gates, respectively, prompting the coining of the
words "small-scale integration" (SSI) and "large-scale integration" (LSI) to define the
two forms of integration (LSI). The number of transistors and gates in today's
microprocessors exceeds this limit by a factor of 100 billion.

Large-scale integration levels above VLSI have been investigated for

identification and calibration. Large-scale integration has been referred to by both the
abbreviation "ULSI" and the more general "ULI" (ULSI). A detailed difference
between gates and transistors is no longer important due to the vast number of gates
and transistors accessible on ordinary devices. Higher-level integration terms, such as
VLSI, are no longer widely used. Given the widely held belief that all
microprocessors are VLSI or better, even VLSI has become quaint.
Intel's Montecito Itanium chip, for example, was commercially available in early 2008
and featured a billion transistors. During the transition from 65 nm to 45 nm
generation of semiconductor fabrication, This is predicted to become increasingly
common in the future (While facing new obstacles like greater process corner

5
variance.) NVIDIA's 280-series GPUs are another famous example. This teraflop
CPU's logic uses the majority of its 1.4 billion transistors (the transistor count of the
Itanium is largely due to the 24MB L3 cache). The growing use of design automation
and automated logic synthesis in current designs means that logic functionality may
be more complicated than before. To attain the maximum degree of performance,
some high-performance logic blocks, such as SRAM cells, are still manufactured by
hand (By sacrificing performance for stability, designers can bend or breach
established design norms).
3.2 What is VLSI?
VLSI is an acronym for "Very Large Scale Integration," which means that the
integration is occurring on a massive scale. More and more logic devices must be
squeezed into ever-tinier spaces in this area of study.
An integrated circuit is a single chip containing a number of transistors using
semiconductor material that has been changed, the design and production of
extremely small, complex circuitry An integrated circuit has millions of transistors,
each of which is only a few milli metres long (IC).Many different kinds of electrical
logic devices may benefit from this.

3.3 History of Scale Integration

late forties Bell Labs created the transistor in the late 1950s. The first IC (JK-
FF by Jack Kilby at TI)Small-Scale Integration in the 1960s (SSI) The late 1960s saw
the first chips with tens of transistors integrated onto a single silicon substrate (MSI)
Early 1970s: An integrated circuit containing several transistors. Integration on a
massive scale is necessary (LSI)
Early 1980s: An integrated circuit (IC) containing many transistors. VLSI Tens of
thousands of transistors may fit on a single silicon chip (later 100,000s & now
1,000,000s)
Occasionally, although seldom often, Ultra LSI is used for 1,000,000s.
The acronym SSI stands for "Small-Scale Integration" (0-102)
MSI is an abbreviation for Medium-Scale Integration (102-103)
Large-Scale Integration may be shortened to LSI (103-105)

6
The acronym "VLSI" stands for "Very Large-Scale Integration" (105-107)
">107" is shortened to "ULSI" (Ultra Large-Scale Integration).

3.4 Advantages of integrated circuits (ICs) over discrete components

It is critical to note that the entire system design is determined by the
characteristics of integrated circuits, notably by the types of components that can and
cannot be integrated into an integrated circuit. Utilizing integrated circuits in a system
has a number of benefits over using discrete components. Compared to discrete digital
circuits, integrated circuits have three major benefits:
Size. Integrated circuits are substantially smaller than discrete components.
which are measured in millimetres or centimetres. Transistors and wires are both
micrometre-sized. The parasitic resistances, capacitances, and inductances of smaller
components are lower, resulting in faster speeds and lower power consumption.
Speed. The speed at which signals inside a chip may transition from logic 0 to
logic 1 is much higher than the speed at which such transitions can occur between
chips. Due to the interconnected nature of the chips on a PCB, their data may travel at
speeds hundreds of times faster than those of a single chip. In on-chip circuitry,
Smaller components and wires have less parasitic capacitance, slowing the
transmission. Consumption of power. In addition, logic operations on a chip use a lot
less power with parasitic capacitance and resistance being smaller, the chip's
smallsize also means It saves electricity driving them.

3.5 VLSI and systems

 These advantages of integrated circuits are reflected in system benefits, which
are as follows:
 The size has been reduced. For example, the tiny size of portable TVs and
mobile phones provides a benefit in and of itself.
 Reduced usage of electrical power. Total power consumption can be reduced
by using a single chip in place of a few standard components. There are a
number of benefits to reducing power consumption power source that is both
more compact and cost-effective may be employed; One of the fans might be
removed. and a cabinet with less electromagnetic shielding may be possible.

7
  Cost reductions. Lower system costs can be achieved by cutting back
onsystem components such as power supply requirements and cabinet costs.
Although the cost of bespoke ICs may be higher than that of the commodity
components they are designed to replace, the system as a whole can be cheaper
because of the cascading effect of integration.
 Integration of IC manufacturing and digital system economics is necessary to
understand why integrated circuit technology has such a profound effect in
digital system design.

3.6 Applications of VLSI

 Cars have electronic systems.
 VCRs are controlled by digital electronics.
 ATM, or transaction processing system
 Workstations and personal computers
 Electronic medical systems.

In today's world, electronic systems are used to accomplish a wide range of

tasks. Many mechanical, hydraulic, and other mechanisms have been replaced by
electronic systems because They are smaller, more flexible, and less difficult to
maintain. Electronic systems have spawned whole new applications in certain
circumstances. Some of the functions performed by electronic systems are
immediately apparent, while others may be more obscure:
It takes a surprising amount of energy to run complex algorithms in personal
entertainment devices like MP3 players and DVD players.
Modern automobiles are controlled entirely by electronic systems, which
include stereo systems and displays, fuel injection systems, suspension adjustment for
different terrain, and anti-lock brake (ABS) system management, among other things.
High-definition video data rates can be compressed and decompressed in real time
using digital electronics.
Cheap Web surfing terminals, despite their niche, nonetheless need complex
electrical parts.Personal computers and workstations can be used to write documents,
look at finances, and play games. Computors have CPUs and other specialised

8
hardware for accessing discs quickly, displaying images on screens faster, and
performing other tasks.
Medical electronic systems use complex algorithms to monitor bodily functions and
identify abnormalities. As a result, rather than overwhelming customers, the
availability of these sophisticated systems actually increases demand for still more
sophisticated systems.
Integration circuits and electronic systems design and manufacturing are
becoming increasingly complex as application complexity rises.Perhaps the most
fascinating aspect of this collection is how diverse it is—instead of a few general-
purpose computers, As systems grow more complicated, we develop a more broad
selection of special-purpose systems to meet the demands of the market. Our
expanding experience in both integrated circuit manufacturing and design is reflected
in this, but rising customer needs are continuing to push the frontiers of design and
production even farther forward.

9
 CHAPTER 4
THE XILINX IP CORE

The Xilinx IP core refers to intellectual property (IP) cores provided by Xilinx, a leading provider of field-
programmable gate array (FPGA) and programmable logic device (PLD) solutions. These IP cores are pre-
designed modules that can be integrated into FPGA designs to add specific functionalities and accelerate
development.

Xilinx offers a wide range of IP cores covering various applications, including digital signal processing
(DSP), communication protocols, memory controllers, video processing, and more. These cores are
optimized for Xilinx FPGA platforms and are typically provided with configurable parameters to tailor their
behavior to specific project requirements.

Using Xilinx IP cores can significantly streamline the FPGA design process by providing ready-made
solutions for complex functionalities, reducing development time and effort. Additionally, Xilinx provides
tools and documentation to facilitate the integration and customization of these IP cores within FPGA
designs.

The FIR (Finite Impulse Response) IP core mentioned in the context of harmonic filtering is one example of
the many IP cores available from Xilinx. It provides functionality for implementing FIR filters in FPGA
designs, allowing engineers to perform tasks such as signal processing, filtering, and equalization efficiently
within the FPGA fabric. By leveraging Xilinx IP cores like the FIR IP core, developers can focus on higher-
level aspects of their designs while benefiting from optimized and reliable implementations of specific
functionalities.

The Xilinx FIR IP core is designed to implement finite impulse response (FIR) filters in FPGA designs. FIR filters
are widely used in signal processing applications for tasks such as smoothing, noise reduction, and frequency
selective filtering.

10
 The FIR IP core typically offers a range of configuration parameters to
customize the filter's behavior. These parameters may include filter order, coefficient
width, input and output data width, filter type (e.g., low-pass, high-pass, band-pass),
and other settings to adjust the filter's frequency response and performance
characteristics.

Xilinx FIR IP cores are designed for easy integration into FPGA designs using
Xilinx's Vivado Design Suite. They can be instantiated within FPGA designs using
HDL (Hardware Description Language) code or graphical design tools provided by
Vivado.

The FIR IP core is optimized for resource utilization within Xilinx FPGA
devices, ensuring efficient use of FPGA resources such as lookup tables (LUTs),
registers, and memory blocks. This optimization helps minimize the impact on overall
FPGA resource usage and can lead to more efficient designs.

Xilinx FIR IP cores are designed to deliver high-performance filtering

capabilities suitable for real-time signal processing applications. They leverage the
parallel processing capabilities of FPGAs to achieve high throughput and low latency
filtering operations.

Xilinx provides comprehensive documentation, user guides, and application

notes for the FIR IP core, helping developers understand its features, usage, and
integration into FPGA designs. Additionally, Xilinx offers technical support and
online forums where developers can seek assistance and collaborate with other users.

Xilinx FIR IP cores are rigorously tested and verified to ensure their
correctness and performance. Xilinx provides simulation models and testbenches to
facilitate verification of the FIR filter's functionality and performance within the FPGA
design environment. By leveraging the Xilinx FIR IP core, developers can implement
sophisticated filtering algorithms in FPGA-based signal processing applications with
ease and efficiency, ultimately accelerating time-to-market and reducing development
complexity.

CHAPTER 5
11
 The Finite Impulse Response (FIR) filter

The term "finite impulse response" refers to the fact that the filter's output response to
any input signal is of finite duration, determined by the length of the filter's impulse
response. FIR filters operate by convolving the input signal with a finite-length

FIR filters exhibit linear and time-invariant characteristics, meaning they obey the
principles of superposition and scaling, and their behavior does not change over time.
FIR filters are inherently stable, meaning they do not exhibit oscillatory or unstable
behavior, regardless of the input signal or filter coefficients.

FIR filters generally provide linear phase response, preserving the phase relationships
within the input signal across different frequency components.The frequency response
of an FIR filter is determined by the coefficients of the filter kernel, allowing for
flexible shaping of the frequency characteristics such as low-pass, high-pass, band-
pass, or band-stop filtering.

The Finite Impulse Response (FIR) filter is a digital filter with a finite
duration response to an input signal. Unlike its counterpart, the Infinite Impulse
Response (IIR) filter, the FIR filter does not rely on feedback loops, which makes it
inherently stable and easier to design. FIR filters are characterized by their linear
phase response, making them particularly useful in applications where phase distortion
must be minimized, such as in audio and communication systems.

Designing an FIR filter involves selecting appropriate filter coefficients to

achieve the desired frequency response. One common method is the windowing
approach, where a desired frequency response is multiplied by a window function in
the frequency domain to obtain the filter coefficients. Another popular method is the
Parks-McClellan algorithm, also known as the Remez Exchange Algorithm, which
optimizes the filter coefficients to minimize ripple in the passband and stopband.

FIR filters find applications in various domains, including digital signal processing,
12
telecommunications, audio processing, and biomedical signal analysis. In
telecommunications, FIR filters are used for tasks such as channel equalization and
pulse shaping. In audio processing, they are employed for tasks like equalization, noise
cancellation, and speaker/headphone calibration. Additionally, FIR filters are utilized
in biomedical signal analysis for tasks such as filtering out noise and artifacts from
physiological signals.

In terms of implementation, FIR filters can be realized using different structures, such
as direct-form, parallel, or cascade forms, depending on factors such as resource
constraints and performance requirements. FPGA platforms, such as those offered by
Xilinx, provide dedicated FIR IP cores that enable efficient implementation of FIR
filters in hardware, allowing for real-time processing of signals in embedded systems
and digital signal processing applications.

One common approach to designing FIR filters is the windowing method,

where the desired frequency response is multiplied by a window function in the
frequency domain to obtain the filter coefficients. This algorithm optimizes the filter
coefficients to minimize the maximum ripple in the passband and stopband of the
filter's frequency response .FIR filters can be implemented using direct-form structures
such as the tapped delay line structure, where each tap represents a delay element and
a coefficient multiplier.

FIR filters can also be implemented in parallel or cascade forms to

optimize resource utilization and achieve higher throughput in FPGA or ASIC
implementations. Xilinx provides IP cores specifically designed for implementing FIR
filters on their FPGA platforms, offering configurable parameters for filter
characteristics.

13
 CHAPTER 6

FILTER DESIGN AND FILTER COEFFICIENT

6.1 FIR Filter Design

First, we discuss the principle of FIR filter. The transfer function and difference equation of
FIR system with length (tap number) N are shown in equations (1.1) - (1.2).From the formula,
we can see that the essence of FIR filter is to multiply the input signal sequence and filter
coefficients, and then accumulate the results. The performance of the filter is mainly reflected
in the establishment of filter coefficients.

The number of filter coefficients is also known as the order of the filter. The
more the order is, the more calculation times will be, and the more FPGA resources will be
consumed, which will be more accurate relative to the filtering results. Therefore, the value of
the order of the filter has a great impact on the whole design.from the formula, we can see that
the essence of FIR filter is to multiply the input signal sequence and filter coefficients, and then
accumulate the results.

The performance of the filter is mainly reflected in the establishment of filter

coefficients. The number of filter coefficients is also known as the order of the filter. The
more the order is, the more calculation times will be, and the more FPGA resources will be
consumed, which will be more accurate relative to the filtering results.

Therefore, the value of the order of the filter has a great impact on the whole
design. Considering that the fundamental frequency that we want to filter out is 50 Hz, the
filtered harmonic frequency is an integral multiple of the fundamental frequency, which is in
different frequency bands. Therefore, the stopband cut off frequency is 10Hz, the passband
starting frequency is 40Hz, the passband cutoff frequency is 60Hz, the stopband starting
frequency is 100Hz, the stopband attenuation is - 20db, the window function is selected as
Kaiser window, and the frequency deviation caused by quantization word length is set to less
than 0.001. The RTU sets the sampling frequency to 1600Hz, so the sampling frequency of
the filter Fs=1600Hz. The order of the designed filter is 63.

N 1

14
Fig. 1 Design of FIR filter index

Fig. 2 Frequency response of fir filter

15
6.2 Acquisition of FIR filter coefficients

When FPGA uses filter coefficients, it needs to convert decimals into fixed-point numbers, which
requires the use of coefficient quantization function in FDAtool to achieve this purpose [5]. This
part needs to consider the influence of coefficient quantization on the frequency characteristics of
the filter. The quantization word length is a part of the coefficient quantization, and its value
directly affects the frequency characteristics of the filter, thus causing interference to the output of
the filter. Therefore, the more accurate the quantization word length is, the smaller the final output
error of the filter will be. According to the design index, the frequency characteristic deviation
caused by quantization error should not exceed 0.001[6], so according to the quantization word
length formulav

(N 1)2b / 2  0.001

When N = 63 is brought into the calculation, b > = 15 is obtained. It can be seen that the
quantization word length of the filter is at least 15.

Note: N is the order of the filter, b is the quantization word length.

The following is a comparison of different frequency characteristic graphs generated by different

quantization word length through FDAtool. The quantization effect of filter coefficients at the filter
zero position is shown in Fig.3-6. In the case of unquantization, the zeros on the unit circle are
dense, but the zeros are still spread in the z plane [7]. The zero-point on the unit circle mainly
forms the stopband attenuation, but the zero-point on the unit circle which is not conjugate
reciprocal position mainly forms the passband characteristic.

16
Fig. 3. Eight-bit coefficient of FIR low pass filter

Fig. 4 Twelve-bit coefficient of FIR low pass filter

17
Fig. 5 Sixteen-bit coefficient of FIR low pass filter

Fig. 6 No quantified coefficient of FIR low pass filter

18
As shown in Fig.5, for the 16-bit wide quantization effect diagram, there is hardly any
movement of the zero-point position; in Fig.4, for the 12-bit wide quantization effect
diagram, there is a small amount of movement of the zero-point position; as shown in
Fig.3, for the 8-bit wide quantization effect diagram, several zeros move out of the unit
circle in pairs to the position of the conjugate reciprocal.

Finally, the conclusion is drawn that when the quantization word length is too short, the
frequency characteristic error is too large, and the zero-pole drift is abnormal. It can be
seen that taking the quantization word length more than 15 bits has little influence on the
various characteristics of the filter. In order to facilitate the final FIR IP core to call the
coefficient file, 16-bit quantization word length is selected.

To view the filter coefficients generated by FDAtool:

Table-1 Filter Coefficient

19
 The filter coefficients generated by the FDAtool are a series of decimal numbers in
the second column of the above table. After quantization, h(n)*216 is obtained.
Finally, the quantized coefficient (16-bits) is converted into hexadecimal fixed-point
data and used by FIR IP_CORE.

20
 CHAPTER 7

FIR FILTER IP CONFIGURATION

Vivado development software provides Xilinx FIR IP for free. This IP core is
verified and tested by a large number of digital signal processing professionals to
ensure its correctness. With the development of generations of developers, its general
effect and various functions are very perfect. Compared with other design methods,
using the IP core to design FIR filter is more convenient[8]. FIR IP core configuration
is shown in the figure.

Fig. 7 Fir IP Core Configuration

21
 The filter coefficients can be obtained by calculation or by calling the .coe file.
The IP core provides the coefficient overload function. The filter types can be single
rate filter, interpolation filter, decimation filter, etc.When the system interpolates the
input signal by N times, N images will appear in the spectrum, so a filter is needed to
filter the image frequency. Interpolation filter is usually
In this paper, we choose to use a single rate filter structure. The single rate FIR
filter is the simplest finite impulse response filter. The so-called single rate FIR filter
means that the input sampling frequency is equal to the output sampling frequency.
FIR compiler IP core to achieve this type of filter is mainly to calculate the
convolution sum, as shown in the following formula

Where N is the number of filter coefficients.

The clock frequency of FIR filter system is selected as 100M, and the input sampling
frequency can be selected as the frequency mode, then the input data is input into the
IP core according to this sampling frequency; if the selected frequency mode is the
output sampling frequency, the output data is output according to this frequency.

FIR compiler IP core provides four quantization options: integer

coefficient, quantization only, maximum dynamic range and optimal precision
decimal length. The coe coefficient file is imported into the IP core for use. The
integer coefficient is selected as the coefficient quantization option by default.The
output of the FIR compiler IP core can be set to full precision, and the output data bit
width is the sum of the input data bit width and the added value of the bit width when
filtering according to the filter coefficient. The increase of bit width is caused by the
multiplication and accumulation operation to realize the basic filtering function. The
upper limit of the increase in bit width is the result of rounding up the base- 2
logarithm of the nonzero multiplicative operands plus the system bit width.

22
 Where N is the tap number of filter coefficients, ai is the coefficient value, and B is
the bit width increase value. For the FIR compiler implemented with MAC structure,
the bit width increment is calculated automatically according to the actual
coefficients.

FIR compiler IP core provides optimization options: speed option,

custom option, area option. In some configurations, the maximum possible speed
needs to be at the expense of overall resource utilization. The speed option selects all
the possible optimization objectives supported by the kernel, and consumes the most
resources to achieve the maximum speed; the custom option selects the optimization
objectives by the user and displays them in the form of a list, which can provide more
accurate control on the critical path to achieve the specific goal; the area option turns
off the optimal function.

User-defined functions can be selected from the list. The functions are as follows:

Data_ Path_ Fanout: adding registers to the data storage side can minimize fan out.

Pre-Adder_ Pipeline: when large width coefficients are used, pipeline pre adders are
implemented.

Coefficient_ Fanout: adding pipelined registers to the coefficient storage side

minimizes fan outs. It is effective when using parallel channel or large data width
filter.

Control_ Path_ Fanout: add pipelined registers to the control logic unit when using
parallel channels.

Control_ Column_ Fanout: when the dsp processor is used to implement the filter, the
pipeline register is added to the control logic unit.
.

23
Control_ Broadcast_ Fanout: add pipeline register in control logic unit to implement
parallel symmetric filter.

Control_ LUT_ Pipeline: realize the look-up table method of advanced control logic
channel sequence.

Optimal_ Column_ Length: when the implementation of asymmetric filter requires

multiple dsp processors, the processing speed of partitioned dsp reaches the
maximum.

Disable_ Half_ Band_ Center_ Tap: when this option is selected, a dsp chip is used to
implement the central tap.

Table-2 Resource Result

The table above shows the resource usage in the report of Vivado software and
obtains the number of logical resources.

Occupied by the three optimization modes. We can know that the area mode takes the
least resources, the speed mode takes the most, and the custom mode can take into
account the requirements of resources and speed training. Custom mode list selection:
Data_Path_Fanout,,Pre-Adder_Pipeline,,Coefficient_Fanout. Adding registers on the
data storage side can effectively reduce the fan-out to minimize the delay of data
transmission, and FIR timing can be well controlled.

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Using the custom mode, you can define the list options that need to be optimized, and
select the appropriate hardware resources according to the parameter settings.
Therefore, when speed is the most important factor, speed mode is the best choice;
when the requirement of data processing speed is not high, area mode can be selected.
In general, according to the custom mode, it is more flexible, which can take into
account the requirements of resource occupation and speed.

The output of the FIR compiler IP core can be set to full precision, and the output data
bit width is the sum of the input data bit width and the added value of the bit width
when filtering according to the filter coefficient. The increase of bit width is caused
by the multiplication and accumulation operation to realize the basic filtering
function. The upper limit of the increase in bit width is the result of rounding up the
base- 2 logarithm of the nonzero multiplicative operands plus the system bit width.

The filter coefficient type selects a signed type with a coefficient width of 16bit, and
the FIR compiler IP core offers four quantization options: integer coefficient,
quantification only, maximizing dynamic range, and optimal precision scale. Using
the coe coefficient file for import into the IP core, the coefficient quantification option
selects the integer factor by default. The custom mode can take into account the
requirements of resources and speed training. Custom mode list selection:
Data_Path_Fanout,,Pre-Adder_Pipeline,,Coefficient_Fanout. Adding registers on the
data storage side can effectively reduce the fan-out to minimize the delay of data
transmission, and FIR timing can be well controlled.

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 CHAPTER 8

VERIFICATION AND ANALYSIS

In this paper, block design is used in Vivado software for module design, and the
simulation results are compared with MATLAB software. The verification diagram is
shown in Fig.8

Fig. 8 Functional verification block diagram

The functional verification block diagram of FIR filter is shown in the figure. The sine waves of 50
Hz, 100 Hz, 150 Hz and 200 Hz are generated through the dds signal generator module to simulate
the fundamental wave and the second, third and fourth harmonic signals in the line. The
fundamental signal is filtered out by a digital filter .

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Fig. 9 Modular design diagram

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 Vivado provides the ability to tag any network at different stages of design. The
hardware logic analyzer allows the designer to access the internal signal to realize
hardware debugging without the need to lead out the internal logic through FPGA
pins.

Fig.10 Logic analyzer signal capture diagram

As shown in FIG.10, ILA (logic analyzer) can grab internal signal after writing in-situ process
sequence on FPGA, set trigger signal as FIR IP core, output effective signal, connect FIR output
and input signal on ILA core, and then realize hardware debugging after burning program, signal
capture situation of ILA can be seen, as shown in the following figure:

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c modeling software embedded in MATLAB Simulink. The FIR filter is modeled by SysGen to verify
the reliability of the design. Using the sine signal generator as excitation, the FIR filter model is
constructed, as shown in FIG. 11

Fig. 11 SysGen FIR filter design diagram

Certainly! System Generator (SysGen) is a tool provided by Xilinx for designing and implementing
digital signal processing (DSP) systems on Xilinx FPGAs. It's part of the Xilinx's Vivado Design
Suite and is commonly used for designing and implementing complex digital signal processing
algorithms in FPGA-based systems.

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 The system built by SysGen is simulated. The simulation results are shown in FIG. 12

Fig. 12 SysGen simulation results

In Vivado software, the implementation of FIR filter IP core can filter out the high-
order harmonic components and leave the waveform of fundamental frequency.
Compared with MATLAB simulation software, the reliability of the results is verified.

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 CHAPTER 9
CONCLUSION AND FUTURE SCOPE

CONCLUSION

In this project, based on the Xilinx IP core method, the FIR filter is designed and
implemented on the FPGA of the Zynq- 7000 platform. The function of filtering fundamental wave
and eliminating harmonic in RTU electric quantity measurement is completed. The correctness of
the filtering function is verified by MATLAB simulation. The implementation method can greatly
shorten the research and development cycle, reduce the cost, and select the appropriate hardware
resources and data processing rate according to the parameter settings.

FUTURE SCOPE

Implementing an FIR filter using Xilinx IP core involves several steps, including generating
the FIR filter IP core, integrating it into your FPGA design, configuring it according to your
specifications, connecting it to other components of your design, synthesizing, implementing, and
generating the bitstream for your FPGA. Xilinx's tools such as Vivado and System Generator offer
graphical environments and libraries of blocks to facilitate this process. Once implemented, the FIR
filter can be used for various signal processing applications, offering real-time filtering capabilities
on Xilinx FPGAs.

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 CHAPTER 10
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