International Scholarly Research Network

ISRN Electronics
Volume 2012, Article ID 538597, 10 pages
doi:10.5402/2012/538597

Review Article
Sigma-Delta Modulation Based Digital Filter Design
Techniques in FPGA

Tayab Memon, Paul Beckett, and Amin Z. Sadik

School of Electrical and Computer Engineering, RMIT University, Melbourne, VIC 3001, Australia

Correspondence should be addressed to Tayab Memon, tayab.memon@rmit.edu.au

Received 15 August 2012; Accepted 8 October 2012

Academic Editors: T. Laopoulos and V. McGahay

Copyright © 2012 Tayab Memon et al. This is an open access article distributed under the Creative Commons Attribution License,
which permits unrestricted use, distribution, and reproduction in any medium, provided the original work is properly cited.

In this paper efficient digital filter design techniques categorized as sigma-delta modulation based short word length (SWL) and
multibit (or contemporary) techniques are reviewed in terms of hardware complexity, area, performance and power tradeoffs,
synthesis issues, and algorithm versatility. More recent, general purpose DSP applications including classical LMS algorithms
reported using sigma-delta modulation encoding are reviewed thoroughly. A small number of basic arithmetic circuits designed
using sigma-delta modulation encoding and synthesized by using FPGAs are also described. Finally, recent FPGA based area-
performance-power analysis of single-bit ternary FIR filtering is discussed and compared to its corresponding multi-bit system.
This work shows that in most cases single-bit ternary FIR-like filters are able to outperform their equivalent multi-bit filters in
terms of area, power, and performance.

1. Introduction However, there is a direct tradeoff between chip area

and throughput in these devices. Some obvious applications
It is no surprise that many signal processing tasks can be that require fast and efficient digital filters are decimation
accomplished by a microprocessor or a digital signal pro- filters, audio filter banks, charge-coupled-device filters, and
cessor (commonly called DSP kits). Built-in multiplication software defined radio, all of which require high through-
modules are the core element of these devices. Further- put. To achieve fast and efficient implementations, many
more, implementation of multiply and accumulate (MAC) techniques have been proposed. The overarching theme of
circuits within signal processors can significantly improve these techniques has been to reduce the complexity of the
the throughput of FIR and IIR digital filters structures (see multiplication process in any possible way. One method of
Figures 1 and 2) that require a large number of multiply and reducing the complexity of the multiplier is to reduce the
accumulation operations per a sampling period. word length in both the input and the filter coefficients. A
An alternative solution is to use gate-level programmable preferred approach is to utilize the sigma-delta modulation
devices such as field programmable gate arrays (FPGAs) to to reduce the word length; this paper focuses on these meth-
perform the digital filtering tasks. Concurrent (i.e., parallel) ods. There are many techniques that use some form of sigma-
mode of operations of these devices is of great interest as it delta modulation or the like to improve the efficiency of the
can improve the throughput of the digital signal processing digital filtering operations. Examples of such techniques were
circuits especially digital filtering modules. This higher reported in [1–9]. In this paper we thoroughly examine the
throughput can be achieved at the cost of a higher chip area design and synthesis of such techniques including general
compared to the serial implementation of the circuits. purpose short word length (SWL) DSP techniques and its
Many of these FPGA devices include a number of built- VLSI analysis in FPGA systems.
in multipliers that take up a large amount of silicon area The remainder of this paper proceeds as follows. Fast
within the device. Further, the most recent FPGA devices FIR filters are discussed in Section 2, followed by short word
include resources that easily support general purpose signal length (SWL) design techniques in Section 3. In Section 4,
processing tasks even within mid-range commercial devices. the VLSI analysis of sigma-delta modulation based general
2 ISRN Electronics

x(k) z −1 z −1 z −1 z −1 z −1 observed that the best tradeoffs between area-performance

and power can be achieved at an address length of four.
Many other techniques have been proposed: Canonical
h0 h1 h2 h3 hi−3 hi−2 hi−1 Sign Digit (CSD) [15], the Dempster Method [16], Mirror
Symmetric Filter Pairs [17], two-stage parallelism [18], and
Redundant Binary Schemes [19] to name just a few. Methods
Final adder tree specifically aimed at FPGA based FIR filter implementations
include the fully pipelined and full-parallel transposed form
[20], Add-and-Shift method with advanced calculation [21],
y(k) and hardware efficient distributed arithmetic for higher
Figure 1: General structure of FIR filter. orders [12, 13]. In [18], a new design technique based on
a linear phase prototype filter that exploits coefficient sym-
metry was shown to offer better performance at a hardware
x(k) + b0 + y(k)
cost similar to that of linear phase filters. Further, [18] also
described a transpose direct form with CSD multipliers that
z −1 offers better area-performance tradeoffs when using classical
methods.
+ a1 b1 + Apart from the classical multiplier complexity reduction
techniques, a new approach called Slice Reduction Graphs
z −1 (SRG) [20], which reduces area by minimizing the multiplier
block logic depth and pipeline registers, has been shown to
offer improved area-performance over the Reduced Adder
Graph (RAG) and Distributed Arithmetic (DA) techniques.
aN bM
In [20], simulations were carried out at coefficient bit widths
in the range of 2–20 bits, while keeping the order of the
Figure 2: Block Diagram of an IIR direct form II filter. filter constant (i.e., at 51). The order of the filter was then
varied in the range 10–250 at fixed coefficient bit widths.
The maximum average operating frequency achieved by the
purpose arithmetic modules and single-bit ternary FIR-like proposed technique was in the range of 175–180 MHz at the
filtering is covered. In Section 5, we describe a multibit lowest filter order, further reducing towards 150–160 MHz as
hardware-efficient FIR filter design techniques that can be the filter order increased above 60.
employed for single-bit purposes as well. Finally, we summa- The primary intent of the techniques mentioned above
rize and conclude the paper. has been to improve the area-performance characteristics of
parallel multibit binary filters operating at the Nyquist rate.
2. Fast FIR Filters However, it is obvious that the format of the coefficients and
input data is one reason for the high complexity of the MAC
Fast and efficient filters generally fall in two classes: sigma- stages. In [22–24], the complexity of the filter coefficients has
delta modulation (ΣΔM) based and optimization techniques been addressed by employing a simple single-bit coefficient
within a multibit format. A brief description of both these format. This technique can reduce the hardware complexity
methods is given below. of multipliers to simple AND-OR logic or small look-up
table (LUT) organizations. In the subsequent sections, we
2.1. FIR Filter Optimization Techniques. This section have discussed such techniques which utilize sigma-delta
describes input and coefficient encoding techniques that can modulation to reduce the complexity of digital filter MAC
be exploited to implement fast and efficient DSP algorithms section and improve the performance of those circuits.
in FPGAs. The techniques can be applied in either a single-bit
or multibit environment [10, 11]. 2.2. Sigma-Delta Modulation Based Fast Filters. Much work
As outlined above, it is the performance of the multiply- has been reported on the design and implementation
accumulate (MAC) stages that will have the greatest impact of the sigma-delta modulation based FIR and IIR filters
on the overall behaviour of digital filters. Thus, various filter encompassing various forms. The work that was commenced
design techniques have been proposed that specifically target by the authors in [22] and progressed by the ones in [8, 24]
the complexity of these stages. For example, distributed has been reported by many, such as in [1–4, 7, 25–28]. More
arithmetic is a common technique that has been used in recently sigma-delta modulation based bit-stream adder and
FPGA designs for many years [12, 13] in which the multi- multiplier modules have been described in [29, 30].
plication stages are performed using look-up tables (LUTs), In [4, 7, 25], efficient FPGA implementations of nar-
thereby reducing the overall size of the hardware. In [14], rowband FIR filters are achieved by simplifying the MAC
Systolic Distributed Arithmetic was used to improve the operation using a lower precision input to the filter. This
area-performance-power tradeoffs of a FIR filter design filtering operation requires that the input to the filter should
implemented on a Xilinx Virtex-E device at various filter be oversampled and requantized through the error feedback
orders but with a fixed coefficient bit width (i.e.,L = 8). It was ΣΔM as shown in Figure 3. In this case, a distributed
ISRN Electronics 3

Interpolation and z−1 z−1

y(k) x(k)
x(k) + zero padding

h0 hN −1
+
+
−
P(z) z−1 Adder

Prediction filter
Single-bit
Multibit Decoder
Figure 3: Block diagram of the error feedback ΣΔM for requanti-
zation.
y(k)

Figure 4: Block diagram of the FIR filter with ΣΔM modulated filter
arithmetic (DA) approach was used to design an error coefficients.
prediction FIR filter that has been placed in a negative
feedback path (see Figure 3). This prediction filter has a flat
pass band and a leading phase shift in the band of interest. Comb Comb R Baseband 4
filter filter 4 filter
The work also discusses the optimum prediction filter design
based on statistics and a minimum-mean-squared error
(MMSE) calculation. For a FIR filter input, only 3-4 bits Figure 5: Block diagram of the decoder used in a FIR filter with
in the requantizer output were processed as compared to ΣΔM modulated filter coefficients and with ΣΔM modulated input
signal.
the original 16-bit input bit-stream to the ΣΔM (i.e., re-
quantizer).
Overall, an efficient implementation of a narrowband
digital filter through a requantizing operation has shown a The decoder for this structure was identical to the one shown
50% reduction in logic resources as compared to a traditional in Figure 5. Signal encoding with sigma-delta modulation
FIR filter implementation using an FPGA. This filter shows a worked as an ADC and single-bit coder so there is no longer
great promise for FIR filter implementation. Further reduc- a requirement for a conventional ADC. Further, no input
tion in complexity can be gained through harsher requanti- interpolation is required in this setup as the signal passing
zation to lower precision words. through ΣΔM will be oversampled.
In [8, 24] fast and efficient FIR filters are presented. To perform the filtering operation, full precision filter
The authors discussed two sigma-delta filtering approaches. coefficients were zero padded by R to match the oversampling
In the first approach, FIR filter coefficients are encoded ratio of the ΣΔM. Decoder circuits comprising cascaded
using first-order sigma-delta modulator. Hence, the input to comb and baseband filters were used to remove the quanti-
the filter must be interpolated and zero-padded to R times zation noise and aliases from the filtered output signal. How-
the sampling frequency. An efficient two-step interpolation ever, the output signal was in a multibit format in all of these
process was proposed that required firstly interpolating the schemes.
original signal (xn ) by 4 times, at a sampling frequency of In [8] the authors also propose a fully sigma-delta
4 fN resulting in xo f . This signal (xo f ) was then upsampled modulated FIR filter. In this instance, it was recognized that
by R/4 times (R is the typical OSR) to give xn by appending the filter performs well if both the input and filter coefficients
zeros. The proposed structure is shown in Figure 4. The are sigma-delta encoded in a single-bit format. A simi-
decoder for this filter is used to reconstruct the original signal lar structure was utilized to that shown in Figure 4 except that
by resampling to the Nyquist rate and removing quantization the interpolator was replaced with a sigma-delta modulator.
noise by using a low pass filter and decimator. It was found using simulation that the design exhibits a flat
The use of cascaded comb filters as reported in [31] input spectrum in the Nyquist frequency range and the latter
was adopted to further simplify the decoder design whilst approach (Figure 6) performed well in comparison to the
removing any alias introduced into the system from the FIR former (Figure 5). This structure was found to further reduce
filter. Only two cascaded comb filters were used in this design the hardware complexity of the filter implementation.
(shown in Figure 5) because it was found that using more A ternary format has an extra symbol for input and filter
than two cascaded comb filters did not improve the tradeoff coefficients and has been found to offer better stop band
between signal-to-noise ratio of the coded output and the attenuation and dynamic range flexibility compared to the
OSR. binary format [8, 32]. While that work illustrates the poten-
In a second approach (Figure 6), input data was tial benefits of ternary encoded filters, the final decoder leaves
encoded into single-bit format through sigma-delta modu- the output in a multibit format that again requires complex
lator whereas the filter coefficients were kept in PCM format. hardware to process.
4 ISRN Electronics

Sigma-delta binary at the Nyquist rate and with a resolution mandated by

x(k) z −R z −R dynamic range and noise considerations.
modulator
Sigma-delta modulation (ΣΔM) encoding of the FIR
filter coefficients has been shown to be an efficient way to
h0 hN −1 reduce the complexity of the multiplier and improve its area-
performance tradeoffs [34]. The simple arithmetic of single-
bit DSP systems results in efficient hardware implementa-
Adder tions that map well to FPGA resources, which tend to com-
prise multiple flip-flops plus simple logic blocks and/or look-
up tables. The advantages of single-bit systems were first
identified by the authors of [22] and further developed in
Decoder [23, 24] and [26]. Recently, general purpose short word
length (SWL) DSP applications including classical LMS
algorithms have been described in [10, 35]. In this section we
y(k) introduce and describe the techniques that have been used
to filter whilst maintaining a single-bit output. This section
Figure 6: Block diagram of the FIR filter with ΣΔM modulated is further divided into two sections, that is, simulation based
input signal. single-bit techniques and their VLSI analysis.

3.1. Single-Bit FIR Filter Design Techniques. As the name

A slightly different fast and efficient FIR filter design suggests the single-bit filters produce a single-bit output. In
using sigma-delta encoding is presented in [27] in which a the last decade various general purpose DSP applications are
Look-Ahead Decision Feedback (LADF) approach is used reported using single-bit sigma-delta modulation encoding
to encode the filter coefficients into a single-bit format. In including classical FIR filter in [10, 35–38]. This single-bit
that work, the proposed technique is compared with two approach was first reported for IIR and FIR filtering in [2, 3].
other ΣΔM architectures: the multistage (MASH) and double In [3], a single-bit FIR filtering technique is proposed
loop (DSM2). It was found that the proposed architec- with bit-stream input and fixed or floating point coefficients
ture outperforms in comparison to double loop but has poor similar to the one reported in [8, 24]. However, the major
performance against the MASH architecture. Given the lower contribution is the replacement of the decoder in [8] by a
complexity implementation of the proposed architecture, the ΣΔM that has a low pass signal transfer function. The single-
author argues that the method is appropriate for filter encod- bit FIR filter as proposed in [3] is shown in Figure 7.
ing. However, the quantizer stage with LADF architecture is Similarly, in the second approach presented in [24], the
more complex than the single-bit quantizer and its associated input is assumed to be in a single-bit format, while full
ΣΔM architecture. precision filter coefficients are generated at the Nyquist rate.
The last group of fast and efficient filters designs uses a This newly generated impulse response was interpolated by R
canonical signed digit (CSD) quantizer with signed powers times, where R is the oversampling ratio of the input signal,
of two ΣΔM output [26]. It is argued that the CSD quantizer via zero-interleaving. The R aliases that were introduced
provides many more quantization levels than a single-bit due to zero-interleaving in [24] were removed by a decoder
quantizer, which suits the linear modelling of the system comprised of cascaded comb filters and a baseband filter.
design and can improve the system stability. Thus an out- However, in [3] a ΣΔM was used instead of a decoder. This
put in CSD format obtained from the ΣΔM can be used as ΣΔM was used to remove the aliasing created by the zero-
the FIR filter coefficients and the multiplication operation interleaving process and served to remodulate the multibit
becomes simple shifts. Another promising scheme presented output signal from the FIR filter back into the single-bit
in [33] uses a slightly more complex architecture but is domain.
essentially the same technique.
The VLSI analysis of the proposed design was carried out
and the single-bit design was found to be more efficient in
3. FIR Filter Encoding Using terms of silicon resources than a PCM digital filter up to 80
Sigma-Delta Modulation taps. The structure still has the complexity of a full precision
filter coefficients, which can also increase the word length of
Regardless of the many optimizations that have been pro- the FIR filter output.
posed, a large number of multiplication stages is still trans- The remodulator complexity is discussed by the same
lated into a large area, delay, and power consumption. One- authors in [39]. Digital ΣΔM low pass frequency responses
bit ΣΔ modulators are widely used in AD and DA conversion are typically not easy to find in the current literature. A
stages due to their inherent linearity and precision. However, fourth-order ΣΔM was used for this purpose with various
it is less common for the entire digital processing path to powers of two multiplications that created more complex
operate on single-bit data. The more usual approach has SDM structure than a standard one. Therefore, the low pass
been to decimate the signal data stream after conversion and modulator structure presented in [39] is very complex for
for the remaining processing to be performed in a standard single-bit filters.
ISRN Electronics 5

z −R + u(k) r(k)
x(k) z−R z −R x(k) Sigma-delta
β + +
modulator
−

Z −1

h0 h0 hN −1
α

Multibit format
Single-bit format
Adder
Figure 8: Block diagram of the first-order single-bit IIR filter.

x(k) Ternary + u(k) r(k)

β + + Sigma-delta
FIR filter
Low pass y(k) −
modulator
sigma-
delta Z −1
modulator

Multibit format
y(k)
Single-bit format
Multibit format
Single-bit format Figure 9: General bock diagram of the single-bit ternary FIR-like
filter.
Figure 7: Block diagram of the single-bit FIR filter.

these SWL techniques, the so-called single-bit ternary FIR

The core idea of the IIR single-bit ΣΔM presented in filter was first proposed in [10]. This design comprises two
[2, 40] is to multiply a one-bit oversampled input signal with parts: the ternary filter and the IIR remodulator, as shown
a multibit fixed coefficient. The resulting multibit output in Figure 9. A new method to generate the single-bit ternary
must be applied to a sigma-delta modulator to get back filter was also proposed that starts with the selection of the
the single-bit output. Initially the model was tested without target impulse response. This target impulse response must
the feed-forward integrator which resulted in a large noise undergo an interpolation stage before the ternary sigma-
gain due to its higher oversampling ratio transfer function. delta modulated form of the filter can be generated. The
A modified version with an integrator inside the loop that generated ternary format of coefficients must have flat pass
resulted in noise reduction and kept the STF and NTF the band frequency response in the frequency band of interest
same is shown in Figure 8. In this model, the ΣΔM is assumed (i.e., 0 → f0 ). The transfer function of the overall design was
to be a single delay element; hence, the system is a basic first- derived and the filter was simulated at a number of OSR val-
order recursive filter [2, 40]. ues. It was found that the resulting single-bit filter produced
The stability of the system in Figure 8 was assumed an equivalent output to the target impulse response. Hence,
to be determined by a rule of thumb with an assumption it appears that single-bit ternary filters can take over from the
that second-order sigma-delta modulators will remain stable. bulky multibit systems that include complex multiplication.
But due to an extra integrator inside the loop, the overall Using the same approach, a narrowband band pass ΣΔM
NTF becomes equivalent to a third-order ΣΔM, making it was proposed in [11] (Figure 10). Again it comprises two
more difficult to analyse the stability of the overall system parts: the ternary filter followed by the remodulation of the
[2]. Therefore, this system was not further studied by those multibit into single-bit format. Unlike the low pass single-
authors. bit filter, these authors have proposed a remodulation by a
However, a quasi-orthonormal state space IIR architec- simple band pass ΣΔM that has efficient architecture and
ture was shown to have good filtering abilities with good stop less stability sensitivity compared to the IIR remodulator.
band attenuation by the same authors in [41]. The downside Coefficients were encoded into a ternary format by passing
of this structure is that it requires N ΣΔM blocks for an Nth- the band-pass target impulse response through an 8th order
order IIR filter and the structure becomes very complex as ΣΔM with optimum coefficients. Through MATLAB simu-
the order number increases. The proliferation of ΣΔM blocks lation it was found that the overall frequency response of
only adds to the quantization noise in the band of interest the proposed method was very similar to the original target
and makes any stability analysis very difficult [2]. impulse response.
Recently, new DSP design techniques called short word The performance of the proposed method is also dis-
length (SWL) have been reported in [10, 11, 38, 42]. Of cussed in [43]. It was found that FFT and spline interpolation
6 ISRN Electronics

Bandpass hardware implementation of the arithmetic modules is done

Ternary in Xilinx Virtex-5 using two’s complement representation.
x(k) c sigma-delta y(k)
FIR filter
modulator The synthesis results demonstrated that there is a significant
improvement in the signal-to-noise ratio and performance
Figure 10: Single-bit narrowband bandpass FIR filter. with ternary format than binary at the cost of a more
complex structure [32]. Bit-stream (i.e., single-bit) ternary
and multibit approaches have been compared in FPGAs
techniques offer superior stop band attenuation performance by synthesizing a type I digital phase locked loop (DPLL)
to other techniques. Following the same approach, single- application using a direct digital synthesis approach [49].
bit resonators and BFSK demodulator designs have been The bit-stream ternary approach was found to be more
reported in [37, 44]. However, this short word length resource efficient than its corresponding multibit system
approach was not verified through hardware synthesis nor [32].
was its area-performance-power compared with contempo- In [47, 48], an efficient implementation of bit-stream
rary multibit techniques. Furthermore, that work does not adders and multipliers modules has been reported in FPGAs.
extend to a rigorous stability analysis of the SWL filtering In [47], a (4, 2) adder structure (i.e., 6-input (4 + 2)) was
techniques. exploited that better suited the Altera and Xilinx 6-input LUT
Further to this work, an LMS-like single-bit adaptive architectures than a conventional (2, 1) architecture. The
filtering structure for noise cancelling has been presented in proposed adder structure resulted in a 50% reduction in LUT
[35, 42, 45], in which all input, output, and filter coefficients count and a 20% higher clock frequency [47]. In [48], the
are in a single-bit format. Overall, three short word length trilevel bit-stream was extended to quad level and compared
adaptive structures were proposed: namely, ternary, single- to the sorter based approach [50]. The quad-level bit-stream
bit, and 2 bit. The overall weight vector equation was derived adder and multiplier presented in [48] were encoded using
by using block LMS algorithm which has advantage of 2 bit and the truncated third bit was fed back to the adder
accommodating more data samples and better performance to suppress the truncation error. Through Xilinx FPGA
than a sample-by-sample LMS algorithm. Through MATLAB synthesis, the proposed adder and multiplier have shown a
simulation it was found that short word length (SWL) significant improvement in area-performance compared to
adaptive filter (i.e., 2-bit format of coefficients) has a superior the sorter approach [50]. This quad-level adder approach
performance than the others, that is, single-bit and ternary, resulted in about a 76% LUT reduction and a 93% higher
at the cost of prospect more chip area. clock rate, while the proposed bit-stream multiplier showed
However, much work is still needed to explore the design a 82% LUT reduction and 122% higher clock frequency [48].
using random inputs within a higher noise environment. Regardless of the work reported on simple arithmetic
In addition, it is still unclear what might be the optimum modules, the drawback to all of these reported works is the
coefficient update rate or range of the convergence parameter limited range of their adder and multiplier modules (i.e.,
(mu) or shape of the learning curves. L = 4). Further, there has been no detailed comparison
provided to its corresponding multibit system except for one
4. VLSI Analysis of ΣΔM Based example reported in [32]. From the general behaviour of
Bit-Stream Circuits multibit versus single-bit systems, it can be predicted that
there may be a cross-over point between the two approaches,
Although much work has been reported on the design and where one could be preferred over the other. This idea will be
analysis of single-bit systems, it appears that there has been addressed later in the work.
little reported on rigorous hardware analysis of single-bit Unlike [32, 47, 48], in [30] an existing IIR low pass filter
signal processing techniques using FPGAs. However, a small ΣΔM is utilized to generate the input bit-stream and the
range of work has been reported on VLSI synthesis and design has been analysed to characterise the selection of the
analysis of bit-stream arithmetic modules and its variants ΣΔM design parameter (i.e., K, shown in Figure 11). The
that are further covered below. These arithmetic modules are design was extended to tri- and quad level and compared
building blocks of DSP algorithms but not a signal processing with the bilevel ΣΔM. The noise performance was simulated
application itself. Furthermore, these modules have been an for all three types of multipliers and it was found that trilevel
inherent part of the single-bit systems already proposed in design has a performance gain of 11.2 dB over the bilevel
[10, 35]. design, while the quad-level design has about a further 8.8 dB
In [6, 46] efficient bit-stream (i.e., single-bit) arith- gain over the trilevel design [30].
metic modules are presented for mobile communication in Hardware implementation of all three designs was
which general purpose modules including adder, multiplier, performed using the Xilinx Virtex-5 FPGA and the area-
divider, and square root have been designed. A typical QPSK performance characteristics of the multiplier were noted.
communication model has been demonstrated by using the The synthesis results show a direct tradeoff between all
proposed bit-stream arithmetic modules and a 40% reduc- the three designs and the two approaches for the IIR and
tion in logic gate count compared to conventional design has FIR filter modules. These results indicate that the bilevel
been reported. design is more resource efficient than either of the tri- and
Bit-stream arithmetic modules with bi-, tri-, and quad quad level and provides a higher performance at the cost
levels are described in [30, 32, 47, 48]. In these cases, of lower noise suppression and vice versa. However, this
ISRN Electronics 7

Table 1: Area-performance comparison of single-bit FIR versus multibit filter: nonpipelined mode.

Single-bit Multibit
Device
Number of tern. coeff LUTs FMAX N W LUTs FMAX
512 4089 (3%) 71.4 8 8860 (7%) 46.2
2048 15603 (13%) 52.6 12 17045 (14%) 35.3
Cyclone-III 64
4096 30894 (26%) 45.3 16 26838 (22%) 29.1
8192 62747 (53%) 40.3 18 32547 (27%) 26.5
512 3925 (1%) 129.8 8 5219 (2%) 86.5
2048 14368 (5%) 97.3 12 10942 (5%) 69.1
Stratix-III 64
4096 28499 (11%) 82.8 16 17731 (7%) 57.5
8192 55927 (21%) 69.6 18 21568 (8%) 51.2

Table 2: Area-performance comparison of single-bit FIR versus multibit Filter: pipelined mode.

Single-bit Multibit
Device
Number of tern. coeff LUTs FMAX N W LUTs FMAX
512 3963 (3%) 125.6 8 9020 (8%) 94.5
2048 15399 (13%) 122 12 17079 (14%) 67.1
Cyclone-III 64
4096 30607 (26%) 120 16 26890 (23%) 53.3
8192 61029 (51%) 118 18 32586 (27%) 47.4
512 3719 (1%) 240 8 4923 (1%) 258.3
2048 14453 (5%) 237 12 10353 (4%) 199.0
Stratix-III 64
4096 28745 (11%) 237 16 16916 (7%) 158.8
8192 57362 (21%) 231 18 20662 (8%) 139.7

x(k) r(k) their relative area, power, and throughput. The second is
+ + Z −1 that it remains to be determined how chip area-performance
− varies with varying OSR and bit width of the hardware SWL
system.
In [51, 52], a single-bit ternary FIR-like filter (SBTFF) has
been designed and synthesized in Quartus-II and ModelSim
K
using VHDL (see Figure 9). The design and implementation
of the overall SBTFF have been explored in small commercial
Figure 11: First order digital sigma-delta modulator [30]. FPGAs in order to compare its power-area-performance
characteristics with approximately equivalent multibit FIR
filters. Both filter types were designed and simulated in
pipelined and nonpipelined modes. In this set of simulations,
assumes that the system was stable by considering the same varying OSR (32–256) was used to identify the area-
approach described in [2]. This rule of thumb may lead to an performance-power analysis of two techniques.
inappropriate solution in real systems [2].
Simulation results obtained through the set of experi-
ments are given in Tables 1 and 2. These results are repro-
5. A Case Study: FPGA Analysis of duced here that were reported in [52]. In this work, it is
Single-Bit Ternary FIR-Like Filter shown conclusively that single-bit ternary FIR-like filters
are able to consistently outperform their equivalent multibit
As discussed earlier much work has been reported on the counterparts in terms of area, power, and performance (i.e.,
design and analysis of single-bit ternary FIR-like filters maximum cut-off frequency in a given technology) except
including classical LMS-like filters that are classified in at the most extreme filter orders analysed in the work.
general short word length (SWL) DSP systems. These have Typically single-bit ternary FIR-like filter offered reasonable
tended to be performed using high-level tools such as area savings at lower orders and higher performance in
MATLAB, with little work reported relating to their hardware all cases in the range of 30%–40% in pipelined and non-
implementation, particularly in Field Programmable Gate pipelined modes.
Arrays (FPGAs). Two primary areas of interest exist here. The power analysis of two filters was performed in two
The first is the comparative behaviour of SWL and multibit steps using clock obtained from the area-performance results
systems exhibiting equal spectral performance in terms of (shown in Tables 1 and 2) and at multibit oversampling clock
8 ISRN Electronics

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