AXI Protocol Checker

v1.1

LogiCORE IP Product Guide

Vivado Design Suite

PG101 October 5, 2016
Table of Contents
IP Facts

Chapter 1: Overview
Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
Licensing and Ordering Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6

Chapter 2: Product Specification

Standards . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Performance. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Resource Utilization. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Port Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Checks and Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16

Chapter 3: Designing with the Core

General Design Guidelines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
Clocking. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
Resets . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25

Chapter 4: Design Flow Steps

Customizing and Generating the Core . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
Constraining the Core . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
Simulation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
Synthesis and Implementation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33

Appendix A: Debugging
Finding Help on Xilinx.com . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
General Checks. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
Debug Tools . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
Clocks and Resets. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
Core Size and Optimization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
Flags . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36

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 Appendix B: Migrating and Upgrading
Migrating to the Vivado Design Suite. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
Upgrading in the Vivado Design Suite . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38

Appendix C: Additional Resources and Legal Notices

Xilinx Resources . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
References . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
Please Read: Important Legal Notices . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40

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 IP Facts

Introduction LogiCORE IP Facts Table

Core Specifics
The AXI Protocol Checker core monitors AXI Supported
UltraScale+™, UltraScale™, 7 Series
interfaces. When attached to an interface, it Device Family(1)
actively checks for protocol violations and Supported User AXI4, AXI4-Lite, AXI3
provides an indication of which violation Interfaces

occurred. Resources See Table 2-1.

Provided with Core

The checks are synthesizable versions of the
Design Files RTL
System Verilog protocol assertions provided by
Example Design Not Provided
ARM in the “AMBA 4 AXI4, AXI4-Lite, and
Test Bench Not Provided
AXI4-Stream Protocol Assertion” library [Ref 2].
Constraints File Not Provided
Simulation
Not Provided
Model
Features Supported
N/A
S/W Driver

• Supports checking for AXI3, AXI4 and Tested Design Flows(2)

AXI4-Lite protocols Design Entry Vivado Design Suite

• Interface data widths: For support simulators, see the

Simulation
Xilinx Design Tools: Release Notes Guide.

° AXI4 and AXI3: 32, 64, 128, 256, 512 or Synthesis Vivado Synthesis.
1024 bits Support
° AXI4-Lite: 32 or 64 bits Provided by Xilinx at the Xilinx Support web page

• Address width: Up to 64 bits Notes:

1. For a complete list of supported derivative devices, see
• USER width (per channel): Up to 1024 bits Embedded Edition Derivative Device Support.
2. For the supported versions of the tools, see the
• ID width: Up to 32 bits Xilinx Design Tools: Release Notes Guide.

• Programmable messaging levels for

simulation operation.
• Supports monitoring of multiple
outstanding READ and WRITE transactions
• Instrumented to support Vivado® Design
Suite Debug Nets and connections to
Vivado Logic Analyzer monitoring

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PG101 October 5, 2016 Product Specification
 Chapter 1

Overview
The AXI Protocol Checker is used to debug interface signals in systems using the AXI4, AXI3
or AXI4-Lite protocol. When placed in an AXI system, the connection of the AXI Protocol
Checker monitors the traffic between the AXI Master and AXI Slave Core.

The interface is checked against the rules outlined in the AXI Specification to determine if
a violation has occurred [Ref 2]. These violations are reported in a simulation log file
message and as a debug net in the Vivado Logic Analyzer. In addition, the violations appear
on the status vector output port from the core.
X-Ref Target - Figure 1-1

axi_protocol_checker

core
AW
AXI4/AXI3
Checker
W

B AXI4-Lite
Checker

AR

Simulation
R
Reporter Error Vector

X13125

Figure 1‐1: AXI Protocol Checker Block Diagram

Applications
The AXI Protocol Checker is typically used by system designers to ensure that traffic on a
given AXI connection complies with the AXI protocol.

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 Chapter 1: Overview

Licensing and Ordering Information

This Xilinx LogiCORE IP module is provided at no additional cost with the Xilinx Vivado
Design Suite under the terms of the Xilinx End User License.

Information about this and other Xilinx LogiCORE IP modules is available at the Xilinx
Intellectual Property page. For information on pricing and availability of other Xilinx
LogiCORE IP modules and tools, contact your local Xilinx sales representative.

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 Chapter 2

Product Specification
The AXI Protocol Checker monitors the connection for AXI4, AXI3, and AXI4-Lite protocol
violations. The AXI Protocol Checker is designed around the ARM System Verilog assertions
that have been converted into synthesizable HDL. When a protocol violation occurs, the AXI
Protocol Checker asserts the corresponding bit on the pc_status output vector. The
output vector bit mapping can be found in Table 2-6 and Table 2-7.

Bits of the pc_status vector are synchronously set when a protocol violation occurs.
Multiple bits can be triggered on the same or different cycles. When the bit within the
pc_status vector has been set, it remains asserted until either the connection has been
reset with aresetn or the core has been reset with system_resetn. The pc_asserted
output signal is also asserted while any bit of the pc_status vector is asserted.

Standards
The AXI interfaces conform to the Advanced Microcontroller Bus Architecture (AMBA®) AXI
version 4 specification from Advanced RISC Machine (ARM®), including the AXI4-Lite
control register interface subset. See ARM AMBA® AXI Protocol v2.0 [Ref 2].

Performance
This section includes information about the core performance.

Maximum Frequencies
The maximum frequency with a 64-bit AXI data width is 200 MHz.

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 Chapter 2: Product Specification

Resource Utilization
Resources required for the AXI Protocol Checker have been estimated for the Kintex®-7
XC7K325T FPGA (Table 2-1). These values were generated using Vivado™ IP Catalog
v2012.4. They are derived from post-synthesis reports, and might change during MAP and
PAR.

Note: Resource utilization for UltraScale architecture devices is expected to be similar to 7 series
results.

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 Chapter 2: Product Specification

Table 2‐1: Kintex-7 FPGA Resource Estimates

Maximum Read/ Maximum READY

Protocol Data Width ID Width Write Transactions Wait Cycles LUTs FFs

1024 3 32 16 4132 5072

1024 3 32 0 4044 4982
1024 3 2 16 3565 4780
1024 3 2 0 3474 4686
1024 0 32 16 3620 4806
1024 0 32 0 3524 4716
1024 0 2 16 3516 4738
1024 0 2 0 3424 4652
128 3 32 16 1467 1264
128 3 32 0 1375 1174
128 3 2 16 886 972
128 3 2 0 798 882
128 0 32 16 930 994
128 0 32 0 844 908
128 0 2 16 837 934
128 0 2 0 745 844
AXI4
64 3 32 16 1279 992
64 3 32 0 1197 902
64 3 2 16 691 696
64 3 2 0 603 610
64 0 32 16 746 722
64 0 32 0 654 632
64 0 2 16 642 662
64 0 2 0 553 572
32 3 32 16 1210 856
32 3 32 0 1119 766
32 3 2 16 623 564
32 3 2 0 532 474
32 0 32 16 672 590
32 0 32 0 583 500
32 0 2 16 574 526
32 0 2 0 486 436

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 Chapter 2: Product Specification

Table 2‐1: Kintex-7 FPGA Resource Estimates (Cont’d)

Protocol Data Width ID Width Maximum Read/ Maximum READY LUTs FFs
Write Transactions Wait Cycles

64 0 32 16 528 591
64 0 32 0 437 501
64 0 2 16 429 527
64 0 2 0 340 437
AXI4-Lite
32 0 32 16 449 455
32 0 32 0 357 365
32 0 2 16 348 391
32 0 2 0 258 301

Port Descriptions
This section contains details about the AXI Protocol Checker ports.

Protocol Independent Port Descriptions

Table 2-2 lists the ports that apply to all protocols.

Table 2‐2: Protocol independent port descriptions

Signal Name Direction Default Width Description
aclk Input Required 1 Interface clock input.
aresetn Input Required 1 Interface reset input (active-Low).
system_resetn Input Optional 1 System reset (active-Low).
Active-High vector of protocol violations
pc_status Output 90
or warnings.
Active-High signal is asserted when any
pc_asserted Output 1
bit of the pc_status vector is asserted.

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 Chapter 2: Product Specification

AXI4 Port Descriptions

Table 2-3 lists the interface signals for the AXI Protocol Checker core when it is configured
to check an AXI4 Interface.

Table 2‐3: AXI4 Protocol Port Descriptions

Signal Name Direction Default Width Description
pc_axi_awid Input 0 ID_WIDTH Write Address Channel Transaction ID
Write Address Channel Transaction
pc_axi_awaddr Input Required ADDR_WIDTH
Address (12-64)
Write Address Channel Transaction Burst
pc_axi_awlen Input 0 8
Length (0-255)
Write Address Channel Transfer Size Code
pc_axi_awsize Input Required 3
(0-7)
Write Address Channel Burst Type Code
pc_axi_awburst Input Required 2
(0-2)
Write Address Channel Atomic Access
pc_axi_awlock Input 0b0 1
Type (0-1)
Write Address Channel Cache
pc_axi_awcache Input 0b0000 4
Characteristics
Write Address Channel Protection
pc_axi_awprot Input 0b000 3
Characteristics
pc_axi_awqos Input 0b0000 4 Write Address Channel Quality of Service
pc_axi_awregion Input 0b0000 4 Write Address Channel Region Index
Write Address Channel User-Defined
pc_axi_awuser Input AWUSER_WIDTH
Signals
pc_axi_awvalid Input Required 1 Write Address Channel Valid
pc_axi_awready Input Required 1 Write Address Channel Ready
pc_axi_arid Input 0 ID_WIDTH Read Address Channel Transaction ID
Read Address Channel Transaction
pc_axi_araddr Input Required ADDR_WIDTH
Address (12-64)
Read Address Channel Transaction Burst
pc_axi_arlen Input 0 8
Length (0-255)
Read Address Channel Transfer Size Code
pc_axi_arsize Input Required 3
(0-7)
Read Address Channel Burst Type Code
pc_axi_arburst Input Required 2
(0-2)
Read Address Channel Atomic Access
pc_axi_arlock Input 0b0 1
Type (0-1)
Read Address Channel Cache
pc_axi_arcache Input 0b0000 4
Characteristics
Read Address Channel Protection
pc_axi_arprot Input 0b000 3
Characteristics

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 Chapter 2: Product Specification

Table 2‐3: AXI4 Protocol Port Descriptions (Cont’d)

Signal Name Direction Default Width Description
pc_axi_arqos Input 0b0000 4 Read Address Channel Quality of Service
pc_axi_arregion Input 0b0000 4 Read Address Channel Region Index
Read Address Channel User-Defined
pc_axi_aruser Input ARUSER_WIDTH
Signals
pc_axi_arvalid Input Required 1 Read Address Channel Valid
pc_axi_arready Input Required 1 Read Address Channel Ready
pc_axi_wlast Input 0b1 1 Write Data Channel Last Data Beat
pc_axi_wdata Input DATA_WIDTH Write Data Channel Data
pc_axi_wstrb Input All Ones DATA_WIDTH/8 Write Data Channel Byte Strobes
pc_axi_wuser Input WUSER_WIDTH Write Data Channel User-Defined Signal
pc_axi_wvalid Input Required 1 Write Data Channel Valid
pc_axi_wready Input Required 1 Write Data Channel Ready
pc_axi_rid Input ID_WIDTH Read Data Channel Transaction ID
pc_axi_rlast Input 1 1 Read Data Channel Last Data Beat
pc_axi_rdata Input DATA_WIDTH Read Data Channel Data
pc_axi_rresp Input 0b00 2 Read Data Channel Response code (0-3)
pc_axi_ruser Input RUSER_WIDTH Read Data Channel User-Defined Signal
pc_axi_rvalid Input Required 1 Read Data Channel Valid
pc_axi_rready Input Required 1 Read Data Channel Ready
pc_axi_bid Input ID_WIDTH Write Response Channel Transaction ID
Write Response Channel Response Code
pc_axi_bresp Input 0b00 2
(0-3)
Write Response Channel User-Defined
pc_axi_buser Input BUSER_WIDTH
Signal
pc_axi_bvalid Input Required 1 Write Response Channel Valid
pc_axi_bready Input Required 1 Write Response Channel Ready

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 Chapter 2: Product Specification

AXI3 Port Descriptions

Table 2-4 lists the interface signals for the AXI Protocol Checker core when it is configured
to check an AXI3 Interface.

Table 2‐4: AXI3 Protocol Port Descriptions

Signal Name Direction Default Width Description
pc_axi_awid Input 0 ID_WIDTH Write Address Channel Transaction ID
Write Address Channel Transaction
pc_axi_awaddr Input Required ADDR_WIDTH
Address (12-64)
Write Address Channel Transaction Burst
pc_axi_awlen Input 0 4
Length (0-16)
Write Address Channel Transfer Size code
pc_axi_awsize Input Required 3
(0-7)
Write Address Channel Burst Type code
pc_axi_awburst Input Required 2
(0-2)
Write Address Channel Atomic Access Type
pc_axi_awlock Input 0b00 2
(0-3)
Write Address Channel Cache
pc_axi_awcache Input 0b0000 4
Characteristics
Write Address Channel Protection
pc_axi_awprot Input 0b000 3
Characteristics
pc_axi_awqos Input 0b0000 4 Write Address Channel Quality of Service
Write Address Channel User-Defined
pc_axi_awuser Input AWUSER_WIDTH
Signals
pc_axi_awvalid Input Required 1 Write Address Channel Valid
pc_axi_awready Input Required 1 Write Address Channel Ready
pc_axi_arid Input 0 ID_WIDTH Read Address Channel Transaction ID
Read Address Channel Transaction Address
pc_axi_araddr Input Required ADDR_WIDTH
(12-64)
Read Address Channel Transaction Burst
pc_axi_arlen Input 0 4
Length (0-16)
Read Address Channel Transfer Size Code
pc_axi_arsize Input Required 3
(0-7)
Read Address Channel Burst Type Code
pc_axi_arburst Input Required 2
(0-2)
Read Address Channel Atomic Access Type
pc_axi_arlock Input 0b00 2
(0-3)
Read Address Channel Cache
pc_axi_arcache Input 0b0000 4
Characteristics
Read Address Channel Protection
pc_axi_arprot Input 0b000 3
Characteristics
pc_axi_arqos Input 0b0000 4 Read Address Channel Quality of Service

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 Chapter 2: Product Specification

Table 2‐4: AXI3 Protocol Port Descriptions (Cont’d)

Signal Name Direction Default Width Description
Read Address Channel User-Defined
pc_axi_aruser Input ARUSER_WIDTH
Signals
pc_axi_arvalid Input Required 1 Read Address Channel Valid
pc_axi_arready Input Required 1 Read Address Channel Ready
pc_axi_wid Input ID_WIDTH Write Data Channel Transaction ID
pc_axi_wlast Input 0b1 1 Write Data Channel Last Data Beat
pc_axi_wdata Input DATA_WIDTH Write Data Channel Data
pc_axi_wstrb Input All Ones DATA_WIDTH/8 Write Data Channel Byte Strobes
pc_axi_wuser Input WUSER_WIDTH Write Data Channel User-Defined Signal
pc_axi_wvalid Input Required 1 Write Data Channel Valid
pc_axi_wready Input Required 1 Write Data Channel Ready
pc_axi_rid Input ID_WIDTH Read Data Channel Transaction ID
pc_axi_rlast Input 1 1 Read Data Channel Last Data Beat
pc_axi_rdata Input DATA_WIDTH Read Data Channel Data
pc_axi_rresp Input 0b00 2 Read Data Channel Response code (0-3)
pc_axi_ruser Input RUSER_WIDTH Read Data Channel User-Defined Signal
pc_axi_rvalid Input Required 1 Read Data Channel Valid
pc_axi_rready Input Required 1 Read Data Channel Ready
pc_axi_bid Input ID_WIDTH Write Response Channel Transaction ID
Write Response Channel Response Code
pc_axi_bresp Input 0b00 2
(0-3)
Write Response Channel User-Defined
pc_axi_buser Input BUSER_WIDTH
Signal
pc_axi_bvalid Input Required 1 Write Response Channel Valid
pc_axi_bready Input Required 1 Write Response Channel Ready

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 Chapter 2: Product Specification

AXI4-Lite Port Descriptions

Table 2-5 lists the interface signals for the AXI Protocol Checker core when it is configured
to check an AXI4-Lite Interface.

Table 2‐5: AXI4-Lite Protocol Port Descriptions

Signal Name Direction Default Width Description
Write Address Channel Transaction
pc_axi_awaddr Input Required ADDR_WIDTH
Address (12-64)
Write Address Channel Protection
pc_axi_awprot Input 0b000 3
Characteristics
pc_axi_awvalid Input Required 1 Write Address Channel Valid
pc_axi_awready Input Required 1 Write Address Channel Ready
Read Address Channel Transaction
pc_axi_araddr Input Required ADDR_WIDTH
Address (12-64)
Read Address Channel Protection
pc_axi_arprot Input 0b000 3
Characteristics
pc_axi_arvalid Input Required 1 Read Address Channel Valid
pc_axi_arready Input Required 1 Read Address Channel Ready
pc_axi_wdata Input DATA_WIDTH Write Data Channel Data
pc_axi_wstrb Input All Ones DATA_WIDTH/8 Write Data Channel Byte Strobes
pc_axi_wvalid Input Required 1 Write Data Channel Valid
pc_axi_wready Input Required 1 Write Data Channel Ready
pc_axi_rdata Input DATA_WIDTH Read Data Channel Data
pc_axi_rresp Input 0b00 2 Read Data Channel Response code (0-3)
pc_axi_rvalid Input Required 1 Read Data Channel Valid
pc_axi_rready Input Required 1 Read Data Channel Ready
Write Response Channel Response Code
pc_axi_bresp Input 0b00 2
(0-3)
pc_axi_bvalid Input Required 1 Write Response Channel Valid
pc_axi_bready Input Required 1 Write Response Channel Ready

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 Chapter 2: Product Specification

Checks and Descriptions

AXI Protocol Checks and Descriptions
The AXI Protocol Checks and descriptions, listed in Table 2-6, correspond to the assertions
that are found in the ARM AXI assertions.

Table 2‐6: AXI4/AXI3 and AXI4-Lite Protocol Checks and Descriptions

Protocol
Name of Protocol Check Bit Support Description

AXI_ERRM_AWADDR_BOUNDARY 0 AXI4/AXI3 A write burst cannot cross a 4KB boundary.

A write transaction with burst type WRAP
AXI_ERRM_AWADDR_WRAP_ALIGN 1 AXI4/AXI3
has an aligned address.
A value of 2’b11 on AWBURST is not
AXI_ERRM_AWBURST 2 AXI4/AXI3
permitted when AWVALID is High.
Exclusive access transactions cannot have a
AXI_ERRM_AWLEN_LOCK 3 AXI4/AXI3 length greater than 16 beats. This check is
not implemented.
If not cacheable (AWCACHE[1] == 1'b0),
AXI_ERRM_AWCACHE 4 AXI4/AXI3
AWCACHE = 2'b00.
Transactions of burst type FIXED cannot
AXI_ERRM_AWLEN_FIXED 5 AXI4/AXI3
have a length greater than 16 beats.
A write transaction with burst type WRAP
AXI_ERRM_AWLEN_WRAP 6 AXI4/AXI3
has a length of 2, 4, 8, or 16.
The size of a write transfer does not exceed
AXI_ERRM_AWSIZE 7 AXI4/AXI3
the width of the data interface.
AWVALID is Low for the first cycle after
AXI_ERRM_AWVALID_RESET 8 AXI4/AXI3/Lite
ARESETn goes High.
Handshake Checks: AWADDR must remain
AXI_ERRM_AWADDR_STABLE 9 AXI4/AXI3/Lite stable when AWVALID is asserted and
AWREADY Low.
Handshake Checks: AWBURST must remain
AXI_ERRM_AWBURST_STABLE 10 AXI4/AXI3 stable when AWVALID is asserted and
AWREADY Low.
Handshake Checks: AWCACHE must remain
AXI_ERRM_AWCACHE_STABLE 11 AXI4/AXI3 stable when AWVALID is asserted and
AWREADY Low.
Handshake Checks: AWID must remain
AXI_ERRM_AWID_STABLE 12 AXI4/AXI3 stable when AWVALID is asserted and
AWREADY Low.
Handshake Checks: AWLEN must remain
AXI_ERRM_AWLEN_STABLE 13 AXI4/AXI3 stable when AWVALID is asserted and
AWREADY Low.

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 Chapter 2: Product Specification

Table 2‐6: AXI4/AXI3 and AXI4-Lite Protocol Checks and Descriptions (Cont’d)

Name of Protocol Check Bit Protocol Description

Support
Handshake Checks: AWLOCK must remain
stable when AWVALID is asserted and
AXI_ERRM_AWLOCK_STABLE 14 AXI4/AXI3
AWREADY Low. This check is not
implemented.
Handshake Checks: AWPROT must remain
AXI_ERRM_AWPROT_STABLE 15 AXI4/AXI3/Lite stable when AWVALID is asserted and
AWREADY Low.
Handshake Checks: AWSIZE must remain
AXI_ERRM_AWSIZE_STABLE 16 AXI4/AXI3 stable when AWVALID is asserted and
AWREADY Low.
Handshake Checks: AWQOS must remain
AXI_ERRM_AWQOS_STABLE 17 AXI4/AXI3 stable when AWVALID is asserted and
AWREADY Low.
Handshake Checks: AWREGION must remain
AXI_ERRM_AWREGION_STABLE 18 AXI4 stable when ARVALID is asserted and
AWREADY Low.
Handshake Checks: Once AWVALID is
AXI_ERRM_AWVALID_STABLE 19 AXI4/AXI3/Lite asserted, it must remain asserted until
AWREADY is High.
Recommended that AWREADY is asserted
AXI_RECS_AWREADY_MAX_WAIT 20 AXI4/AXI3/Lite within MAXWAITS cycles of AWVALID being
asserted.
The number of write data items matches
AWLEN for the corresponding address. This
is triggered when any of the following
occurs:
• Write data arrives, WLAST is set, and the
AXI_ERRM_WDATA_NUM 21 AXI4/AXI3 WDATA count is not equal to AWLEN
• Write data arrives, WLAST is not set, and
the WDATA count is equal to AWLEN
• ADDR arrives, WLAST is already received,
and the WDATA count is not equal to
AWLEN
AXI_ERRM_WSTRB 22 AXI4/AXI3/Lite Write strobes must only be asserted for the
correct byte lanes as determined from the:
Start Address, Transfer Size and Beat
Number.
WVALID is LOW for the first cycle after
AXI_ERRM_WVALID_RESET 23 AXI4/AXI3/Lite
ARESETn goes High.
Handshake Checks: WDATA must remain
AXI_ERRM_WDATA_STABLE 24 AXI4/AXI3/Lite stable when WVALID is asserted and
WREADY Low.
Handshake Checks: WLAST must remain
AXI_ERRM_WLAST_STABLE 25 AXI4/AXI3 stable when WVALID is asserted and
WREADY Low.

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Table 2‐6: AXI4/AXI3 and AXI4-Lite Protocol Checks and Descriptions (Cont’d)

Name of Protocol Check Bit Protocol Description

Support
Handshake Checks: WSTRB must remain
AXI_ERRM_WSTRB_STABLE 26 AXI4/AXI3/Lite stable when WVALID is asserted and
WREADY Low.
Handshake Checks: Once WVALID is
AXI_ERRM_WVALID_STABLE 27 AXI4/AXI3/Lite asserted, it must remain asserted until
WREADY is High.
Recommended that WREADY is asserted
AXI_RECS_WREADY_MAX_WAIT 28 AXI4/AXI3/Lite within MAXWAITS cycles of WVALID being
asserted.
A slave must not take BVALID HIGH until
AXI_ERRS_BRESP_WLAST 29 AXI4/AXI3 after the last write data handshake is
complete.
An EXOKAY write response can only be given
AXI_ERRS_BRESP_EXOKAY 30 AXI4/AXI3 to an exclusive write access. This check is not
implemented.
BVALID is Low for the first cycle after
AXI_ERRS_BVALID_RESET 31 AXI4/AXI3/Lite
ARESETn goes High.
A slave must not take BVALID HIGH until
AXI_ERRS_BRESP_AW 32 AXI4/AXI3/Lite after the write address is handshake is
complete.
Handshake Checks: BID must remain stable
AXI_ERRS_BID_STABLE 33 AXI4/AXI3
when BVALID is asserted and BREADY Low .
Checks BRESP must remain stable when
AXI_ERRS_BRESP_STABLE 34 AXI4/AXI3/Lite
BVALID is asserted and BREADY Low.
Once BVALID is asserted, it must remain
AXI_ERRS_BVALID_STABLE 35 AXI4/AXI3/Lite
asserted until BREADY is High.
Recommended that BREADY is asserted
AXI_RECM_BREADY_MAX_WAIT 36 AXI4/AXI3/Lite within MAXWAITS cycles of BVALID being
asserted.
AXI_ERRM_ARADDR_BOUNDARY 37 AXI4/AXI3 A read burst cannot cross a 4KB boundary.
A read transaction with a burst type of
AXI_ERRM_ARADDR_WRAP_ALIGN 38 AXI4/AXI3
WRAP must have an aligned address.
A value of 2'b11 on ARBURST is not
AXI_ERRM_ARBURST 39 AXI4/AXI3
permitted when ARVALID is High.
Exclusive access transactions cannot have a
AXI_ERRM_ARLEN_LOCK 40 AXI4/AXI3 length greater than 16 beats. This check is
not implemented.
When ARVALID is HIGH, if ARCACHE[1] is
AXI_ERRM_ARCACHE 41 AXI4/AXI3
LOW, then ARCACHE[3:2] must also be Low.
Transactions of burst type FIXED cannot
AXI_ERRM_ARLEN_FIXED 42 AXI4/AXI3
have a length greater than 16 beats.
A read transaction with burst type of WRAP
AXI_ERRM_ARLEN_WRAP 43 AXI4/AXI3
must have a length of 2, 4, 8, or 16.

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Table 2‐6: AXI4/AXI3 and AXI4-Lite Protocol Checks and Descriptions (Cont’d)

Name of Protocol Check Bit Protocol Description

Support
The size of a read transfer must not exceed
AXI_ERRM_ARSIZE 44 AXI4/AXI3
the width of the data interface.
ARVALID is Low for the first cycle after
AXI_ERRM_ARVALID_RESET 45 AXI4/AXI3/Lite
ARESETn goes High.
ARADDR must remain stable when ARVALID
AXI_ERRM_ARADDR_STABLE 46 AXI4/AXI3/Lite
is asserted and ARREADY Low.
ARBURST must remain stable when ARVALID
AXI_ERRM_ARBURST_STABLE 47 AXI4/AXI3
is asserted and ARREADY Low.
ARCACHE must remain stable when
AXI_ERRM_ARCACHE_STABLE 48 AXI4/AXI3
ARVALID is asserted and ARREADY Low.
ARID must remain stable when ARVALID is
AXI_ERRM_ARID_STABLE 49 AXI4/AXI3
asserted and ARREADY Low.
ARLEN must remain stable when ARVALID is
AXI_ERRM_ARLEN_STABLE 50 AXI4/AXI3
asserted and ARREADY Low.
ARLOCK must remain stable when ARVALID
AXI_ERRM_ARLOCK_STABLE 51 AXI4/AXI3 is asserted and ARREADY Low. This check is
not implemented.
ARPROT must remain stable when ARVALID
AXI_ERRM_ARPROT_STABLE 52 AXI4/AXI3/Lite
is asserted and ARREADY Low.
ARSIZE must remain stable when ARVALID is
AXI_ERRM_ARSIZE_STABLE 53 AXI4/AXI3
asserted and ARREADY Low.
ARQOS must remain stable when ARVALID is
AXI_ERRM_ARQOS_STABLE 54 AXI4/AXI3
asserted and ARREADY Low.
ARREGION must remain stable when
AXI_ERRM_ARREGION_STABLE 55 AXI4
ARVALID is asserted and ARREADY Low.
Once ARVALID is asserted, it must remain
AXI_ERRM_ARVALID_STABLE 56 AXI4/AXI3/Lite
asserted until ARREADY is High.
Recommended that ARREADY is asserted
AXI_RECS_ARREADY_MAX_WAIT 57 AXI4/AXI3/Lite within MAXWAITS cycles of ARVALID being
asserted.
The number of read data items must match
AXI_ERRS_RDATA_NUM 58 AXI4/AXI3
the corresponding ARLEN.
The read data must always follow the
address that it relates to. If IDs are used, RID
must also match ARID of an outstanding
AXI_ERRS_RID 59 AXI4/AXI3/Lite
address read transaction. This violation can
also occur when RVALID is asserted with no
preceding AR transfer.
An EXOKAY write response can only be given
AXI_ERRS_RRESP_EXOKAY 60 AXI4/AXI3 to an exclusive read access. This check is not
implemented.
RVALID is Low for the first cycle after
AXI_ERRS_RVALID_RESET 61 AXI4/AXI3/Lite
ARESETn goes High.

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Table 2‐6: AXI4/AXI3 and AXI4-Lite Protocol Checks and Descriptions (Cont’d)

Name of Protocol Check Bit Protocol Description

Support
RDATA must remain stable when RVALID is
AXI_ERRS_RDATA_STABLE 62 AXI4/AXI3/Lite
asserted and RREADY Low.
RID must remain stable when RVALID is
AXI_ERRS_RID_STABLE 63 AXI4/AXI3
asserted and RREADY Low.
RLAST must remain stable when RVALID is
AXI_ERRS_RLAST_STABLE 64 AXI4/AXI3
asserted and RREADY Low.
RRESP must remain stable when RVALID is
AXI_ERRS_RRESP_STABLE 65 AXI4/AXI3/Lite
asserted and RREADY Low.
Once RVALID is asserted, it must remain
AXI_ERRS_RVALID_STABLE 66 AXI4/AXI3/Lite
asserted until RREADY is High.
Recommended that RREADY is asserted
AXI_RECM_RREADY_MAX_WAIT 67 AXI4/AXI3/Lite within MAXWAITS cycles of RVALID being
asserted.
The address of an exclusive access is aligned
AXI_ERRM_EXCL_ALIGN 68 AXI4/AXI3 to the total number of bytes in the
transaction. This check is not implemented.
The number of bytes to be transferred in an
exclusive access burst is a power of 2, that is,
AXI_ERRM_EXCL_LEN 69 AXI4/AXI3
1, 2, 4, 8, 16, 32, 64, or 128 bytes. This check
is not implemented.
Recommended that the address, size, and
length of an exclusive write with a given ID
AXI_RECM_EXCL_MATCH 70 AXI4/AXI3 is the same as the address, size, and length
of the preceding exclusive read with the
same ID. This check is not implemented.
128 is the maximum number of bytes that
AXI_ERRM_EXCL_MAX 71 AXI4/AXI3 can be transferred in an exclusive burst. This
check is not implemented.
Recommended that every exclusive write
has an earlier outstanding exclusive read
AXI_RECM_EXCL_PAIR 72 AXI4/AXI3
with the same ID. This check is not
implemented.
AWUSER must remain stable when AWVALID
AXI_ERRM_AWUSER_STABLE 73 AXI4/AXI3
is asserted and AWREADY Low.
WUSER must remain stable when WVALID is
AXI_ERRM_WUSER_STABLE 74 AXI4/AXI3
asserted and WREADY Low.
BUSER must remain stable when BVALID is
AXI_ERRS_BUSER_STABLE 75 AXI4/AXI3
asserted and BREADY Low.
ARUSER must remain stable when ARVALID
AXI_ERRM_ARUSER_STABLE 76 AXI4/AXI3
is asserted and ARREADY Low.
RUSER must remain stable when RVALID is
AXI_ERRS_RUSER_STABLE 77 AXI4/AXI3
asserted and RREADY Low.

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Table 2‐6: AXI4/AXI3 and AXI4-Lite Protocol Checks and Descriptions (Cont’d)

Name of Protocol Check Bit Protocol Description

Support
Read CAM overflow, increase MAXRBURSTS
AXI_AUXM_RCAM_OVERFLOW 78 AXI4/AXI3/Lite
parameter.
AXI_AUXM_RCAM_UNDERFLOW 79 AXI4/AXI3/Lite Read CAM underflow.
Write CAM overflow, increase MAXWBURSTS
AXI_AUXM_WCAM_OVERFLOW 80 AXI4/AXI3/Lite
parameter.
AXI_AUXM_WCAM_UNDERFLOW 81 AXI4/AXI3/Lite Write CAM underflow.
AXI_AUXM_EXCL_OVERFLOW 82 AXI4/AXI3 Exclusive access monitor overflow.
A slave must not give an EXOKAY response
AXI4LITE_ERRS_BRESP_EXOKAY 83 Lite
on an AXI4-Lite interface.
A slave must not give an EXOKAY response
AXI4LITE_ERRS_RRESP_EXOKAY 84 Lite
on an AXI4-Lite interface.
AXI4LITE_AUXM_DATA_WIDTH 85 Lite DATA_WIDTH parameter is 32 or 64.

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 Chapter 2: Product Specification

Xilinx Configuration Checks and Descriptions

The Xilinx Configuration Checks are listed and described in Table 2-7.

Table 2‐7: Xilinx Configuration Checks and Descriptions

Protocol
Name of Protocol Check Bit Description
Support
When the connection does not
support narrow transfers, the AW
XILINX_AW_SUPPORTS_NARROW_BURST 86 AXI4/AXI3 Master cannot issue a transfer with
AWLEN > 0 and AWSIZE is less than
the defined interface DATA_WIDTH.
When the connection does not
support narrow transfers, the AR
XILINX_AR_SUPPORTS_NARROW_BURST 87 AXI4/AXI3 Master cannot issue a transfer with
ARLEN > 0 and ARSIZE is less than the
defined interface DATA_WIDTH.
When the connection does not
support narrow transfers, the AW
XILINX_AW_SUPPORTS_NARROW_CACHE 88 AXI4/AXI3 Master cannot issue a transfer with
AWLEN > 0 and AWCACHE modifiable
bit is not asserted.
When the connection does not
support narrow transfers, the AR
XILINX_AR_SUPPORTS_NARROW_CACHE 89 AXI4/AXI3 Master cannot issue a transfer with
ARLEN > 0 and ARCACHE modifiable
bit is not asserted.
AW Master cannot issue AWLEN
XILINX_AW_MAX_BURST 90 AXI4/AXI3 greater than the configured maximum
burst length.
AR Master cannot issue ARLEN greater
XILINX_AR_MAX_BURST 91 AXI4/AXI3 than the configured maximum burst
length.
AWREADY is Low for the first cycle
XILINX_AWVALID_RESET 92 AXI4/AXI3/Lite
after ARESETn goes High.
WREADY is Low for the first cycle after
XILINX_WVALID_RESET 93 AXI4/AXI3/Lite
ARESETn goes High.
BREADY is Low for the first cycle after
XILINX_BVALID_RESET 94 AXI4/AXI3/Lite
ARESETn goes High.
ARREADY is Low for the first cycle
XILINX_ARVALID_RESET 95 AXI4/AXI3/Lite
after ARESETn goes High.
RREADY is Low for the first cycle after
XILINX_RVALID_RESET 96 AXI4/AXI3/Lite
ARESETn goes High.

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 Chapter 3

Designing with the Core

This chapter includes guidelines and additional information to facilitate designing with the
core.

General Design Guidelines

The AXI Protocol Checker should be inserted into a system as shown in Figure 3-1.
X-Ref Target - Figure 3-1

aclk

aresetn

AXI AXI
Master Slave

AW/W/B

AR/R

system_resetn AXI Protocol Checker pc_status

X13126

Figure 3‐1: Example Topology

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 Chapter 3: Designing with the Core

Finding protocol violations in simulation is generally easier. Therefore, it is highly

recommended to debug a system in simulation rather than in hardware. In simulation, it is
possible to instantiate protocol checkers on all AXI interfaces.

Simulation
When simulating, the AXI Protocol Checker can be configured to print display messages in
the form of:

<time>ns : <instance_path> : BIT( <bit_number>) : <log_level> : <violation_message>

Table 3‐1: Message Field Descriptions
Message Field Description
<instance_path> The simulation hierarchy to the protocol checker instance that is issuing
the message.
<bit_number> Indicates which bit is asserted in the pc_status vector. This bit can be used
to look up the violation in Table 2-6 and Table 2-7.
<log_level> Messaging level text that can be one of the following values: INFO,
WARNING, or ERROR with the ability to stop or finish the simulation. This
value is set in the configuration Vivado IDE.
<violation_message> Descriptive message indicating the name of the violation (for example,
AXI_ERRS_RID) and violation. In most cases, this includes the location in the
AXI specification where the protocol is described. The violation message
name can be used to look up the violation in Table 2-6 and Table 2-7.

For example:

73717.00ns : tb.top.AXI4_0.REP : BIT(59) : ERROR : AXI_ERRS_RID. A slave can only

give read data with an ID to match an outstanding read transaction. Spec: section 8.3
on page 8-4.

In this example, the core provides a debugging capability for simulation where the AXI
Protocol Checker can either finish or stop the simulation at the point of detecting the
violation.

Hardware In-system Monitoring

The AXI Protocol Checker tracks Read and Write transactions by their ARID and AWID
respectively. Therefore, the wider the ID width, the greater amount of resources are
consumed by the Protocol Checker. The transaction information per ID is stored until the
transactions are completed, and the depth of the memory is directly related to the number
of outstanding transactions that can occur for a given transaction ID.

IMPORTANT: Configure the core to ensure the core is not over-monitoring and wasting resources. An ID
width greater than 6 bits can lead to very large resource utilization by the core.

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 Chapter 3: Designing with the Core

Integration into Vivado Logic Analyzer and Vivado Debug Nets

The AXI Protocol Checker core supports probing using the Vivado ILA 2.0 core and the
Vivado Logic Analyzer. All of the protocol checks named in both Table 2-6 and Table 2-7 are
available as Unassigned Debug Nets in the synthesized design. See Vivado Design Suite
Tutorial: Programming and Debugging (UG936) [Ref 5].

Clocking
The same aclk that is connected to both the AXI Master and AXI Slave should also be
connected to the AXI Protocol Checker.

Resets
System Reset and AXI Reset
At a minimum, the AXI Protocol Checker requires the aresetn signal. system_resetn
can be configured to clear the pc_status vector without resetting the AXI4 interface. Both
reset inputs are synchronous to aclk. The assertion of either reset clears the pc_status
vector and the pc_asserted output.

TIP: Xilinx recommends asserting aresetn for a minimum of 16 clock cycles.

If system_resetn is enabled, the Protocol Checker can check the AXI4 specification that
defines the state of the interface following the de-assertion of aresetn. Protocol violation
notifications related to the required behavior of interface with respect to aresetn are
cleared using system_resetn.

When a system reset is not available, the system_resetn should be disabled. When this is
done, the following checks are not possible:

• AXI_ERRM_AWVALID_RESET
• AXI_ERRM_ARVALID_RESET
• AXI_ERRM_WVALID_RESET
• AXI_ERRM_RVALID_RESET
• AXI_ERRM_BVALID_RESET
• XILINX_AWREADY_RESET
• XILINX_WREADY_RESET

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 Chapter 3: Designing with the Core

• XILINX_BREADY_RESET
• XILINX_ARREADY_RESET
• XILINX_RREADY_RESET

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 Chapter 4

Design Flow Steps

This chapter describes customizing and generating the core, constraining the core, and the
simulation, synthesis and implementation steps that are specific to this IP core. More
detailed information about the standard Vivado® design flows and the IP integrator can be
found in the following Vivado Design Suite user guides:

• Vivado Design Suite User Guide: Designing IP Subsystems using IP Integrator (UG994)
[Ref 3]
• Vivado Design Suite User Guide: Designing with IP (UG896) [Ref 6]
• Vivado Design Suite User Guide: Getting Started (UG910) [Ref 8]
• Vivado Design Suite User Guide: Logic Simulation (UG900) [Ref 7]

Customizing and Generating the Core

This section includes information about using Xilinx tools to customize and generate the
core in the Vivado Design Suite environment. You can customize the IP for use in your
design by specifying values for the various parameters associated with the IP core using the
following steps:

1. Select the IP from the IP catalog.

2. Double-click the selected IP or select the Customize IP command from the toolbar or
right-click menu.

For details, see the Vivado Design Suite User Guide: Designing with IP (UG896) [Ref 6] and
the Vivado Design Suite User Guide: Getting Started (UG910) [Ref 8].

Note: Figures in this chapter are illustrations of the Vivado Integrated Design Environment (IDE).
This layout might vary from the current version.

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 Chapter 4: Design Flow Steps

X-Ref Target - Figure 4-1

Figure 4‐1: AXI Protocol Checker Customization IDE

Modify the parameters to meet the requirements of the larger project into which the core is
integrated. The following subsections discuss the options in detail to serve as a guide.

Global Parameters
• Component Name: The base name of the output files generated for the core. Names
must begin with a letter and can be composed of any of the following characters: a to z,
0 to 9, and “_”.
• Connection Protocol: Specifies the type of interface for the AXI Protocol Checker to
monitor: AXI4, AXI3 or AXI4-Lite. Certain protocol checks are not performed based on
this parameter.
Note: This value is automatically set when using IP integrator.
• READ_WRITE Mode: Indicates which channels of the interface are active. When
READ_WRITE mode is selected, all five channels are active. In WRITE_ONLY mode, only
the AW, W, and B channels are active. In READ_ONLY mode, only AR and R channels are
active.
Note: This value is automatically set when using IP integrator.

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 Chapter 4: Design Flow Steps

• Address Width: Specifies the width of the awaddr and araddr signals to be
monitored. Protocol checks use these signals for validation of the transactions. For AXI4
and AXI3 protocols, the minimum width is 12 bits, and for AXI4-Lite, the minimum
width is 1 bit.
• Data Width: Specifies the width of the Write and Read data path interfaces and its
companion signals. Protocol checks use these signals for validation of the transactions.
For AXI4 and AXI3 protocols, the value can be any of: 32, 64, 128, 256, 512, or 1024 bits.
For AXI4-Lite, the value can be either 32 or 64 bits.
Note: This value is automatically set when using IP integrator.
• ID Width: This parameter specifies the width of the awid, arid, bid, wid (for AXI3)
and rid signals. This parameter is not available when the protocol is AXI4-Lite. The ID
width is used for transaction completion tracking and checking and will generate one
FIFO for each ID value.
Note: This value is automatically set when using IP integrator.

User Signal Widths

• AWUSER Width: Specifies the width of the awuser signals (if any) to be monitored by
the protocol checker. This value is only available when the protocol is AXI4 or AXI3. If
set to 0, the signal is omitted.
Note: This value is automatically set when using IP integrator.
• ARUSER Width: Specifies the width of the aruser signals (if any) to be monitored by
the protocol checker. This value is only available when the protocol is AXI4 or AXI3. If
set to 0, the signal is omitted.
Note: This value is automatically set when using IP integrator.
• WUSER Width: Specifies the width of the wuser signals (if any) to be monitored by the
protocol checker. This value is only available when the protocol is AXI4 or AXI3. If set to
0, the signal is omitted.
Note: This value is automatically set when using IP integrator.
• RUSER Width: Specifies the width of the ruser signals (if any) to be monitored by the
protocol checker. This value is only available when the protocol is AXI4 or AXI3. If set to
0, the signal is omitted.
Note: This value is automatically set when using IP integrator.
• BUSER Width: Specifies the width of the buser signals (if any) to be monitored by the
protocol checker. This value is only available when the protocol is AXI4 or AXI3. If set to
0, the signal is omitted.
Note: This value is automatically set when using IP integrator.

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 Chapter 4: Design Flow Steps

Parameter Checker Options

• Maximum outstanding READ transactions Per ID: Specifies the depth of the FIFOs
for storing the outstanding Read transactions per ID. The value should be equal to or
greater than the number of outstanding Read transactions for that connection.
• Maximum outstanding WRITE transactions PER ID: Specifies the depth of the FIFOs
for storing the outstanding Write transactions. The value should be equal to or greater
than the number of outstanding Write transactions for that connection.
• Maximum number of idle cycles for AWREADY monitoring: This parameter specifies
the maximum number of cycles between the assertion of awvalid to the assertion of
awready before an ERROR is generated. When the value is set to 0, this check is
disabled.
• Maximum number of idle cycles for ARREADY monitoring: This parameter specifies
the maximum number of cycles between the assertion of arvalid to the assertion of
arready before an ERROR is generated. When the value is set to 0, this check is
disabled.
• Maximum number of idle cycles for WREADY monitoring: This parameter specifies
the maximum number of cycles between the assertion of wvalid to the assertion of
wready before an ERROR is generated. When the value is set to 0, this check is
disabled.
• Maximum number of idle cycles for RREADY monitoring: This parameter specifies
the maximum number of cycles between the assertion of rvalid to the assertion of
rready before an ERROR is generated. When the value is set to 0, this check is
disabled.
• Maximum number of idle cycles for BREADY monitoring: This parameter specifies
the maximum number of cycles between the assertion of bvalid to the assertion of
bready before an ERROR is generated. When the value is set to 0, this check is
disabled.
• Simulation Log Messaging Level: When a violation is triggered, this parameter allows
the core to indicate to the simulation log file different error levels or to disable all
messaging entirely. It is also possible to use this parameter to stop or finish the
simulation upon a protocol violation occurrence.
• Xilinx Connection Checking of Supports Narrow Bursts: If set to no, this parameter
specifies that the protocol checker should trap narrow burst violations on the
connection. This attribute is not available for AXI4-Lite interfaces.
Note: This value is automatically set when using IP integrator.
• Xilinx Maximum Connection Burst Length: The protocol checker should trap
transactions lengths which exceed the value indicated by this parameter. The default
value varies by protocol and is not available for AXI4-Lite interfaces.
Note: This value is automatically set when using IP integrator.

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 Chapter 4: Design Flow Steps

• Enable system reset interface: Enables the system_resetn port. When disabled, the
port is tied High.

User Parameters
Table 4-1 shows the relationship between the fields in the Vivado IDE and the User
Parameters (which can be viewed in the Tcl console).

Table 4‐1: Vivado IDE Parameter to User Parameter Relationship

Vivado IDE Parameter/Value User Parameter/Value Default Value
Connection Protocol PROTOCOL AXI4
READ_WRITE Mode READ_WRITE_MODE READ_WRITE
Address Width ADDR_WIDTH 32
Data Width DATA_WIDTH 32
ID Width ID_WIDTH 0
AWUSER Width AWUSER_WIDTH 0
ARUSER Width ARUSER_WIDTH 0
WUSER Width WUSER_WIDTH 0
RUSER Width RUSER_WIDTH 0
BUSER Width BUSER_WIDTH 0
Maximum Outstanding Read
MAX_RD_BURSTS 8
Transactions per ID
Maximum Outstanding Write
MAX_WR_BURSTS 8
Transactions per ID
Maximum Number of Idle Cycles
MAX_AW_WAITS 0
for AWREADY Monitoring
Maximum Number of Idle Cycles
MAX_AR_WAITS 0
for ARREADY Monitoring
Maximum Number of Idle Cycles
MAX_W_WAITS 0
for WREADY Monitoring
Maximum Number of Idle Cycles
MAX_R_WAITS 0
for RREADY Monitoring
Maximum Number of Idle Cycles
MAX_B_WAITS 0
for BREADY Monitoring
Simulation Log Messaging Level MESSAGE_LEVEL
• Quiet • 0
• Info • 1
2 (Error)
• Error • 2
• Stop on error • 3
• Finish on error • 4

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Table 4‐1: Vivado IDE Parameter to User Parameter Relationship (Cont’d)

Vivado IDE Parameter/Value User Parameter/Value Default Value
Xilinx Connection Checking of
SUPPORTS_NARROW_BURST
Supports Narrow Burst
• 0 1 (Yes)
• No
• 1
• Yes
Xilinx Maximum Connection
MAX_BURST_LENGTH 256
Burst Length
Enable System Reset Interface HAS_SYSTEM_RESET
• No • 0 0 (No)
• Yes • 1

Output Generation
The AXI Protocol Checker deliverables are organized in the directory <project_name>/
<project_name>.srcs/sources_1/ip/<component_name> and is designed as
the <ip_source_dir>.

For details, see the Vivado Design Suite User Guide: Designing with IP (UG896) [Ref 6].

Constraining the Core

This section contains information about constraining the core in the Vivado® Design Suite.

Required Constraints
There are no required constraints for this core.

Device, Package, and Speed Grade Selections

See IP Facts for details on device support.

Clock Frequencies
There are no clock frequency constraints for this core.

Clock Management
There are no clock management constraints for this core.

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 Chapter 4: Design Flow Steps

Clock Placement
There are no clock placement constraints for this core.

Banking
There are no banking constraints for this core.

Transceiver Placement
There are no transceiver placement constraints for this core.

I/O Standard and Placement

There are no I/O constraints for this core.

Simulation
For details, see Vivado Design Suite User Guide: Logic Simulation (UG900) [Ref 7].

Synthesis and Implementation

For details about synthesis and implementation, see the Vivado Design Suite User Guide:
Designing with IP (UG896) [Ref 6].

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 Appendix A

Debugging
This appendix includes details about resources available on the Xilinx Support website and
debugging tools.

Finding Help on Xilinx.com

To help in the design and debug process when using the AXI Protocol Checker, the Xilinx
Support web page contains key resources such as product documentation, release notes,
answer records, information about known issues, and links for obtaining further product
support.

Documentation
This product guide is the main document associated with the AXI Protocol Checker. This
guide, along with documentation related to all products that aid in the design process, can
be found on the Xilinx Support web page or by using the Xilinx Documentation Navigator.

Download the Xilinx Documentation Navigator from the Downloads page. For more
information about this tool and the features available, open the online help after
installation.

Answer Records
Answer Records include information about commonly encountered problems, helpful
information on how to resolve these problems, and any known issues with a Xilinx product.
Answer Records are created and maintained daily ensuring that users have access to the
most accurate information available.

Answer Records for this core can be located by using the Search Support box on the main
Xilinx support web page. To maximize your search results, use proper keywords such as

• Product name
• Tool message(s)
• Summary of the issue encountered

A filter search is available after results are returned to further target the results.

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 Appendix A: Debugging

Master Answer Record for the AXI Protocol Checker

AR: 57790

Technical Support
Xilinx provides technical support at the Xilinx Support web page for this LogiCORE™ IP
product when used as described in the product documentation. Xilinx cannot guarantee
timing, functionality, or support if you do any of the following:

• Implement the solution in devices that are not defined in the documentation.
• Customize the solution beyond that allowed in the product documentation.
• Change any section of the design labeled DO NOT MODIFY.

To contact Xilinx Technical Support, navigate to the Xilinx Support web page.

General Checks
The AXI Protocol Checker design limits the types of problems one may encounter when
using the core. In the case where the interface is not fully specified, the system designer
must ensure that any unused inputs to the AXI Protocol Checker have been correctly tied off
based on the AXI Protocol that is to be monitored using Table 2-3, Table 2-4, or Table 2-5.

Debug Tools
Vivado Design Suite Debug Feature
The Vivado® Design Suite debug feature inserts logic analyzer and virtual I/O cores directly
into your design. The debug feature also allows you to set trigger conditions to capture
application and integrated block port signals in hardware. Captured signals can then be
analyzed. This feature represents the functionality in the Vivado IDE that is used for logic
debugging and validation of a design running in Xilinx devices in hardware.

The AXI4 Protocol Checker core supports probing using the Vivado ILA 2.0 core and the
Vivado Logic Analyzer. All of the protocol checks named in Table 2-3, Table 2-4, and
Table 2-5 are available as Unassigned Debug Nets in the synthesized design. More details
can be found in the Vivado Design Suite Tutorial: Programming and Debugging on the Vivado
Design Suite [Ref 5].

It is also possible to monitor all or one bit of the pc_status vector through any other
desired method.

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 Appendix A: Debugging

Clocks and Resets

To resolve clocking and reset issues, verify these items:

• Check that aclk is connected to the same clock that is driving both the Master and
Slave interfaces.
• Check that aresetn is connected to the same reset that is driving both the Master and
Slave interfaces.
• Ensure that both aresetn and system_resetn (if enabled) are connected to
active-Low polarity.
• Ensure that aresetn is both synchronously asserted and released on aclk.

Core Size and Optimization

In some cases the size of the core can become very large. The following tips can reduce the
size of the core:

• Set the Maximum number of idle cycles for (AW|AR|W|R|B) READY monitoring to
0. This disables a recommended *VALID to *READY wait checks.
• If possible, reduce the ID Width. This directly reduces the number of ID tracker and
block RAMs.
• Reduce either or both of Maximum outstanding READ transactions PER ID or
Maximum outstanding WRITE transactions PER ID.
• Each bit of the pc_status vector consumes some amount of resources; therefore,
fewer bits observed reduces the overall foot print of the design.

Flags
No Flags Asserted
One simple test to check to see if the AXI Protocol Checker is correctly connected to the
interface is to not connect the pc_axi_arready or the pc_axi_awready input into the
protocol checker and to tie those ports to 0. This causes the pc_asserted output and
multiple bits in the pc_status vector to be asserted when AXI traffic begins because this
will violate all the AXI_ERRS_A*_STABLE protocol checks (bits 46 - 56). See Table 2-6 for the
descriptions of these checks.

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 Appendix A: Debugging

Flags Asserted
If there are bits asserted in the pc_status vector and the source/reason of the violation
using Table 2-6 is not clear, move the AXI Protocol Checker “upstream” toward the AXI
Master generating the transactions.

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 Appendix B

Migrating and Upgrading

This appendix contains information about migrating a design from ISE® to the Vivado®
Design Suite, and for upgrading to a more recent version of the IP core. For customers
upgrading in the Vivado Design Suite, important details (where applicable) about any port
changes and other impact to user logic are included.

Migrating to the Vivado Design Suite

For information about migrating to the Vivado Design Suite, see the Vivado Design Suite
Migration Methodology Guide (UG911) [Ref 9].

Upgrading in the Vivado Design Suite

This section provides information about any changes to the user logic or port designations
that take place when you upgrade to a more current version of this IP core in the Vivado
Design Suite.

Parameter Changes
There are no parameter changes.

Port Changes
There are no port changes.

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 Appendix C

Additional Resources and Legal Notices

Xilinx Resources
For support resources such as Answers, Documentation, Downloads, and Forums, see Xilinx
Support.

References
These documents provide supplemental material useful with this product guide:

1. ARM® AMBA® AXI Protocol v2.0, ARM IHI 0022C

2. AMBA® 4 AXI4™, AXI4-Lite™, and AXI4-Stream™ Protocol Assertions User Guide
3. Vivado Design Suite User Guide: Designing IP Subsystems using IP Integrator (UG994)
4. Xilinx Vivado AXI Reference Guide (UG1037)
5. Vivado Design Suite Tutorial: Programming and Debugging (UG936)
6. Vivado Design Suite User Guide: Designing with IP (UG896)
7. Vivado Design Suite User Guide: Logic Simulation (UG900)
8. Vivado Design Suite User Guide: Getting Started (UG910)
9. Vivado Design Suite Migration Methodology Guide (UG911)

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 Appendix C: Additional Resources and Legal Notices

Revision History
The following table shows the revision history for this document.

Date Version Revision

10/05/2016 1.1 Updated “AXI_ERRS_RID” protocol support and description.
11/18/2015 1.1 Added support for UltraScale+ families.
04/01/2015 1.1 • Added “User Parameters” in the Design Flow Steps chapter.
12/18/2013 1.1 • Added support for UltraScale™ architecture.
10/02/2013 1.1 • Added compatibility with AXI Interconnect v2.1.
• Added Chapter 6, Simulation and Chapter 7, Synthesis and
Implementation.
06/19/2013 1.0 • Updated Parameter Checker Options in Chapter 4.
• Clarified bit options for pc_status vector.
12/18/2012 1.0 Initial Xilinx release.

Please Read: Important Legal Notices

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