DP Darshan 1 - Logic Function Realization with MSI Iran Earn cone Circuits AND Gate ‘+ An AND gate has two or more inputs but only one output. ‘© The output assumes the logic 1, only when each one of its inputs is at logic 1 ‘+The output assumes the logic 0 even if one ofits inputs is at logic 0. * The logic symbol & truth table are shown in below figure. 0 0 0 ss : 0 3 E 1 0 0 1 1 i OR Gate An OR gate has two or more inputs but only one output. ‘© The output assumes the logic 0, only when each one of its inputs is at logic 0. © The output assumes the logic 1 even if one of its inputs is at logic 1. The logic symbol & truth table are shown in below figure. Notation:- C=A+B A B c le |e lo Binlolo lolH lo fy NOT Gate ANOT gate (also called an inverter) has only one input & one output. Itis a device whose output is always the complement of its input. The output assumes the logic 2, when its input is at logic 0. The output assumes the logic 0, when its input is at logic 1. ‘The logic symbol & truth table are shown in below figure. Notation:- C = A A c 0 1 1 0 NAND Gate (Universal Gate) ‘+ NAND means NOT AND, i.e. the AND output is NOTed. ‘+The output assumes the logic 0, only when each one of its inputs is at logic 1. Krunal D. Vyas, CE Department | 3130704 ~ Digital Fundamentals 1DP Darshan 1 - Logic Function Realization with MSI Iran Earn cone Circuits * The output assumes the logic 1 even if one of its inputs is at logic 0 ‘+ The logic symbol & truth table are shown in below figure. © Notation:- ¢=A-B 4 c a NOR Gate (Universal Gate) ‘+ NOR means NOT OR, i.e. the OR output is NOTed. ‘+ The output assumes the logic 1, only when each one of its inputs is at logic 0. ‘+The output assumes the logic 0 even if one ofits inputs is at logic 1. The logic symbol & truth table are shown in below figure. * Notation:- C=A+B A B c ofp} a] 4 iB BlRlolo lols )olE ololo|e ls nlelolo plole|o fy EX-OR Gate ‘An X-OR gate has two or more inputs but only one output. ‘The output assumes the logic 1 when one and only one of its inputs assumes a logic 2. ‘+ Under the conditions when both the inputs assume the logic 0, or when both the inputs assume the logic 1, the output assumes a logic 0. '* Since, an X-OR gate produces an output 1 only when the inputs are not equal, itis called an anti- coincidence gate or inequality detector. ‘© The logic symbol & truth table are shown in below figure. + Notation:- C= A @B A B G EX-NOR Gate '* An X-NOR gate has two or more inputs but only one output. ‘+ The output assumes the logic 0 when one and only one of its inputs assumes a logic 0. ‘* Under the conditions when both the inputs assume the logic 1, or when both the inputs assume the logic 1, the output assumes a logic 0. ole |H|o [ey le lolo rlolH | of Krunal D. Vyas, CE Department | 3130704 ~ Digital Fundamentals 2Darshan & 1 - Logic Function Realization with MSI Circuits gate or equality detector. Notation: C=A@B > A B Basic Gates as Universal Gates Implementation of NOT, AND & OR gates using NOT using NAND gate ‘Since, an X-NOR gate produces an output 1 only when the inputs are equal, itis called a coincidence The logic symbol & truth table are shown in below figure. oO oO 1 0 1 0 1 0 0 1 z 1 NAND gate only ‘ANAND gate can also be used as an inverter by tying all its input terminals together and applying the signal to be inverted to the common terminal as AND using NAND gate ‘+ NAND means NOT AND, i.e. the AND output So, a NAND gate is combination of an AND g (AB) A B OR using NAND gate ‘© By inverting inputs in NAND gate, a OR gate AB= A+B=A+B — > is NOTed, ate and a NOT gate. (aBy'Y = AB is constructed via De Morgan's theorem. | > (wey = qe Implementation of NOT, AND & OR gates using 1. NOTusing NOR gate NOR gate only ANOR gate can also be used as an inverter by tying all its input terminals together and applying the signal to be inverted to the common terminal. ‘Krunal D. Vyas, CE Department | 3130704 — Digital Fundamentals 3Darshan 1 - Logic Function Realization with MSI ome enaere sot Circuits <> 2. OR using NOR gate ‘+ NOR means NOT OR, i.e. the OR output is NOTed. ‘+ So, a NOR gate is combination of an OR gate and a NOT gate. (asBy’ (A+B)')’ = AB A B 3. AND using NOR gate . inputs in NOR gate, a AND gate is constructed via De Morgan's theorem. (A’+B’)' = AB © AND laws (Wull Law) (Identity Law) + Commutative laws 1 A+B=BHA 2. AB=B-A © Associative laws 1, (A+B) +C=A+(B+C) 2. (A-B)C =A(B-C) © Distributive laws 1 AB +C) 2. A+B AB + AC (+B)A+0) Krunal D. Vyas, CE Department | 3130704 |1 - Logic Function Realization with MSI Circuits © Redundant Literal Rule 1. A+AB=A+B 2. A(A+B) = AB ‘* Idempotence laws 1 A‘A=A 2. A+A=A + Absorption laws 1 A+AB=A 2. AA+B)=A De Morgan’s Theorem 1. lawi:AFBFC=ABC ‘© This law states that the complement of a sum of variables is equal to the product of their individual complements. AYBeC °. plale|elolololo|> nlplolo|H|Hlolole BlolHlolHlolulola ps] |a|e |e] ello elolofole)e|a|el> olo|H|elolole |e ‘+ Hence, Law 1 is proved from the above truth table. 2. law2;ABC=A+B+6 ‘+ This law states that the complement of a product of variables is equal to the sum of their individual complements. ° || a) lolololo/> lo|H/o}H fo} fo}. |a| | |olo|4|H)olo|m Hlo|H)o}4lolnlola slololololololole lolololoa |e sala /> lolo|H|Hlololee Hence, Law 2 is proved from the above truth table, Krunal yas, CE Department | 3130704.Darshan 1 - Logic Function Realization with MSI Circuits Reduction of Boolean Expression [B + € (AB + AC)) [2 + C (AB A (8 +CA+ RAO] [B +0 (4A+ Ac + BA + Bc)] =AlB+E (4+ AC + AB + BC)) (B + CA + CAC + CAB + CBC) (B + AC +0 + ABC + 0) = AB + AAC + AABC B 1 f 2: + BIAC + (B +C)D] + BAC + BD + CD] =A+BAC + BBD + BCD +ABC + BD + BCD (1 + BC) + BDA +0) “14BD+1 +BD Common Number Systems (De Morgan's Theorem) (De Morgan’s Theorem) (Distributive Law) (ew =a) (Distributive Law) (C-C'=0) (A-a'=0) (Distributive Law) (Distributive Law) (B-B=B) (1+#A=a) ‘+ There are mainly four number systems which are used in digital electronics platform. 1. Decimal number system The decimal number system contains ten unique symbols 0, 1, 2, 3,4,5, 6, 7,8,9. © The base or radix is 10. 9's and 10's complements are possible for any decimal number. 2. Binary number system (© The binary number system contains two unique symbols 0, 1. © The base or radixis 2. © 1’sand 2’s complements are possible for any binary number. Octal number system ‘The base or radix is 8. ooo Hexadecimal number system on B,C, 0, E,F. ‘The base or radix is 16. ‘The actal number system contains eight unique symbols 0, 1, 2, 3, 4,5, 6, 7. 7's and 8's complements are possible for any octal number. ‘The hexadecimal number system contains sixteen unique symbols 0, 1, 2, 3, 4, 5, 6, 7,8,9, A, 15's and 16's complements are possible for any hexadecimal number. Krunal D. Vyas, CE Department | 3130704 — Digital Fundamentals 6Darshan 1 - Logic Function Realization with MSI ome enaere sot Circuits In general, if radix or base of a number system is “r’, then there is possibility of r’s complement and (r-1)'s complement of a number. Decimal to Binary Conversion The decimal integer is converted to the binary integer number by successive division by 2, and the decimal fraction is converted to the binary fraction number by successive multiplication by 2. In the successive division-by-2 method, the given decimal integer number is successively divided by 2till the quotient is 0 The remainders read from bottom to top give the equivalent binary integer number. In the successive multiplication-by-2 method, the given decimal fraction and the subsequent fractions are successively multiplied by 2, tll the fraction part of the product is 0 or till the desired accuracy is obtained, ‘The integers read from top to bottom give the equivalent binary integer number. To convert a mixed number to binary, convert the integer and fraction parts separately to binary, and then combine them. Example:- (125.6875)ao = ()2 2 | 125 | 2 0.6875 x2=1.3750 | 1+0.3750 2[ 2 [0 0.3750x2=0.7500 | 0+0.7500 2 [31 [a 0.7500x2=1.5000 | 1 +0.5000 2 [as [a 0.5000 2= 1.0000 ¥1+0.0000 2/7 [4 2[3 /4 Hence, (125.6875)10= (1121101.1011)2 2f4a/4 0 Binary to Decimal Conversion Binary numbers may be converted to their decimal equivalents by the positional weights method. In this method, each binary digit of the number is multiplied by its position weight (2°, where n is the weight of the bit) and the product terms are added to obtain the decimal number. Example:- (101011.11)2= (so = 1x2® 4 0x2" 1x2? + OK2?+ 124+ 14294 1x22 + 1x2? =32+0+8+0+2+1405+0.25 = 43.75 Hence, (101011.11)2 = (43.75)0 Krunal D. Vyas, CE Department | 3130704 — Digital Fundamentals 7Darshan 1 - Logic Function Realization with MSI ome enaere sot Circuits Decimal to Octal Conversion © The decimal integer is converted to the octal integer number by successive division by 8, and the decimal fraction is converted to the octal fraction number by successive multiplication by 8. + Inthe successive division-by-8 method, the given decimal integer number is successively divided by 8 till the quotient is 0. +The remainders read from bottom to top give the equivalent octal integer number. In the successive multiplication-by-8 method, the given decimal fraction and the subsequent fractions are successively multiplied by 8, till the fraction part of the product is 0 or till the desired accuracy is obtained. © The integers read from top to bottom give the equivalent octal integer number. * Toconvert a mixed number to octal, convert the integer and fraction parts separately to octal and then combine them, * Example:- (125.6875)io = ( )s 8 | 125 | 5 0.6875 x8 = 5.5000 { +0.5000 8 [15 [7 0.5000 x8 = 4.0000 44 +0.0000 a[a[a 0 Hence, (125.6875)io = (175.54)s Octal to Decimal Conversion * Octal numbers may be converted to their decimal equivalents by the positional weights method, ‘+ Inthis method, each octal digit of the number is multiplied by its position weight (8°, where n is the weight of the bit) and the product terms are added to obtain the decimal number. © Example:- (724.25)s= (jo = 7x8? + 2x8! + 4x89 + 2x8" + 5x8? = 408 +16 +.4+0.25 + 0.0781 = 468.3281 Hence, (724.25)s = (468.3281) Decimal to Hexadecimal Conversion '* The decimal integer is converted to the hexadecimal integer number by successive division by 16, and the decimal fraction is converted to the hexadecimal fraction number by successive multiplication by 16. ‘* Inthe successive division-by-16 method, the given decimal integer number is successively divided by 16 till the quotient is 0. ‘+ The remainders read from bottom to top give the equivalent hexadecimal integer number. Krunal D. Vyas, CE Department | 3130704 — Digital Fundamentals 8Darshan 1 - Logic Function Realization with MSI ome enaere sot Circuits * In the successive multiplication-by-16 method, the given decimal fraction and the subsequent fractions are successively multiplied by 16, tll the fraction part of the products 0 or till the desired accuracy is obtained. * The integers read from top to bottom give the equivalent hexadecimal integer number. ‘+ To convert a mixed number to hexadecimal, convert the integer and fraction parts separately to hexadecimal and then combine them. © Example: (2598.675)10= ()is 16 |2598| 6 + 0.6750 x 16 = 10,8000 | 10(A) + 0.8000 16 | 162 | 2 0.8000 x 16 = 12.8000 | 12(C) + 0.8000 16 | 10 | 10(a) 0.8000 x 16 = 12.8000 | 12(C) + 0.8000 0 0.8000 x 16 = 12.8000 ¥ 12(C) + 0.8000 Hence, (2598.675)so = (A26.ACCC)sc Hexadecimal to Decimal Conversion '* Hexadecimal numbers may be converted to their decimal equivalents by the positional weights method. '* In this method, each hexadecimal digit of the number is multiplied by its position weight (16", where n is the weight of the bit) and the product terms are added to obtain the decimal number. ‘© Example:- (AOF9.08):6 = ()so = 10x16? + 0x16? + 15x16" + 9x16" + Ox16" + 14x16? + 11x16" = 40960 + 0+ 240 +9 + 0 + 0.0546 + 0.0026 = 41209.0572 Hence, (AOF9.OEB) (41209.0572):0 Octal to Binary Conversion * To convert a given octal number to a binary, just replace each octal digit by its 3-bit binary equivalent as per below table. Octal Number Binary Number oO 000 [ 001 010 ou 100 102 110 a Krunal D. Vyas, CE Department | 3130704 — Digital Fundamentals 9Dp Darshan 1 - Logic Function Realization with MSI ome enaere sot Circuits ‘© Example:- (367.52)s= (Je =011 110 111.101 010 = 11110111.10101 Hence, (367.52)s (11110111.10101)2 Binary to Octal Conversion ‘+ To convert a binary number to an octal number, starting from the binary point make groups of 3 bits each (i.e. from point (".") in binary number, group of 3 bits in left side and group of 3 bits in right side), if there are not 3 bits available at last, just stuff “0” to make 3 bits group. ‘+ Replace each 3-bit binary group by the equivalent octal digit. © Example:-(110101,101010)2 = ()e = 110 101, 101 010 = 65.52 Hence, (110101.101010)2 = (65.525 Hexadecimal to Binary Conversion ‘* To convert a given hexadecimal number to a binary, just replace each hexadecimal digit by its 4- bit binary equivalent as per below table. Hexadecimal Number Binary Number oO (0000 0001 (0010 011 0100 0101 0110 0111 1000 1001 1010 1011 11100 1101 1110 111 a] mfo|or|a|> | co) wor |un| = fur] fn. Krunal D. Vyas, CE Department | 3130704 | 101 - Logic Function Realization with MSI Circuits & Darshan © Example:- (3A9E.BOD):6 = ( )2 =0011 1010 1001 1110. 1011 0000 1101 = 11101010011110.101100001101 Hence, (3A9E.BOD)ac = (11101010011110.101100001101), Binary to Hexadecimal Conversion ‘+ Toconvert a binary number to a hexadecimal number, starting from the binary point make groups of 4 bits each (i.e. from point (".”) in binary number, group of 4 bits in left side and group of 4 bits, in right side), if there are not 4 bits available at last, just stuff “0” to make 4 bits group. ‘+ Replace each 4-bit binary group by the equivalent hexadecimal digit. © Examples (01011111011.011111), = ( je =0010 1111 1011..0111 1100 = 2FB7C Hence, (01011111011.011111)2 = (2FB.7Chis Octal to Hexadecimal Conversion '* To convert an octal number to hexadecimal, the simplest way is to first convert the given octal number to binary and then the binary number to hexadecimal. (.e. first from table of 3-bit and then table of 4-bit) © Example = (756.603)5 = (Jis =7 5 6.6 0 3 111 101 110, 110 000 011 = 9001 1110 1140 . 1100 9001 1000 1 — —€.C 1 8 Hence, (756.603)s = (1EE.C18)is Hexadecimal to Octal Conversion * To convert a hexadecimal number to octal, the simplest way is to first convert the given hexadecimal number to binary and then the binary number to octal. (ie. first from table of 4-bit and then table of 3-bit) © Example :- (B9F.AE)sc = (Je = B 9 F.A E 1011 1001 1111 . 1010 1110 Krunal D. Vyas, CE Department | 3130704 — Digital Fundamentals 11Darshan 1 - Logic Function Realization with MSI ome enaere sot Circuits 101 110 011 111 . 101 011 100 5 637.53 4 Hence, (BSF.AE)ss = (5637.534)e Accuracy in Binary Number Conversion ‘+ Example:- Convert (0.252}:0 to binary with an error less than 1% ‘+ Absolute value of allowable error is found by calculating 1% of the number. Eguow = 0.01 ¥ 0,252 = 0.025210 ‘+ Maximum error due to truncation is set to be less than allowable error by solving from Eo = 2 This equation is written as 2" < 0.00252 Inverting both sides of the inequality 2" > 397 Taking log of both sides and solving for n nlog2 = log 397 = tog397 = “Togz This indicates that the use of 9 bits in the binary number will guarantee an error less than 1%, 8.63 ~ 9 (next largestinteger) So, the conversion is carried out to 9 places. 0.128x2 = 0.256 0.256x2=0.512 0.S12%2= 1.024 0.252x2= 0.504 |0 0.504x2= 1,008 /1 0.008 x 2 = 0.016 |0 0.016 x 2 = 0.0320 0.032 x 2 = 0.064 | 0 0.064 x2 =0.128|0 0 0 1 ‘* Therefore, (0.252)10 = (0.010000001)2 Krunal D. Vyas, CE Department | 3130704 | 12Darshan 1 - Logic Function Realization with MSI ome enaere sot Circuits Complement Forms + 9's Complement © The 9's complement of a decimal number is obtained by subtracting each digit of that decimal number from 9. © Example:- 782.54 999.99 -182.54 217 . 45 (9's complement of 782.54) * 10's Complement 9 The 10's complement of a decimal numbers obtained by adding a 1 to its 9’s complement. © Shorteut:- Subtract LSB(Least Significant Bit) from 10 and rest of the digits from 9. © Example:- 1056.074 ope wlow wlow 9 7 2 +1 89 43. 9 2 6 (10's complement of 1056.074) + Vs Complement © The 1's complement of a binary number's obtained by subtracting each digit of that binary number from 1. © Shortcut: Change 1’s to 0's and 0's to 1’s in binary number. © Example: 101101.1001 a11111.1111 -101101.1001 010010. 011 O{1's complement of 101101.1001) + 2's Complement © The 2’s complement of a binary number is obtained by adding a 1 to its 1’s complement. © Shortcut: shortcut to manually convert a binary number into its 2's complement is to start at the least significant bit (LSB), and copy all the zeros, working from LSB toward the most significant bit (MSB) until the first 1 is reached; then copy that 1, and flip all the remaining bits. © Example: 110101.10100 a11111.11211 -110101.10100 001010.01011 +1 0.01010. 0110 0(2'scomplement of 110101.10100) Krunal D. Vyas, CE Department | 3130704 — Digital Fundamentals, BDarshan 1 - Logic Function Realization with MSI ome enaere sot Circuits Signed Number Representation ‘+The 2's complement system for representing signed numbers works like this: 1) Ifthe number is positive, the magnitude is represented in its true binary form and a sign bit 0 is placed in front of the MSB. 2) ifthe number is negative, the magnitude is represented in its 2's complement form and a sign bit 1is placed in front of the MSB. + Example: (1) Express -45 in 8-bit 2's complement form. Ans. +45 in &-bit form is 00101101 (By taking decimal to binary conversion). take 2’s complement of it, 11010011 Hence, -45 in 2's complement form is 11010011 (2) Express -73.25 in 12-bit 2's complement form. ‘Ans. +73.25 in 12-bit form is 01001001,1100 (By taking decimal to binary conversion). take 2’s complement of it, 10110110.0100 Hence, -73.25 in 2’s complement form is 10110110.0100 Subtraction using Complement Forms ‘© Subtraction using 9s complement form © Toperform decimal subtraction using the 9's complement method, obtain 9's complement of the subtrahend and add it to the minuend, Call this number the intermediate result. Ifthere is a carry, itindicates that the answer is positive ‘Add the carry to the LSD of this result to get the answer. If there is no carry, it indicates that the answer is negative and the intermediate result is its 9's complement. ©. Take the 9’s complement of this result and place a negative sign in front to get the answer. o Example:- (1) 745.81 ~ 436.62 Ans.745.81 745.81 -436.62 +5 6 3 . 3 7 (9's complement of 436.62) 309.19 @3 09 . 1B (Intermediate result) ed 3.09. 1 9(Answer) (2) 436.62- 745.81 Ans.436.62 436.62 - 245. 81———»42 5 4. 1. 8(9' complement of 745.81) -309.19 6 9.0. 8 O (Intermediate result) ‘There is no carry indicating that the answer is negative. So, take the 9's complement of, the intermediate result and put a minus sign. Therefore, the answer is -309.19 Krunal D. Vyas, CE Department | 3130704 — Digital Fundamentals 14D Darshan 1 - Logic Function Realization with MSI ome enaere sot Circuits * Subtraction using 10's complement form ° To perform decimal subtraction using the 10's complement method, obtain the 10’s complement of the subtrahend and add it to the minuend. If there is a carry, ignore it. ‘The presence of the carry indicates that the answer is positive; the result obtained is itself the answer. If there is no carry, it indicates that the answer is negative and the result obtained is its 10's complement. Obtain the 10's complement of the result and place a negative sign in front to get the answer. Example: (1) 2928.54~416.73, Ans.2928.54 2928.54 -0416.73 ———»49 5 8 3. 27 (10's complement of 416.73) 2511.81 1)2§ 11. 8 1 (Ignore the carry) (2) 416.73 - 2928.54 Ans.0416.73 0416.73 -2928.54————47 071. 4 6 (10's complement of 2928.54) -2511.81 7488. 19(Nocarry) ‘There is no carry indicating that the answer is negative. So, take the 10's complement of the intermediate result and put a minus sign. Therefore, the answer is -2511.81 ‘© Subtraction using 1’s complement form To perform binary subtraction using the 1’s complement method, obtain 1's complement of the subtrahend and add it to the minuend, Call this number the intermediate result. If there is a carry, it indicates that the answer is positive. ‘Add the carry to the LSB of this result to get the answer. If there is no carry, it indicates that the answer is negative and the intermediate result is its 1's complement. Take the 1’s complement of this result Example:- (a) 11010-1101 Ans.11010 11010 -01101———*#1 0 0 10(1's complement) @o 1 1 0 o(intermediate result) Seed 0 110 1 (Answer) (2) 100-1000 Ans.000100 oo00100 -110000 +10 0 11 1 1(1’s complement) 1.01001 1 (Intermediate result) ‘There is no carry. The MSB is 1. Hence, the answer is negative. Take the 1's complement of the remaining bits. So, its 101100 (negative). Krunal D. Vyas, CE Department | 3130704 — Digital Fundamentals, 15D Darshan 1 - Logic Function Realization with MSI Circuits * Subtraction using 2's complement form © To perform binary subtraction using the 2’s complement method, obtain the 2's complement of the subtrahend and add it to the minuend. 0 I there is a carry, ignore it. 0 The presence of the carry indicates that the answer is positive; the result obtained is itself the answer. ©. Ifthere is no carry, it indicates that the answer is negative and the result obtained is its 2's complement. © Obtain the 2's complement of the result. © Example:- (a) 12011-1101 Ans.11011 11011 -01101 +100 :11(2's complement) 0 1 1.0 1 (ignore the carry, result is positive) {2} 100-110000 Ans.000100 0000100 -110000-—»41. 0 10 00 0(2's complement) 10 10 1 0 0 (Results negative) There is no carry. The MSB is 1. Hence, the answer is negative. Take its 2's complement and put a minus sign. So it is, 101100 (negative). Binary Operation © Binary Addition 0+0=0; O+1=1; 140= | 1#1=10 (ie. Owitha carry of 1); 1#141=11 Example:- Add the binary numbers 1101.101 and 112.011. 1111 114—Cany 1101.101 +0111.011 0101.000 © Binary Subtraction 0-0=0; 1-1 = Lwith a borrow of 1. Example:- Subtract 111.111 from 1010.01 0.1101 11010 «— Borrow 2020.030 2O141.111 0010.011 ‘Krunal D. Vyas, CE Department | 3130704 — Digital Fundamentals 16Darshan 1 - Logic Function Realization with MSI ome enaere sot Circuits * Binary Multiplication Example:- Multiply 1011.101 by 101.01. 1011.101 X 101.010 1021101 00000000 101110100 9000000000 10111010000 11110100001 Therefore, 1011.101 x 101.010 = 111101.00001 © Binary Division Example:- Divide 101101 by 110. 110)102101(111.1 110 1010 110 1001 1i0 110 110 000 Therefore, 101101 / 110 = 111.1 BCD Code ‘+ Inthis code, each decimal digit, 0 through 9, is coded by 4-bit binary number. ‘+ Itis a weighted code and is also sequential. Therefore, itis useful for mathematical operations. ‘+The main advantage of this code is its ease of conversion to and from decimal. ‘+ [tis less efficient than the pure binary, in the sense that it requires more bits. * For example, the decimal number 14 can be represented as 1110 in pure binary but as 0001 0100 in 8421 BCD code. '* Another disadvantage of the BCD code is that, arithmetic operations are more complex than they are in pure binary. ‘+ There are six illegal combinations 1010, 1011, 1100, 1101, 1110 and 1111 in this code. BCD Addition + If there is no carry and the sum term is not an illegal code, no correction is needed * if there is a carry out of one group to the next group, or if the sum term is illegal code, then 6 (0110) is added to the sum term of that group and the resulting carry is added to the next group. = Example:- (1) 25413 Ans, 25 0010 0101 (25in8co) 3 — +0001 0011 sinc) 38 0011 1000 (No carry, no illegal code. So, this is the correct sum) Krunal D. Vyas, CE Department | 3130704 — Digital Fundamentals, 7Darshan 1 - Logic Function Realization with MSI ome enaere sot Circuits (2) 679.6 +536.8 Ans. 679.6 0110 0111 1001. 0110 (679.6 in BCD) +5368 "+0101 0011 0110. 1000 (536.8 in BCD) 1216.4 1011 1010 1111. 1110 (Allare illegal codes) +0110 +0110 +0110 +0110 (Add 0110 to each) 0001 0010 0001 0110. 0100 (Corrected sum = 1216.4) BCD Subtraction '* If there is no borrow from the next higher group then no correction is required. ‘+ Ifthere is a borrow from the next group, then 610 (0110) is subtracted from the difference term of this group. + Example:- (a) 38-15 Ans. 38 1000 (38in BCD) =, 0.101 (15 in BCD) (0011 (No borrow. So, thisis the correct difference.) (2) 206.7 147.8 Ans. 206.7», 0010 0000 0110. 0111 (206.7inBCO) 143 001 0100 0111. 1000 (147.8in BCD) 58.9 0000 1011 1110. 1111 (Borrows are present, subtract 0110) -0110 -0110 .-0110 0101 1000 . 1001 (Corrected difference = 58.9) Excess-3 Code ‘+The Excess-3 code, also called XS-3, is a non-weighted BCD code. * This code derives its name from the fact that each binary code word is the corresponding 8421 code word plus 0011(3). ‘+ Itis sequential code and, therefore, can be used for arithmetic operations. ‘+ Itis a self-complementing code. ‘©The XS-3 code has six invalid states 0000, 0001, 0010, 1101, 1110 and 1111. XS-3 Addition If there is no carry out from the addition of any of the 4-bit groups, subtract 0011 from the sum term of those groups. ‘* Ifthere is a carry out, add 0011 to the sum term of those groups. © Example:- (a) 247.6+359.4 Ans. 247.6 0101 0111 1010. 1001 (247.6inxs-3) #3594'——"s0110 1000 1100, 0113 (359.4 in XS 3) 607.0, 1100 0000 0111. 0000 (Add 0011 to 0000, 0111, 0000 20011 +0011 +0011 +0011 and subtract 0011 from 1100) 1001 0011 1010 0011 (Corrected sum in XS-3 = 607.0) XS-3 Subtraction © If there is no borrow from the next 4-bit group, add 0011 to the difference term of such groups. * If there is a borrow, subtract 0011 from the difference term. Krunal D. Vyas, CE Department | 3130704 — Digital Fundamentals, 18Dp Darshan 1 - Logic Function Realization with MSI ome enaere sot Circuits + Example:- (1) 267-175 Ans. 267 5 0101 1001 1010 (267 inxs-3) 175 0100 1010 1000 (175in xS-3) 092 0000 1111 0010 (Subtract 0011 from 1111 and #0011 -0011+0011 add 0011 to 0000 & 0010) 0011 1100 0101 (Corrected difference in XS-3 = 92) Gray Code ‘+The gray code is a non-weighted code. ‘+ Itis.a cyclic code because successive code words in this code differ in one bit position only, ie. it isa unit distance code. © Itis also a reflective code. ‘+ Then least significant bits for 2° through 2-1 are the mirror images of those for 0 through 2"-1. ‘+ An N-bit gray code can be obtained by reflecting an N-1 bit code about an axis at the end of the code, and putting the MSB of O above the axis and the MSB of 1 below the axis. '* One reason for the popularity of the gray code is its ease of conversion to and from binary. ‘+ Reflection of gray code is shown in table. Gray Code Decimal 4-bit binary Lit Zoit B-bit ‘abit 0 00 (000 (0000 0 ‘0000 1 o1 001, 0001 1 0001 cry ont, 0011 2 0010 10 10 0010 3 0011 110 o110 4 0100 at o111 5 0101 101 0101, 6 0110 100 0100 7 111 1100 8 1000 1101 9 1001 qa 10 1010 1110 u 1011 1010 2 1100 1011 B 1101 1001 “4 1110 1000 15 qt Binary to Gray Conversion + fan n-bit binary number is represented by By By... Bs and its gray code equivalent G, Grs .. Gs, where B, and G, are the MSBs, then the gray code bits are obtained from the binary code as follows: Bs B Bot 2= Bot @ Bez ‘+ The conversion procedure is as follows: 1. Record the MSB of the binary as the MSB of the gray code. 2. Perform X-ORing between the MSB of the binary and the next bit in binary. This answer is the next bit of the gray code. Krunal D. Vyas, CE Department | 3130704 ~ Digital Fundamentals 19Darshan 1 - Logic Function Realization with MSI ome enaere sot Circuits 3. Perform X-ORing between 2” bit of the binary and 3" bit of the binary, the 3° bit with the 4" bit, and so on. 4, Record the successive answer bits as the successive bits of the gray code until all the bits of the binary number are exhausted. ‘© Example:- Convert the binary 1001 to Gray code. Ans: 1-@> 0-@> 0-@> 1 1] td 1 1 0 1 Gray to Binary Conversion ‘© fan n-bit gray number is represented by Gy Gps .. Gy and its binary code equivalent By By». Buy where G, and B, are the MSBs, then the binary bits are obtained from the gray bits as follows: B= Ga Bra=Br@®@Gei | Br2= Bri ® Gor Bi=B2@ G ‘+The conversion procedure is as follows: 1. The MSB of the binary number is the same as the MSB of the gray code number. 2. Perform X-ORing between the MSB of the binary and next significant bit of gray code. This, answer is the next bit of binary. 3. Perform X-ORing between the 2” bit of the binary and 3% bit of the gray code, the 3° bit of the binary with the 4" bit of gray code, and so on. 4, Record the successive answers as the successive bits of the binary until all the bits of the gray code are exhausted. © Example:- Convert the gray code 1101 to binary. Ans. 1 1 0 1 Lol el | Py, 1 0 0 2 Error Detecting Code * When binary data is transmitted and processed, it is susceptible to noise that can alter or distort its contents. ‘+ The 1s may get changed to 0s and 0s to 1s. '* Because digital systems must be accurate to the digit, errors can pose a serious problem, ‘* Several schemes have been devised to detect the occurrence of a single-bit error in a binary word, so that whenever such an error occurs the concerned binary word can be corrected and retransmitted, Parity ‘+ The simplest technique for detecting errors is that of adding an extra bit, known as the parity bit, to each word being transmitted. ‘+ There are two types of parity ~ odd parity and even parity. ‘+ For odd parity, the parity bit is set to a0 or a 1 at the transmitter such that the total number of 2 bits in the word including the parity bit is an odd number. + For even parity, the parity bit is set to a0 or a 1 at the transmitter such that the total number of 1 bits in the word including the parity bit is an even number. Krunal D. Vyas, CE Department | 3130708 — Digital Fundamentals, 201 - Logic Function Realization with MSI D ‘arshan Circuits When the digital data is received, a parity checking circuit generates an error signal if the total number of 1s is even in an odd-parity system or odd in an even-parity system. This parity check can always detect a single-bit error but can not detect two or more errors within the same word, In any practical system, there is always a finite probability of the occurrence of single error. (Odd parity is used more often than even parity because even parity does not detect the situation where all 0s are created by a short-circuit or some other fault condition. Example:-If Data is 1011010, then even parity must be 0 and odd parity must be 1. Check Sums Simple parity cannot detect two errors within the same word. One way of overcoming this difficulty is to use a sort of two-dimensional parity. As each word is transmitted, itis added to the sum of the previously transmitted words, and the sum retained at the transmitter end. At the end of transmission, the sum (called the check sum) up to that time is sent to the receiver. The receiver can check its sum with the transmitted sum, Ifthe two sums are the same, then no errors were detected at the receiver end. If there is an error, the receiving location can ask for retransmission of the entire data. This is the type of transmission used in teleprocessing systems. Block Parity When several binary words are transmitted or stored in succession, the resulting collection of bits, can be regarded as a block of data, having rows and columns. Parity bits can then be assigned to both rows and columns. This scheme makes it possible to correct any single error occurring in a data word and to detect any two errors in a word. This technique also called word parity, is widely used for data stored on magnetic tapes. For example, six 8-bit words in succession can be formed into a 6x8 block for transmission. Parity bits are added so that odd parity is maintained both row-wise and column-wise and the block is transmitted as a 7x9 block as shown in Figure 1. At the receiving end, parity is checked both row-wise and column-wise and suppose errors are detected as shown in Figure 2. These single-bit errors detected can be corrected by complementing the error bit, In Figure 2, parity errors in the 3" row and 5" column mean that the 5* bit in 3" row is in error. It can be corrected by complementing it Two errors as shown in Figure 3 can only be detected but not corrected, In Figure 3, parity errors are observed in both columns 2 and 4. Itindicated that in one row there two errors. Krunal D. Vyas, CE Department | 3130704 — Digital Fundamentals 21Darshan 1 - Logic Function Realization with MSI ome enaere sot Circuits 01011011 10010101 01011011 10010101 0 01011011 1 10010101 01101110 01100110 | 05 eriqgs 01101110 11010011 11010011 |0 row 10000011 10001101 10001101 | 1 10001101 01110111 01110111 1 01110111 orroore ofePoorse — 01110110 01110110 0 01110110 en | | I Parity Column Party efrorin 5® Column Party errors in 2° & 4 Column Figure 1 Figure 2 Figure3 Error Correcting Code © Accode is said to be an error-correcting code, if the correct code word can always be deducted from an erroneous word. + Fora code to be a single-bit error-correcting code, the minimum distance of that code must be three. © Themi differ. ‘+ Acode with minimum distance of three can not only correct single-bit errors, but also detect (but cannot correct) two-bit errors. ‘+The key to error correction is that it must be possible to detect and locate erroneous digits. ‘+ If the location of an error correction is determined, then by complementing the erroneous digit, the message can be corrected. * Tit hamming code is one type of error-correcting code. \um distance of a code is the smallest number of bits by which any two code words must The 7-bit hamming code ‘+ Totransmit four data bits, three parity bits located at positions 2°, 2', and 2? from left are added to make a 7-bit code word which is then transmitted. ‘+The word format would be as shown below: Pi P2 Ds Ps Ds De Dy Where the 0 bits are the data bits and the P bits are the parity bits. ‘© Pristobe set a 0 or 1 so that it establishes even parity bits 1, 3, 5, and 7 (Ie. Px Ds Ds D>) ‘+ Pris tobe set a 0 or 1 s0 that it establishes even parity bits 2, 3, 6, and 7 (i. P2 Ds Ds D) ‘+ Psis tobe set a 0 or 1 so that it establishes even parity bits 4, 5, 6, and 7 (i.e. Pa Ds Ds D2) + Example:- (1) Encode data bits 1101 into the 7-bit even-parity hamming code. ‘Ans: The bit pattern is P: Pz Ds Pa Ds Ds Dy =P: Pr 1Ps101. Bits 1, 3, 5, 7 (Le. P: 11 1) must have even parity. So, Pi must be a 1 Bits 2, 3, 6,7 (ie, P» 10 1) must have even parity. So, Pz must be a 0. Bits 4, 5, 6,7 (ie, Ps 10 1) must have even parity. So, Pa must be a 0. Therefore, the final code is 1010101. Krunal D. Vyas, CE Department | 3130704 — Digital Fundamentals 22Darshan 1 - Logic Function Realization with MSI ome enaere sot Circuits (2) The message 1001001 in the 7-bit hamming code is transmitted through a noisy channel, Decode the message assuming that at most a single error occurred in each code word. ‘Ans. Message is 1001001 Bits 1, 3, 5, 7 (1001) — no error —#C; = 0 Bits 2, 3, 6, 7 (0001) —» error 9 —wC,=1. Bits 4, 5, 6, 7 (1001) —» no error —*C; = 0 The error word is CsC2C: = 010 = 230. So, complement the 2” bit from left. ‘Therefore, the correct code is 1101001. Digital IC Specifications 1. Threshold voltage:- * Itis defined as that voltage at the input of a gate which causes a change in the state of the ‘output from one logic level to the other. 2. Propagation delay:- ‘= Apulse through a gate takes a certain amount of time to propagate from input to output. This interval of time is known as the propagation delay of gate. tis the average transition delay time tya, expressed by tye = eum 2 where, tau is the signal delay time when the output goes from a logic 0 to a logic 1 state and tow isthe signal delay time when the output goes from a logic 1 to logic 0 state. 3. Power dissipation:- * The power dissipation, Po, of a logic gate is the power required by the gate to operate with 50% duty cycle at a specified frequency and is expressed in milliwatts, leet 2 Po = Vec x leelave)/n, where lec(avg) = 4. Far-in:- The fan-in of a logic gate is defined as the number of inputs that the gate is designed to handle. 5. Fan-out:- * The fan-out (also called the loading factor) of a logic gate is defined as the maximum number of standard loads that the output of the gate can drive without impairing its normal operation 6. Voltage parameter:~ © Vidmin): tis the minimum voltage level required at the input of a gate for that input to be treated as a logic 1. Any voltage below this level will not be accepted as a logic 1 input by the logic circuit. '* Vou(rmin): itis the minimum voltage level required at the output of a gate for that output to be treated as a logic 1. Any voltage below this level will not be accepted as a logic 1 output. © Va(max): tis the maximum voltage level that can be treated as logic 0 at the input of the gate. Any voltage above this level will not be treated as a logic 0 input by the logic circuit. Krunal D. Vyas, CE Department | 3130704 — Digital Fundamentals 23Darshan 1 - Logic Function Realization with MSI ome enaere sot Circuits © Vn(min): tt is the maximum voltage level that can be treated as logicO at the output of the gate. Any voltage above this level will not be treated as a logic 0 output. 7 Current parameter:- ‘* Ing The current that flows into an input when a specified HIGH level voltage is applied to that input. © in: The current that flows into an input when a specified LOW level voltage is applied to that input. © Jou: The current that flows from an output in a logic 1 state under specified load conditions. © Jo The current that flows from an output in a logic 0 state under specified load conditions. 8. Noise margi * When the digital circuits operate in noisy environment the gates may malfunction if the noise is beyond certain limits. * The noise immunity of a logic circuit refers to the circuit's ability to tolerate noise voltages at its inputs. * Aquantitative measure of noise immunity is called noise margin. 9. Operating temperature:- The IC gates and other circuits are temperature sensitive being semiconductor devices. + However, they are designed to operate satisfactorily over a specified range of temperature. © The range specified for commercial applications is 0 to 70°C, for industrial it is 0 to 85°C, and for military applications itis -55°C to 125°C. 10. Speed power product:- * Acommon means for measuring and comparing the overall performance of an IC family is the speed power product, which is obtained by multiplying the gate propagation delay by the gate power dissipation. * Alow value of speed power product is desirable. The smaller the product, the better the overall performance. © Itis figure of merit of an IC family. TTL v/s CMOS v/s ECL Characteristic ™ cmos ECL Power Input Moderate Low Moderate-High Frequency limit High Moderate Very high Circuit density ‘Moderate-high High-very high Moderate Circuit types per family | High High Moderate Krunal D. Vyas, CE Department | 3130704 — Digital Fundamentals, 24Darshan 1 - Logic Function Realization with MSI ome enaere sot Circuits Logic Family | Propagation | Power Noise Fan-in Fan-out Cost delay time | dissipation | Margin (V) (ns) per gate (mw) ™m 9 10 oa 3 10 low ‘MOS <50 o.01 5 10 50 Low ECL 1 50 0.25 5. 10 High Transistor-Transistor Logic (TTL) ‘+ The TTL or T'L family is so named because of its dependence on transistors alone to perform basic logic operations ‘+ Itis the most popular logic family. Itis also the most widely used bipolar digital IC family ‘+The TTL uses transistors operating in saturated mode. It is the fastest of the saturated logic families. ‘+ The basic TTL logic circuit is the NAND gate. Good Speed, low manufacturing cost, wide range of Circuits, and the availability in SSI and MSI are its merits, ‘* Tight Vcc tolerance, relatively high-power consumption, moderate packing density, generation of noise spikes and susceptibility to power transients are its demerits, ‘+The TTL logic family consists of several subfamilies or series such as: ‘+ Standard TTL, High Speed TTL, Low power TTL, Schottky TTL, Low power Schottky TTL, Advanced Schottky TTL, Advanced low power Schottky TTL and F(fast)TTL. ‘© The differences between the various TTL subfamilies are in their electrical characteristics such as delay time, power dissipation, switching speed, fan-out, fan-in, noise margin, etc. For Standard TIL, propagation delay time = 9 ns, power dissipation per gate = 10 mW. now margin = 0.4 mV, fan-in = 8, and fan-out = 10, ‘© For standard TTL, 0 V to 0.8 Vis treated as a logic O and 2 V to S Vis treated as logic 1. ‘© Signals in 0.8 V to 2 V range should not be applied as input as the corresponding response will be independent. * Ifa terminal is left open in TIL, it is equivalent to connecting it to HIGH, Le. +5 V. * But such a practice is not recommended, since the floating TTL is extremely susceptible to picking up noise signals that can adversely affect the operation of the device. Schottky TTL '* The standard TTL, low power TTL, and high speed TTL series operate using saturated switching '* When a transistor is saturated, excess charge carriers will be stored in the base region and they ‘must be removed before the transistor can be turned off. ‘+ So, owing to storage time delay, the speed is reduced. ‘+The Schottky TTL 748 series reduces this storage time delay by not allowing the transistor to go into full saturation. ‘+ This is accomplished by using a Schottky barrier diode (SBD) between the base and the collector of each transistor. ‘© Virtually, all modern TTL devices incorporate this so-called Schottky clamp. * The SBD has a forward voltage of only 0.25 V. The circuits in the 745 series also use smaller resistance values to improve the speed of operation. ‘+ The speed of the 745 series is twice that of the 74H series, Krunal D. Vyas, CE Department | 3130704 — Digital Fundamentals, 25QD Darshan 1 - Logic Function Realization with MSI ome enaere sot Circuits * Schottky TTL has more than three times the switching speed of standard TTL, at the expense of approximately doubling the power consumption. Tri-State TTL + The third TTL configuration is the tri-state configuration. ‘+ It utilizes the advantage of high speed of operation of the totem-pole configuration and wire ANDing of the open-collector configuration. ‘+ [tis called the tri-state TTL, because it allows three possible output states: HIGH, LOW, and HIGH impedance (Hi-Z). ‘+ Inthe Hi-Z state, both the transistors in the totem-pole arrangement are turned off, so that the ‘output terminalis a HIGH impedance to ground or VCC. ‘© In fact, the output is an open or floating terminal, that is, neither a LOW nor a HIGH ‘+ Inpractice, the output terminal is not an exact open circuit, but has a resistance of several MQ or ‘more relative to ground and Vcc. Krunal D. Vyas, CE Department | 3130704 — Digital Fundamentals, 26Darshan 2 - Combinational digital circuits Standard representation for logic functions 1, Sum-of-products (SOP) form: + This form is also called the Disjunctive Normal Form (NF) * Forexample, /(4,B,C) = AB+ BC 2. Product-of-sums (POS) form: * This form is also called the Conjunctive Normal Form (CNF). * The function of above equation may also be written in the form shown in equation below. * By using multiplying it out and using the consensus theorem, we can see that it is the same as f(A,B,C) = (A+ BY(B +0) 3. ‘Standard sum-of-products form: * This form is also called Disjunctive Canonical Form (DCF), * Itis also called the Expanded Sum of Products Form or Canonical Sum-of-Products Form. + Inthis form, the function is the sum of a number of product terms where each product term contains all the variables of the function either in complemented or uncomplemented form. * This can be derived from the truth table by finding the sum of all the terms that correspond to those combinations (rows) for which ‘f’ assumes the value 1. + Itcan also be obtained from the SOP form algebraically as shown below. {(A,B,C) = AB + BC = AB(C+0)+(A+AB ABC + ABC + ABC + ABC * A product term which contains all the variables of the function either in complemented or uncomplemented form is called a minterm + Aminterm assumes the value 1 only for one combination of the variables. An n variable function can have in all 2° minterms © The sum of the minterms whose value is equal to 1 is the standard sum of products form of the function, * The minterms are often denoted as mo, m:, ma, .., where the suffixes are the decimal codes of the combinations * For a 3-variable function mo = ABC, m: ABC, mz = ABC. * Another way of representing the function in canonical SOP form is by showing the sum of minterms for which the function equals 1. # Thus f(A, B,C) = mit mz+ms+ms * Yet another way of representing the function in DCF is by listing the decimal codes of the minterms for which f= 1. © Thus f(4,B,C) = Ym(1,2,3,5) 1C, m2 = ABC, ma = ABC, ms = ABC, ms = ABC, me = 4. Standard product-of sums form: * This form is also called Conjunctive Canonical Form (CCF). * Iti also called Expanded Product-of-Sums Form or Canonical Product-of-Sums Form. *Thisis derived by considering the combinations for which f= 0. Each term isa sum of al the variables, * variable appears in uncomplemented form ifit has a value of 0 in the combination and appears in ‘complemented form ifit has a value of | in the combination. F(A,B,C) = (A+ B)(B +0) = (44+ 8 + 00) (AA +B +0) Krunal D. Vyas, CE Department | 3130704 — Digital Fundamentals 27Dp Darshan 2 - Combinational digital circuits AFB +OA+R+ OU+B+O)A+B+C) ‘+ Assum term which contains each of the n variables in either complemented or uncomplemented form is called a maxterm. ‘+A maxterm assumes the value 0 only for one combination of the variables. For all other combinations it will be 1 * There will be at the most 2” maxterms. The product of maxterms corresponding to the rows for which f=, is the standard or canonical product of sums form of the function. ‘+ Maxterms are often represented as Mo, Mi, Ma, .., where the suffixes denote their decimal code. ‘+ Thus, the CCF of function f may be written as f(A, B, C) = Mo: Ma: Me M, * Expression can also be expressed as f(4,8,C) = Ty(0,4,6,7) ‘* Where TT represents the product of all maxterms whose decimal code is given within the parenthesis. Karnaugh Map (K-Map) + The Karnaugh map (K-map) method is a systematic method of simplifying the Boolean expression. ‘The K-map is a chart or a graph, composed of an arrangement of adjacent cells, each representing a particular combination of variables in sum or product form. + The output values placed in each cell are derived from the minterms of a Boolean function. + Aiminterm is a product term that contains all of the function’s variables exactly once, either complemented or not complemented. Two-variable K-Map ‘+ The two variable expression can have 2?= 4 possible combinations of the input variables A and 8. ‘+ Each of these combinations, A’B’, A’B, AB’, and AB (in SOP form) is called minterm. ‘+ These possible combinations can be represented in table and by the map as follows: nl ololp Three-variable K-Map * A function in three variable (A, B, C) expressed in the standard SOP form can have eight possible combinations: A’B’C’, A’B‘C, A’BC’, A’BC, ABC’, AB'C, ABC’ and ABC. * Each one of these combinations designated by mo, m., mz, Ms, Ms, ms, Ms, and m, respectively, is called minterm. * In the standard POS form, the eight possible combinations are: A*B+C, A¥B+C’, A*B'+C, AHB'+C’, A'+B+C, AB4C, A'4B'4C, and A’+B'*C’. ‘+ Each one of these combinations designated by Mc, Mi, Mz, Ma, Ma, Ms, Ms, and My, respectively, is called maxterm. Krunal D. Vyas, CE Department | 3130704 Digital Fundamentals. 28DP Darshan 2 - Combinational digital circuits A B c Minterm SAB 0 0 0 | m=a'B'C’ CX 00 01 1110 9. o 1 | m=asic t 0 2] 6) 4 0 1 0 | m=asc’ o 1 4 m= ABC 4 a 3 a 5 1 0 0 | m= AC t 1 ° 1 | m=aee | 1 1 0 | m= ABC" Minterm Number 1 1 1 | m,=ABC Four-variable K-Map * The four variables A, 8, C and D have sixteen possible combinations that can be represented by the mapas follows A\B/C|D Minterm A/|B/C|D Minterm 0 | 0] 0| 0 | m=AB'C'D’ 1|0]0] 0] m=ascD 0 /}0} 0] 1 | m=~AB'C’D 1|0/] 0) 1] m=AB'C’D o|}0/1]0 | m=as'co’ 1 | 0] 1] 0 | m,=as'co’ o/0/}1/ 1) m,=aecD 1/0/21] 1] m,=as'cD 0} 1) 0] 0 | m,=A‘BC’D’ 1 | 1/0 | 0 | m)=ABC'D’ O/}1|0)} 1) m =A‘BC’D 1 1] 0} 1 | my3=ABC’D o}a]1]0 | m=asco' 12 |a]1| 0 | m4=ABcD’ o}1[1/1/ m,=Asco 1/1]1] 1] my,=ascp AB tp. 0 Ol 11 10 oO 4 12 8 00 1 5 13) o1 “| 3 7 uu 15) 11) 2 6 14 10) 10 Krunal D. Vyas, CE Department | 3130704 ~ Digital Fundamentals 29© Darshan Semen ern ver 2 - Combinational digital circuits Reduction using K-Map Squares which are physically adjacent to each other or which can be made adjacent by wrapping. ‘the map around from left to right or top to bottom can be combined to form bigger squares. ‘The bigger squares (2 squares, 4 squares, 8 squares, etc.) must form either a geometric square or rectangle. For the minterms or maxterms to be combinable into bigger squares, it is necessary but not sufficient that their binary designations differ by a power of 2. Example - 1 Reduce f(A, B, C) = A’B'C + A'BC + AB'C + ABC SAB Cu 0001 1110 o] 2] 6) 4 0 fh" Answer: f= C Example - 2 Reduce f(A, 8, C, D) = ABC’D + ABCD + A’BC'D + A’BCD co. 00 1 110 00 on coy 10 Answer: f= BD Example - 3 Reduce f(A, 8, C, 0) = Em(0,2,8, 10, 13) “8 00 1 Oo on 10 ya] ,8 00 1 al 7 a 3 ul 3) 7) 3) a] 6] 18\—70) 10] 1} 1 Krunal D. Vyas, CE Department | 3130704 ~ Digital Fundamentals 30© Darshan Semen ern ver 2 - Combinational digital circuits ‘Answer: f= B'D’ + ABC'D Example ~ 4 Reduce f(A, B, C, 0) = [y(0,1,4,5, 10, 11, 14, 15) '* In POS form, we have to put “0” in the given number boxes in K-Map. ‘+ Make group of Os same as we make group of 1s in SOP form, ‘+ For common “1” write complemented form and for common “0” write uncomplemented form of variable, e.g. 1-A’ and0-A, SAB cp.00 of 10 wl(Grel) I * alle) of > nl 3)? otal wl?) ol oP Answer: f = (A+C) (A’+C’) K-Map with don’t care condition ‘+ Suppose we are given a problem of implementing a circuit to generate a logical 1 when a 2, 7, or 15 appears on a four-variable input. '* Alogical 0 should be generated when 0, 1, 4, 5, 6,9, 10, 13 or 14 appears. ‘+The input conditions for the numbers 3, 8, 11 and 12 never occur in the system. This means we don’t care whether inputs generate logical 1 or logical 0, ‘+ Don’t care combinations are denoted by “x'in K-Map which can be used for the making groups. ‘+ The above example can be represented as Example - 1 Reduce f(A, B, C, 0) = Em(2,7,15) + d(3,8, 11,12) \ AB 0 ol 10 o] 4] 00 x7) x 7] 3) 3 on “9 > u(x]f17 6] a4] 10] 10 Answer: f=CD+A’B'C Krunal D. Vyas, CE Department | 3130704 — Digital Fundamentals 31DP Darshan Semen ern ver 2 - Combinational digital circuits Example - 2 Reduce f(W, X, ¥, Z) = ZmC1,3, 7,11, 15) + 400, 2,5) o1 11 10 4a) 12 8) a] ofall} x *| uiafla Tata] 10 Lx Answer: f = W’ Variable-Entered Map (VEM) Variable-entered map can be used to plot an n-variable problem on n- 1 variable map. Possible to reduce the map dimension by two or three in some cases. Advantage of using VEM occurs in design problems involving multiplexers, For example, Map-entered variable for 3 variable function Consider the function X = A'B'C’ + ABC! + AB'C' + ABC Considering value of X to be function of map location and the variable C and plotting 2 variable K- Map. of ¢ co Example - 1 Reduce ABCD + A’BC’D + AB‘CD’ + ABC'D +A’B'C'D BICD + ABCD + AB'CD’ + ABC'D + A'B'C’D 5 2 5 6 0 SAB eo ot 1 0 o | (0 | [o]| 0} 1 D+D) Answer: f= A’C’D + BCD + AB’C Krunal D. Vyas, CE Department | 3130704 — Digital Fundamentals 32Dp Darshan 2 - Combinational digital circuits A’B'C'D + A’BC’D’ + A’BC’D + AB'C’D’ + AB'CD’ + AB'CD + ABCD’ using VEM method. 'B'C'D + A'BC'D’ + A’BC'D + AB'C’D’ + AB'CD’ + AB'CD + ABCD’ 0 2 2 4 5 5 7 Example - 2 Reduce \ AB X00 O11 10 o|(0 Bho] OH 1 ¢D? [D4D) ‘Answer: f= A’C’D + ABC’ + ACD! + ABD’ + ABIC WBICDE+A’B'C’DE + A’BCDE’ + A’BCD’E + AB'C'D'E’ + ABC'D’E + AB'C’D + A’BCDE’ Example -3 Reduce 1 F 10 E Answer: f= B’C'E + AB'C’ + A’BCD' + A’BCE’ Quine McCluskey Method (Tabulation Method) Procedure for minimization using tabulation method 1. List all the minterms. 2. Arrange all minterms in groups of the same number of 1 in their binary representation in column 1 Start with the least number of 1s group and continue with groups of increasing number of 1s. 3. Compare each term of the lowest index group with every term in the succeeding group. Whenever possible, combine the two terms being compared by means of the combining theorem, Two terms from adjacent groups are combinable, if their binary representations differ by just a single digit in the same position; the combined terms consist of the original fixed representation with the differing one replaced by a dash (-). Place a check mark (v) next to every term, which has been combined With at least one term and write the combined terms in column 2. Repeat this by comparing each term in a group of index i with every term in the group of index i + 1, until all possible applications of the combining theorem have been exhausted. Krunal D. Vyas, CE Department | 3130704 — Digital Fundamentals 33& Darshan Semen ern ver 2 - Combinational digital circuits 4. Compare the terms generated in step 3 in the same fashion; combine two terms which differ by only a single 1 and whose dashes are in the same position to generate anew term. Two terms with dashes in different positions cannot be combined. Write the new terms in column 3 and put a check ‘mark next to each term which has been combined in column 2. Continue the process with terms in columns 3, 4 etc. until no further combinations are possible, The remaining unchecked terms constitute the set of prime implicants of the expression. 5. List all the prime implicants and draw the prime implicant chart. (The don't cares if any should not appear in the prime implicant chart) 6. Obtain the essential prime implicants and write the minimal expression. Example - 1 Simplify f(A, 8, C, D) = En (1,2,3, 5, 6,7, 8,9, 12, 13, 15) using tabulation method. Step List all minterm Step:-2 Arrange all minterms in groups ‘of same number of 1s Minterms Column-t 1 Binary 2 tndex | Minterms | Designation 3 laden i oo01v 5 t 2 6 8 7 3 8 Index 3 9 3 6 2 8 13 12 15 index 7 3 13 ‘Step:-3 Compare each term of the lowest index group with Index 15 every term in the succeeding group till no change. & Column-2 Step:-4 Compare the terms generated in Pairs [ABCD step 3 in the same fashion until no 13 00-14 further combinations are possible. 15 o-o1v 19 -001¥ Column-3 23 oo1-v Quads [ABCD 26 0-104 1,3,5,7 o--iT 39 100-4 15,93 --018 8,12 1-00¥ 2,3,6,7 0-1-R o-11¥ 8,9,12,13 1-0-a o1-1v 5,7,13,15 =1-iP -101¥ o1i-¥ 1-01¥ 110-¥ 7,15 -11i¥ 13,15 li-1v, Krunal D. Vyas, CE Department | 3130704 — Digital Fundamentals 34QD Darshan 2 - Combinational digital circuits Step:-5 List all prime implicants and draw prime implicants chart, Prime implicants: P(BD), Q(AC’), R(A’C), S(C’D) , T(A’D) Minterms | 1 [2” |3v |5v|6v|7¥ [av [Sv | aay | i3v | i5v Tao) |X xx x | s(c’D) x x |x x RIA’C) ¥ yx x | x Qac’) ¥ x x xX P(BD) ¥ x x x Step-6 Obtain essential prime implicants and minimal expression. Essential Prime Implicants: P(BD), Q(AC’), R(A’C) Minimal Expression: P+Q+R+S = BD + A’C + AC’ +C’D. r ~ ~ 1 PrQuReT=BD+a'c+ac+ary — _AsMminterm 11s covered by Sand T. | Example - 2 Simplify f(A, B, C, 0) = Dm(0, 1,3, 7, 8,9, 11, 15) using tabulation method. Step:-1 List all minterm Step:-2 Arrange all minterms in groups. of same number of 1s Minterms | Binary Designation Column-1 0 0001 Binary 1 0010 Index | Minterms | pesignation 3 0011 Index 0 oocov 7 0111 0 8 1000 Index 1 9 1001 al 8 a 1011 Index 3 15 aai1 2 9 Index 7 3 u Step:-3 Compare each term of the lowest index group with Index | 4 every term in the succeeding group till no change. 4 ‘Column-2 ‘Stepi-4 Compare the terms generated in Pairs ABCD step 3 in the same fashion until no 01 000-7 further combinations are possible. 08 -000¥ 13 00-14 ‘Column-3 19 -001¥ ‘Quads ABCD 89 100-v 0189 =00-R 3,7 0-114 13,911 -0-19 311 -o11y 3,7,11,15 =-11P gat 10-14 7,15 -111¥ 11,15 a-11¥ Krunal D. Vyas, CE Department | 3130704 — Digital Fundamentals 35DH Darshan 2 - Combinational digital circuits ‘Step:-5 List all prime implicants and draw prime implicants chart. Prime implicants: P(CD), Q(B’D), R(B’C’) Minterms | ov [ iv | 3v | 7v | 8v | 9v | aay | 15v P(co x Dy x | x Q(B'D) x x x x RBC ‘Step:-6 Obtain essential prime implicants and minimal expression Essential Prime Implicants: P(CD), R(B'C’) Minimal Expression: P+R = CD +B'C’ Realization using universal gates 1. Draw the circuit in AO! logic. 2. If NAND hardware is chosen, add a circle at the output of each AND gate and at the inputs to all the OR gates. 3. If NOR hardware is chosen, add a circle at the output of each OR gate and at the inputs to all the AND. gates. 4. Add or subtract an inverter on each line that received a circle in steps 2 or 3 so that the polarity of signals on those lines remains unchanged from that of the original diagram. 5. Replace bubbled OR by NAND and bubbled AND by NOR. 6. Eliminate double inversions. Example - 1 Implement the following AO! logic using NAND, ‘+ Puta circle at the output of each AND gate and at the inputs to all OR gates i o> rl ‘+ Add an inverter to each of the lines that received only one circle at input so that polarity remains unchanged, Krunal D. Vyas, CE Department | 3130704 — Digital Fundamentals 36© Darshan 2 - Combinational digital circuits PLO Replace bubbled OR gates and NOT gates by NAND gates. Multiplexer ‘A multiplexer (MUX) is a device that allows digital information from several sources to be routed conto a single line for transmission over that line to a common destination. Consider an integer ‘m’, which is constrained by the following relation: m-=2", where m and n are both integers. Am+to-1 Multiplexer has = miinputs: toy hy la, lea) + One Output: ¥ +n Control inputs: So, $1, $2, Sina) + One (or more) Enable input(s) Pr >- such that Y may be equal to one of the inputs, depending upon the control inputs. The block diagram of 4 x 1 multiplexer is as follows. 4— h 4axd \, Mux 45— ane TTI SS. y output Krunal D. Vyas, CE Department | 3130704 ~ Digital Fundamentals 37