Department of Electronics and Communication Engineering

DIGITAL CIRCUIT DESIGN LABORATORY

MANUAL

DEPARTMENT OF ELECTRONICS AND COMMUNICATION ENGINEERING

GUDLAVALLERU ENGINEERING COLLEGE

(An Autonomous Institute with Permanent Affiliation to JNTUK, Kakinada)
SESHADRI RAO KNOWLEDGE VILLAGE::GUDLAVALLERU

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Vision of the Institute

To be a leading institution of engineering education and research, preparing students for
leadership in their fields in a caring and challenging learning environment.

Mission of the Institute

 To produce quality engineers by providing state-of-the-art engineering education.

 To attract and retain knowledgeable, creative, motivated and highly skilled individuals
whose leadership and contributions uphold the college tenets of education, creativity,
research and responsible public service.

 To develop faculty and resources to impart and disseminate knowledge and information
to students and also to society that will enhance educational level, which in turn, will
contribute to social and economic betterment of society.

 To provide an environment that values and encourages knowledge acquisition and

academic freedom, making this a preferred institution for knowledge seekers.

 To provide quality assurance.

 To partner and collaborate with industry, government, and R and D institutes to develop
new knowledge and sustainable technologies and serve as an engine for facilitating the
nation’s economic development.

 To impart personality development skills to students that will help them to succeed and
lead.

 To instill in students the attitude, values and vision that will prepare them to lead lives of
personal integrity and civic responsibility.

 To promote a campus environment that welcomes and makes students of all races,
cultures and civilizations feel at home.

 Putting students face to face with industrial, governmental and societal challenges.

Vision of the Department

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To be a leading centre of education and research in Electronics and Communication Engineering,

making the students adaptable to changing technological and societal needs in a holistic learning
environment.

Mission of the Department

 To produce knowledgeable and technologically competent engineers for providing
services to the society.
 To have a collaboration with leading academic, industrial and research organizations for
promoting research activities among faculty and students.
 To create an integrated learning environment for sustained growth in electronics and
communication engineering and related areas.

Programme Educational Objectives (PEOs):

Graduates of the Electronics and Communication Engineering program will
1. demonstrate a progression in technical competence and leadership in the practice/field of
engineering with professional ethics.
2. continue to learn and adapt to evolving technologies for catering to the needs of the
society.
Programme Outcomes (POs):
The graduates of electronics and communication engineering program will be able to
a) apply knowledge of mathematics, science, and engineering for solving intricate engineering
problems.
b) identify, formulate and analyze multifaceted engineering problems.
c) design a system, component, or process to meet desired needs within realistic constraints
such as economic, environmental, social, political, ethical, health and safety,
manufacturability, and sustainability.
d) design and conduct experiments based on complex engineering problems, as well as to
analyze and interpret data.
e) use the techniques, skills, and modern engineering tools necessary for engineering practice.
f) understand the impact of engineering solutions in a global, economic and societal context.
g) design and develop eco-friendly systems, making optimal utilization of available natural
resources.
h) understand professional ethics and responsibilities.
i) work as a member and leader in a team in multidisciplinary environment.

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j) communicate effectively.
k) manage the projects keeping in view the economical and societal considerations.
l) recognize the need for adapting to technological changes and engage in life-long learning.

Course objectives:
After completion of this lab, students will get an idea of how to design, simulate and synthesize
various digital circuits. This course presents the students with a top down methodology for
digital circuit using a hardware description language (HDL). The objective is to develop students'
knowledge and expertise in the specialization of digital circuit design with HDL, and present the
techniques from an initial specification down to final implementation with FPGA for rapid
prototyping via top-down design methodology. The course is emphasized on hands-on exercises
of using state-of-the-art Electronic Design Automation (EDA) tools to the complete design of a
controller implemented with FPGA.  The students will be equipped with the knowledge
necessary to design digital circuits for rapid prototyping using HDL.

Course outcomes:
After the completion of course, students will be able to
• learn the digital circuit concepts.
• design the digital circuits.
• develop digital circuits using CAD tools.

CO, PO and PSOs Mapping

2018-19 II B.TECH SEM-II
Cos PO1 PO2 PO3 PO4 PO5 PO6 PO7 PO8 PO9 PO10 PO11 PO12 PSO1 PSO2
CO1 1 1           1 2 2   2 2  
CO2 1 1 3 3 2   1 1 2 2 2 2 3 1
CO3 1 1 3 3 3     1 2 2 2 3 3 2
                           
PSO1: designing electrical,electronics and communication systems in the domains of VLSI,
embedded systems signal processing and RF communications systems and apply modern tools.

PSO2: apply the contextual knowledge of Electronics and Communication Engineering to assess
societal, environmental, health, safety, legal and cultural issues with professional ethics.components

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taking into societal, environmental, health, safety, legal, cultural, ethical and economical

List of Experiments

Part-A: To design and simulate using Electronic Workbench

1. Full adder.
2. 8:1 multiplexer.
3. SR and D flip-flop.
4. Shift register
5. Asynchronous counter.
6. Open Ended Experiment

Part B: To design and simulate using CAD tools

1. 8:3 priority encoder.
2. Ring counter.
3. Asynchronous counter.
4. Simple Datapath
5. ALU Design
6. Open Ended Experiment

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INDEX
Page
S. No. Name of the Experiment
No.
Part-A

1 Full adder. 7-9

2 8:1 multiplexer. 10-12

3 SR and D flip-flop. 13-17

4 Shift register 18-19

5 Asynchronous counter. 20-21

Part-B

6 8:3 priority encoder. 22-23

7 Ring counter. 24-25

8 Asynchronous counter. 26

9 Simple Datapath 27-29

10 ALU Design 30-31

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PART-A
1. Full Adder
Aim:
To test the functionality of full adder using NAND gates.
Tools Required:
NI Multisim 14.0

Theory:

To construct a full adder circuit, we’ll need three inputs and two outputs. Since we’ll have both
an input carry and an output carry, we’ll designate them as CIN and COUT. At the same time, we’ll
use S to designate the final Sum output. The resulting truth table is shown to the right.
This is looking a bit messy. It looks as if C OUT may be either an AND or an OR function,
depending on the value of A, and S is either an XOR or an XNOR, again depending on the value
of A. Looking a little more closely, however, we can note that the S output is actually an XOR
between the A input and the half-adder SUM output with B and C IN inputs. Also, the output carry
will be true if any two or all three inputs are logic 1.
What this suggests is also intuitively logical: we can use two half-adder circuits. The first will
add A and B to produce a partial Sum, while the second will add C IN to that Sum to produce the
final S output. If either half-adder produces a carry, there will be an output carry. Thus, C OUT will
be an OR function of the half-adder Carry outputs. The resulting full adder circuit is shown here

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Logic Symbols & Function tables of ICs

Fig. 1.1 Full Adder with gates

Table 1.1: Truth Table

Procedure:
1. Connect the circuit as shown in figure.

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2. Apply Vcc & ground signal to every IC.

3. Observe the input & output according to the truth table.

Experimental Setup

Fig: Full- Adder

Precautions:

1) Make the connections according to the IC pin diagram.

2) The connections should be tight.

3) The Vcc and ground should be applied carefully at the specified pin only.

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2. 8*1 Multiplexer
Aim:
To design and test the functionality of 8*1Mux using basic gates.
Tools Required:
NI Multisim 14.0
Theory:

The multiplexer or MUX is a digital switch, also called as data selector. It is a combinational
circuit with more than one input line, one output line and more than one select line. It allows the
binary information from several input lines or sources and depending on the set of select lines,
particular input line, is routed onto a single output line.

An 8-to-1 multiplexer consists of eight data inputs D0 through D7, three input select lines S2
through S0 and a single output line Y. Depending on the select lines combinations, multiplexer
decodes the inputs.

The below figure shows the block diagram of an 8-to-1 multiplexer with enable input that enable
or disable the multiplexer. Since the number data bits given to the MUX are eight then 3 bits
(23=8) are needed to select one of the eight data bits. An 8-to-1 multiplexer consists of eight data
inputs D0 through D7, three input select lines S2 through S0 and a single output line Y.
Depending on the select lines combinations, multiplexer decodes the inputs. The below figure
shows the block diagram of an 8-to-1 multiplexer with enable input that enable or disable the
multiplexer. Since the number data bits given to the MUX are eight then 3 bits (23=8) are needed
to select one of the eight data bits.
Logic Symbols & Function tables of ICs

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Fig. 1.1 8*1 Mux

Table 1.1: Truth Table

Procedure:
1. Connect the circuit as shown in figure.
2. Apply Vcc & ground signal to every IC.
3. Observe the input & output according to the truth table.

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Experimental Setup
U6B
VDD VDD
VDD
5.0V 5.0V
5.0V
74HC21D_4V
U6A

S2A S3A
S1A
Key = A Key = A
Key = A
74HC21D_4V
U2A

LED1
74HC21D_4V A

U2B

U1A U7A
U3A
74HC04D_4V 74HC04D_4V 74HC21D_4V
74HC04D_4V
U4A

74HC21D_4V
U8
1 U4B
Key = Space

74HC21D_4V
U5A

74HC21D_4V
U5B

Fig: 74HC21D_4V Schematic

Diagram of 8X1 MUX

Precautions:

1) Make the connections according to the IC pin diagram.

2) The connections should be tight.

3) The Vcc and ground should be applied carefully at the specified pin only.

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3. a) S-R Flip flop

Aim:
To test the functionality of S-R Flip flop using NAND gates.

Tools Required:
NI Multisim 14.0

Theory:

An SR Flip Flop is an arrangement of logic gates that maintains a stable output even after the
inputs are turned off.  This simple flip flop circuit has a set input (S) and a reset input (R). The
set input causes the output of 0 (top output) and 1 (bottom output).  The reset input causes the
opposite to happen (top = 1, bottom =0).  Once the outputs are established, the wiring of the
circuit is maintained until S or R go high, or power is turned off to the circuit.

This is a simple model of how one bit of RAM can be perpetuated.  There are many issues not
shown here such as timing inputs and synchronization, but the simplicity of the circuit gives you
an idea of how RAM operates

Logic Symbols & Function tables of ICs

Fig. 1.1 High Activated Clocked SR Flip-flop

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Table 1.1: Truth Table

Explanation:
1. Q is set to 1 when the S input goes to logic 1.
2. This is remembered on Q after the S input returns to logic 0.
3. Q is reset set to 0 when the R input goes to logic 1.
4. This is remembered on Q after the R input returns to logic 0.
5. If both inputs are at logic 1, Q is the same as Q (the non-allowed state).
6. The state of the outputs cannot be guaranteed if the inputs change from 1,1 to 0, 0 at the
same time.

Procedure:
1. Connect the circuit as shown in figure.
2. Apply Vcc & ground signal to every IC.
3. Observe the input & output according to the truth table.

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Experimental Setup

Fig 1.2: circuit diagram for SR flip flop

Precautions:

1) Make the connections according to the IC pin diagram.

2) The connections should be tight.

3) The Vcc and ground should be applied carefully at the specified pin only.

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3. b) D Flip flop
Aim:
To test the functionality of D Flip flop using NAND gates.

Tools Required:
NI Multisim 14.0

Theory:

D flip flop is a better alternative that is very popular with digital electronics. They are commonly
used for counters and shift-registers and input synchronization. In a D flip flop, the output can be
only changed at the clock edge, and if the input changes at other times, the output will be
unaffected.

Logic Symbol & Circuit Diagram & Function table :

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Procedure:
1. Connect the circuit as shown in figure.
2. Apply Vcc & ground signal to every IC.
3. Observe the input & output according to the truth table.

Experimental Setup

Precautions:

1) Make the connections according to the IC pin diagram.

2) The connections should be tight.

3) The Vcc and ground should be applied carefully at the specified pin only.

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4. Shift Register

Aim:
To design and test the functionality of 4-bit shift register.

Tools Required:
NI Multisim 14.0

Theory:

In digital circuits, a shift register is a cascade of flip flops, sharing the same clock, in
which the output of each flip-flop is connected to the "data" input of the next flip-flop in the
chain, resulting in a circuit that shifts by one position the "bit array" stored in it, "shifting in" the
data present at its input and 'shifting out' the last bit in the array, at each transition of the clock
input.More generally, a shift register may be multidimensional, such that its "data in" and stage
outputs are themselves bit arrays; this is implemented simply by running several shift registers of
the same bit-length in parallel.
Shift registers can have both parallel and serial inputs and outputs. These are often
configured as "serial-in, parallel-out" (SIPO) or as "parallel-in, serial-out" (PISO). There are also
types that have both serial and parallel input and types with serial and parallel output. There are
also "bidirectional" shift registers which allow shifting in both directions: L→R or R→L.

Logic Diagram

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Procedure:
1. Connect the circuit as shown in figure.
2. Apply Vcc & ground signal to every IC.
3. Observe the input & output according to the truth table.

Experimental Setup

Precautions:

1) Make the connections according to the IC pin diagram.

2) The connections should be tight.

3) The Vcc and ground should be applied carefully at the specified pin only.

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5. Asynchronous Counter

Aim:
To design and test the functionality of 4-bit Asynchronous Counter.

Tools Required:
NI Multisim 14.0
Theory:

An Asynchronous counter can count using Asynchronous clock input. Counters can be easily
made using flip-flops. As the count depends on the clock signal, in case of an Asynchronous
counter, changing state bits are provided as the clock signal to the subsequent flip-flops. Those
Flip-flops are serially connected together, and the clock pulse ripples through the counter. Due to
the ripple clock pulse, it’s often called a ripple counter. An Asynchronous counter can count 2n –
1 possible counting states.

Logic Diagram

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Procedure:
1. Connect the circuit as shown in figure.
2. Apply Vcc & ground signal to every IC.
3. Observe the input & output according to the truth table.

Experimental Setup

Precautions:

1) Make the connections according to the IC pin diagram.

2) The connections should be tight.

3) The Vcc and ground should be applied carefully at the specified pin only.

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PART-B

6. 8X3 PRIORITY ENCODER

Aim: To design a 8X3 Priority Encoder and simulation, synthesis has to be performed.

Tools Required: Personal Computer with Xilinx ISE Design Software 14.2

Program:
module priorityencoder(
input [7:0] inp,
output reg[2:0] y
);
always @ (inp)
begin
casex (inp)
8'b00000001: y = 3'b000;
8'b0000001x: y = 3'b001;
8'b000001xx: y = 3'b010;
8'b00001xxx: y = 3'b011;
8'b0001xxxx: y = 3'b100;
8'b001xxxxx: y = 3'b101;
8'b01xxxxxx: y = 3'b110;
8'b1xxxxxxx: y = 3'b111;
default: y =3'bxxx;
endcase
end
endmodule

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RTL Schematic:

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7. RING COUNTER
Aim: To design a Ring Counter and simulation, synthesis has to be performed.

Tools Required: Personal Computer with Xilinx ISE Design Software 14.2

Program:
module ringcounter(
input clk,
input reset,
output reg [3:0] q
);
always @(posedge clk, posedge reset)
if(reset==1)
q<=4′b1000;
else
begin
q[3]<=q[0];
q[2]<=q[3];
q[1]<=q[2];
q[0]<=q[1];
end
endmodule

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RTL Schematic:

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8.ASYNCHRONOUS COUNTER

Aim: To design a Asynchronous Counter and simulation, synthesis has to be performed.

Tools Required: Personal Computer with Xilinx ISE Design Software 14.2
Program:
module counter4bit(
input clk,
input reset,
output reg [3:0] q
);
always @ (posedge clk, posedge reset)
begin
if( reset==1'b1)
q<=4'b0000;
else
q<=q+4'b0001;
end
endmodule

RTL Schematic:

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9. Data path
Aim: To design a simple data path and simulation, synthesis has to be performed.
Tools Required: Personal Computer with Xilinx ISE Design Software 14.2
Block diagram:

Program:
Serial in Parallel out Register (SIPO) program:
module sipo( input clk, input reset, input sin, output [3:0] pout );
reg [3:0]temp;
always @ (posedge clk,posedge reset)
begin
if (reset==1'b1)
temp<=4'b0000;
else
begin
temp[3] <=sin;
temp[2]<=temp[3];
temp[1]<=temp[2];
temp[0]<=temp[1];
end
end
assign pout=temp;
endmodule
Parallel in Serial out (PISO) Register:
module piso( input clk, input reset, input load, input [3:0] pin, output reg sout );
reg [3:0] temp;
always @ (posedge clk, posedge reset,posedge load)

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begin
if (reset ==1'b1)
sout <=1'b0;
else
if (load==1'b1)
temp<=pin;
else
begin
sout<=temp[3];
temp[3]<=temp[2];
temp[2]<=temp[1];
temp[1]<=temp[0];
end
end
endmodule
ALU:
module ALU( input [3:0] A, input [3:0] B, input [2:0] Control, output reg[3:0] Out, output
reg Cout );

always @ (A,B, Control)

begin
case(Control)
3'b000: {Cout,Out} = A+B;
3'b001: {Cout,Out} = A-B;
3'b010: Out = A*B;
3'b011: Out = A+1;
3'b100: Out = A|B;
3'b101: Out = A&B;
3'b110: Out = A^B;
3'b111: Out = ~A;
default: Out = 4'b0000;
endcase
end
endmodule
Data path (Top Module):
module datapath( input clk, input reset, input load, input A, input B, input [2:0] control,
output Out, output Cout );

wire [3:0] poutA,poutB,aluout;

sipo a1(clk,reset,A,poutA);
sipo a2(clk,reset,B,poutB);
ALU a3 (poutA,poutB,control,aluout,Cout);
piso a4 (clk,reset,load,aluout,Out);
endmodule

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RTL Schematic:

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10. ALU

Aim: To design an 8 bit ALU and simulation, synthesis has to be performed.

Tools Required: Personal Computer with Xilinx ISE Design Software 14.2

Program:
module alu(
input [7:0] A,B,
input [2:0] Control,
output reg [7:0] Out,
output reg Cout
);
always @ (A,B, Control)
begin
case(Control)
3'b000: {Cout,Out} = A+B;
3'b001: {Cout,Out} = A-B;
3'b010: Out = A*B;
3'b011: Out = A+1;
3'b100: Out = A|B;
3'b101: Out = A&B;
3'b110: Out = {A[7:0],1'b0};
3'b111: Out = {1'b0, A[7:1]};
endcase
end
endmodule

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RTL Schematic:

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