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Processor Performance Enhancement

The document discusses several techniques for enhancing processor performance: 1. Clock speed, cache memory, and number of cores all impact processor performance, with higher clock speeds, more cache, and additional cores allowing more instructions to be processed per second. 2. Pipelining improves performance by allowing the processor to fetch, decode, and execute instructions simultaneously rather than sequentially. 3. Contemporary architectures combine aspects of von Neumann and Harvard architectures, using separate caches and buses for instructions and data while storing both in main memory.

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Sheraz Ali
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456 views

Processor Performance Enhancement

The document discusses several techniques for enhancing processor performance: 1. Clock speed, cache memory, and number of cores all impact processor performance, with higher clock speeds, more cache, and additional cores allowing more instructions to be processed per second. 2. Pipelining improves performance by allowing the processor to fetch, decode, and execute instructions simultaneously rather than sequentially. 3. Contemporary architectures combine aspects of von Neumann and Harvard architectures, using separate caches and buses for instructions and data while storing both in main memory.

Uploaded by

Sheraz Ali
Copyright
© © All Rights Reserved
Available Formats
Download as DOCX, PDF, TXT or read online on Scribd
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Processor Performance Enhancement


The performance of a CPU can be affected by 3 different quantities: Clock speed, cache
memory, and number of cores. These quantities are very important for processor performance.

Clock Speed
The clock speed of the processor is the number of FDE Cycles it can perform per second, for
example 3.4 GHz is 3,400,000,000 cycles per second. The higher the clock speed, the greater
the number of FDE Cycles that can occur each second, hence higher clock speeds improve
performance.
Cache Memory
Cache Memory is memory which is built directly into the CPU. It is far faster to access than
RAM, as it is much closer to the registers that require the data, and it also operates at a similar
speed to the CPU, so has very little lag comparative to retrieving data from RAM. It contains
multiple levels of cache which differ in size and distance from the CPU, Level 1, 2 and 3 cache.
Level 1 is closest to the CPU and is the smallest, whereas Level 3 is furthest from the CPU and
is the biggest. The reason all the cache isn't simply made Level 1 is cost- faster memory is more
expensive.
Frequently used data such as parts of the OS are stored in the cache, allowing the processor to
run faster as it doesn't have to rely on slower fetches from the RAM as often.
Number of Cores
A multi-core processor is one which contains multiple distinct processing units within a single
CPU. Each core can operate independently of the others, and will each have their own low-
level cache, as well as sharing a high-level cache. Different cores can run different applications
at the same time during multitasking, allowing more actions to occur each second.
However, multiple cores do not always improve processor performance; if a core is processing
an instruction which is dependent on the outcome of another instruction, being processed by
another core, it will have to wait until that core returns a result before the instruction can finish
processing. This can cause hanging, where a core is wasted while it waits for the result of
another instructions execution.

Following is a technique that is used to enhance processor performance.


Pipelining
Pipelining is a process that can be used to improve the performance of a CPU. It operates in
such a way that while the processor is decoding an instruction, the next instruction can be
fetched from memory. This works best in code where the next instruction is not dependent on
the instruction before it- when code branches, the CPU will have decoded the wrong next
instruction and so will have to 'clear the pipes' by getting rid of the current fetch and decode
steps.
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In other words, pipelining technique executes one instruction, while the next instruction is
being decoded, and the instruction after that is being fetched. This allows high efficiency of
the components/processes in a CPU.
Pipelining does have its downsides for instance, it is not always possible to predict the
instruction that needs to be fetched and decoded next. For instance, a program that has IF
statements will require ‘instruction jumps’. As a result, the pipeline must be ‘flushed’, and then
obtain the correct instruction. The more often the pipeline is flushed, the less of a benefit the
pipeline becomes.

An example of CPU Instruction Pipelining

Step Fetch Decode Execute

Step 1 Instruction 1

Step 2 Instruction 2 Instruction 1

Step 3 Instruction 3 Instruction 2 Instruction 1

Step 4 Instruction 4 Instruction 3 Instruction 2

Contemporary Architecture
This is a modified form of Harvard Architecture. It relaxes the strict separation of data and
instructions, but still lets the CPU access more than 2 memory buses. Contemporary processors
use a mixture of both von Neumann and Harvard architecture, which differs from a pure von
Neumann architecture by using von Neumann architecture for the main memory to the CPU
and Harvard for the control unit and caches.
Following are the details of Von Neumann and Harvard architecture.

Von Neumann Architecture


This architecture has a single control unit. It works sequentially through instructions, and stores
instructions and data together in the same memory unit. A von Neumann architecture has
only one bus which is used for both data transfers and instruction fetches, and therefore data
transfers and instruction fetches must be scheduled - they cannot be performed at the same
time. A Von Neumann CPU has a control unit. The control unit is in charge of 'fetching' each
instruction that needs to be executed in a program by issuing control signals to the hardware.
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It then decodes the instruction and finally issues more control signals to the hardware to
actually execute it.

Harvard Architecture
This architecture is almost identical to Von Neumann; however, it stores data and instructions
in separate memory units. The CPU is also capable of reading an instruction and performing
memory access at the same time, even without a cache. This is because there are separate buses
for the data and instructions. It is possible to have two separate memory systems for a Harvard
architecture and to use pipelining.

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