FLYNNS TAXONOMY OF COMPUTER ARCHITECTURE

Sureja Rajani R. (12MECE32) M.Tech (Embedded System) Nirma Institute of Technology

ABSTRACT: Flynn's taxonomy is a classification of computer architectures, proposed by Michael J. Flynn. The four classifications defined by Flynn are based upon the number of concurrent instruction (or control) and data streams available in the architecture: Single Instruction, Single Data stream (SISD) :A sequential computer which exploits no parallelism in either the instruction or data streams. Single control unit (CU) fetches single Instruction Stream (IS) from memory. The CU then generates appropriate control signals to direct single processing element (PE) to operate on single Data Stream (DS) i.e. one operation at a time Examples of SISD architecture are the traditional uniprocessor machines like a PC (currently manufactured PCs have multiple processors) or old mainframes. Single Instruction, Multiple Data streams (SIMD): A computer which exploits multiple data streams against a single instruction stream to perform operations which may be naturally parallelized. For example, an array processor or GPU. Multiple Instruction, Single Data stream (MISD): Multiple instructions operate on a single data stream. Uncommon architecture which is

generally used for fault tolerance. Heterogeneous systems operate on the same data stream and must agree on the result. Examples include the Space Shuttle flight control computer. Multiple Instruction, Multiple Data streams (MIMD): Multiple autonomous processors simultaneously executing different instructions on different data. Distributed systems are generally recognized to be MIMD architectures; either exploiting a single
shared memory space or a distributed memory space. A multi-core superscalar processor is an MIMD processor.

1 ) SISD In computing, SISD (single instruction, single data) is a term referring to a computer architecture in which a single processor, a uniprocessor, executes a single instruction stream, to operate on data stored in a single memory. This corresponds to the von Neumann architecture. SISD is one of the four main classifications as defined in Flynn's taxonomy. In this system classifications are based upon the number of concurrent instructions and data streams present in the computer architecture. According to Michael J. Flynn, SISD can have concurrent processing

characteristics. Instruction fetching and pipelined execution of instructions are common examples found in most modern SISD computers.

2.1 ) Advantages An application that may take advantage of SIMD is one where the same value is being added to (or subtracted from) a large number of data points, a common operation in many multimedia applications. One example would be changing the brightness of an image. Each pixel of an image consists of three values for the brightness of the red (R), green (G) and blue (B) portions of the color. To change the brightness, the R, G and B values are read from memory, a value is added to (or subtracted from) them, and the resulting values are written back out to memory. With a SIMD processor there are two improvements to this process. For one the data is understood to be in blocks, and a number of values can be loaded all at once. Instead of a series of instructions saying "get this pixel, now get the next pixel", a SIMD processor will have a single instruction that effectively says "get n pixels" (where n is a number that varies from design to design). For a variety of reasons, this can take much less time than "getting" each pixel individually, as with traditional CPU design. Another advantage is that SIMD systems typically include only those instructions that can be applied to all of the data in one operation. In other words, if the SIMD system works by loading up eight data points at once, the add operation being applied to the data will happen to all eight values at the same time. Although the same

2 ) SIMD Single instruction, multiple data (SIMD), is a class of parallel computers in Flynn's taxonomy. It describes computers with multiple processing elements that perform the same operation on multiple data points simultaneously. Thus, such machines exploit data level parallelism. SIMD is particularly applicable to common tasks like adjusting the contrast in a digital image or adjusting the volume of digital audio. Most modern CPU designs include SIMD instructions in order to improve the performance of multimedia use.

is true for any super-scalar processor design, the level of parallelism in a SIMD system is typically much higher. 2.2 ) Disadvantages

available in some SIMD instruction sets. Instruction sets are architecturespecific: old processors and non-x86 processors lack SSE entirely, for instance, so programmers must provide non-vectorized implementations (or different vectorized implementations) for them. The early MMX instruction set shared a register file with the floating-point stack, which caused inefficiencies when mixing floatingpoint and MMX code. However, SSE2 corrects this.

Not all algorithms can be vectorized. For example, a flow-control-heavy task like code parsing wouldn't benefit from SIMD. It also has large register files which increases power consumption and chip area. Currently, implementing an algorithm with SIMD instructions usually requires human labor; most compilers don't generate SIMD instructions from a typical C program, for instance. Vectorization in compilers is an active area of computer science research. (Compare vector processing.) Programming with particular SIMD instruction sets can involve numerous low-level challenges. SSE (Streaming SIMD Extension) has restrictions on data alignment; programmers familiar with the x86 architecture may not expect this. Gathering data into SIMD registers and scattering it to the correct destination locations is tricky and can be inefficient. Specific instructions like rotations or three-operand addition are not

Conclusion: Generally used for Data Level Parallism 3 ) MISD In computing, MISD (multiple instruction, single data) is a type of parallel computing architecture where many functional units perform different operations on the same data. Pipeline architectures belong to this type, though a purist might say that the data is different after processing by each stage in the pipeline. Fault-tolerant computers executing the same instructions redundantly in order to detect and mask errors, in a manner known as task replication, may be considered to belong to this type. Not many instances of this architecture exist, as MIMD and SIMD are often more appropriate for common data parallel techniques. Specifically, they allow

better scaling and use of computational resources than MISD does. However, one prominent example of MISD in computing are the Space Shuttle flight control computers.

memory machines may be of the busbased or hierarchical type. Distributed memory machines may have hypercube or mesh interconnection schemes. A multi-core CPU is an MIMD machine.

A systolic array is an example of a MISD structure. Linda Null and Julia Lobur classify systolic arrays as SIMD. 4 ) MIMD In computing, MIMD (multiple instruction, multiple data) is a technique employed to achieve parallelism. Machines using MIMD have a number of processors that function asynchronously and independently. At any time, different processors may be executing different instructions on different pieces of data. MIMD architectures may be used in a number of application areas such as computer-aided design/computer-aided manufacturing, simulation, modeling, and as communication switches. MIMD machines can be of either shared memory or distributed memory categories. These classifications are based on how MIMD processors access memory. Shared 4.1)Shared Memory (Multiprocessor): Model

The processors are all connected to a "globally available" memory, via either a software or hardware means. The operating system usually maintains its memory coherence.

From a programmer's point-of-view, this memory model is better understood than the distributed memory model. Another advantage is that memory coherence is managed by the operating system and not the written program. Two known disadvantages are: scalability beyond thirty-two processors is difficult, and the shared memory model is less flexible than the distributed memory model. There are many examples of shared memory (multiprocessors): UMA (Uniform Memory Access), COMA (Cache Only Memory Access) and NUMA (Non-Uniform Memory Access). These models are differ in how the memory and peripheral resources are shared or Distributed. UMA Model: In this model the physical memory is uniformly shared by all the processors. All processors have equal access time to all memory words, which is why it is called uniform memory access. Each processor may use a private cache. Peripherals are also shared. Multi processors are called tightly coupled systems due to high degree of resource sharing. UMA model is suitable for time sharing applications by multiple users. It can be used to speed up the execution of single large program in time critical application. When all processors have equal access to all peripheral devices, the system is called a symmetric multiprocessor. In this case, all

the processors are equally capable of running executive program, such as kernel. In an asymmetric multiprocessor, only one or subset of processors are executive capable. An executive or master processor can execute the operating system and handle I/O. The remaining processors called attached processors (AP) executes user code under the supervision of master processor.

Cache coherence is usually through snoopy protocols for bus-based architectures NUMA Model: A NUMA multiprocessor is a shared memory system in which the access time varies with the location of memory word. Two NUMA machine models are depicted. The shared memory is physically distributed to all processors, called local memories. The collection of all local memories forms a global address space accessible by all processors. It is faster to access a local memory with a local processor. The access of remote memory attached to other

processors takes longer due to the added delay through the interconnection network.

4.1.2) Hierarchical MIMD machines with hierarchical shared memory use a hierarchy of buses to give processors access to each other's memory. Processors on different boards may communicate through inter-nodal buses. Buses support communication between boards. With this type of architecture, the machine may support over a thousand processors. 4.2) Distributed Model(Multicomputers) Memory

3) COMA

This model is a special case of NUMA machine where distributed main memories are replaced with cache memory. At individual processor node, there is no memory hierarchy. All cache made a global address space. Depending on interconnection network used, directories may be used to help in locating copies of cache blocks.

4.1.1) Bus-based MIMD machines with shared memory have processors which share a common, central memory. In the simplest form, all processors are attached to a bus which connects them to memory.

In distributed memory MIMD machines, each processor has its own individual memory location. Each processor has no direct knowledge about other processor's memory. For data to be shared, it must be passed from one processor to another as a message. Since there is no shared memory, contention is not as great a problem with these machines. It is not economically feasible to connect a large number of processors directly to each other. A way to avoid this multitude of direct connections is to connect each processor to just a few others. This type of design can be inefficient because of the added time required to pass

a message from one processor to another along the message path. The amount of time required for processors to perform simple message routing can be substantial. Systems were designed to reduce this time loss and hypercube and mesh are among two of the popular interconnection schemes. As examples of distributed memory(multicomputers): MPP (massively parallel processors) and COW (Clusters of Workstations). The first one is complex and expensive: lots of super-computers coupled by broad-band networks. Examples: hypercube and mesh interconections. COW is the "home-made" version for a fraction of the price. Cache coherence usually maintained through directory based protocols 4.2.1) Hypercube interconnection network In an MIMD distributed memory machine with a hypercube system interconnection network containing four processors, a processor and a memory module are placed at each vertex of a square. The diameter of the system is the minimum number of steps it takes for one processor to send a message to the processor that is the farthest away. So, for example, the diameter of a 2-cube is 1. In a hypercube system with eight processors and each processor and memory module being placed in the vertex of a cube, the diameter is 3. In general, a system that contains 2^N processors with each processor directly connected to N other processors, the

diameter of the system is N. One disadvantage of a hypercube system is that it must be configured in powers of two, so a machine must be built that could potentially have many more processors than is really needed for the application. 4.2.2) Mesh interconnection network In an MIMD distributed memory machine with a mesh interconnection network, processors are placed in a two-dimensional grid. Each processor is connected to its four immediate neighbors. Wraparound connections may be provided at the edges of the mesh. One advantage of the mesh interconnection network over the hypercube is that the mesh system need not be configured in powers of two. A disadvantage is that the diameter of the mesh network is greater than the hypercube for systems with more than four processors.

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