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Lower Sixth Science, 2 Sequence Test. Computer Science November 2014, Time 2hours

The document is a past exam for a lower sixth science class in Cameroon on the topic of computer science. It contains 30 multiple choice questions testing knowledge of topics like CPU and memory components, interrupts, Boolean logic, and characteristics of different types of memory like RAM, ROM, and cache.

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Ferdinand Ngum
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Download as PDF, TXT or read online on Scribd
0% found this document useful (0 votes)
138 views

Lower Sixth Science, 2 Sequence Test. Computer Science November 2014, Time 2hours

The document is a past exam for a lower sixth science class in Cameroon on the topic of computer science. It contains 30 multiple choice questions testing knowledge of topics like CPU and memory components, interrupts, Boolean logic, and characteristics of different types of memory like RAM, ROM, and cache.

Uploaded by

Ferdinand Ngum
Copyright
© © All Rights Reserved
Available Formats
Download as PDF, TXT or read online on Scribd
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REPUBLIC OF CAMEROON REPUBLIQUE DU CAMEROUN

Peace Work Fatherland Paix Travail Patrie


MINISTRY OF SECONDARY EDUCATION MINISTERE DE L’ENSEIGNEMENT SECONDAIRE
GOVERNMENT BILINGUAL HIGHSCHOOL LYCEE BILINGUE DE BAMENDA
(G.B.H.S) BAMENDA

Lower Sixth Science, 2nd Sequence Test.


Computer Science
November 2014, Time 2hours

8. A signal sent to the CPU from a device, causing


1. Which of the following examples uses an the CPU to stop what it is doing and start doing
embedded system. Select the best answer. something else is known as:
A Desktop computer. A An interrupt signal.
B Network server. B An interrupt.
C Television set. C Process interrupt.
D Network router. D An I/O interrupt.
2. Arrange in increasing order of storage 9. The number of address lines required to address
capacity: a memory of size 32 k is:
A Register, RAM, Tapes, Disks. A 15 lines
B Register, Tapes, RAM, Disks. B 16 lines
C Tapes, Disks, RAM, Register. C 18 lines
D Register, RAM, Disks, Tapes. D 14 lines
3. When the main memory of a computer is 10. An address bus from a storage unit has 32 bus
unable to keep all data and instructions of a lines. What is the capacity of the storage unit?
program, the program can behave as if it has (Assume 1GB = 1024 MB and 1MB = 1024 KB)
unlimited memory by using a(n): A 4GB.
A Cache memory. B 512 MB.
B DRAM. C 512 GB.
C Virtual memory. D 4 MB.
D SRAM. 11. Given a 7-segment decoder that prints digits in
4. How many bits are in the extended ASCII the form below:
code of a character? 8 2
A 16
etc. For digits 0 to 9, how many bits should the
B 7 decoder have for its input?
C 32
A 7 bits.
D 8
B 10 bits.
5. The register that keeps track of program C 4 bits.
instructions during execution is a(n) D 8 bits.
A Address register.
B Program counter. 12. The expression in Boolean algebra is
C Data register. equivalent to:
D Accumulator. A .
6. Programs which are treated as hardware and B .
stored in the ROM are known as C .
A Middleware D B+A .
B Software
13. What is the equivalent circuit for the expression?
C Firmware
=S
D ROMware
(A) A S
7. The examining and possibly changing of sets B
of single bits within a machine word is
called: (B) A S
A Word manipulation. B
B Byte manipulation.
C Bit manipulation. ( C) A
S
D Bit slice manipulation. B

(D) A S
B
2
14. According to the Von Neumann computer D. Non-execution of priority processes
model, 23. The hardware instruction cycle is
A. A computer must have a secondary A. fetch decode store
B. fetch execute decode
memory
C. decode execute store
B. A computer must have a memory D. fetch decode execute store
C. A computer may not have a storage unit 24. The hardware activity that consists of the CPU
D. All of the above. checking constantly to see if device is ready is
15. Cache memory works on the principle of: known as;
A. Locality of data. A. Spooling
B. Locality of reference. B. Polling
C. Locality of memory. C. Buffering
D. Locality of reference & memory. D. Interruption
16. When a CD is inserted into the CD-drive a 25. The process of polling is
signal goes to the CPU to indicate that the A. Time saving
input device is ready. What is this signal B. Difficult to implement
C. Time wasting
called?
D. User friendly
A. Clock signal
26. Interrupts are;
B. An interrupt A. Time consuming
C. A system call B. Unfriendly to users
D. wakeup call C. Useful in multi-programming
17. The CPU D. Useful for real time processing
A. Execute system software instructions. 27. It takes a longer time to access information on a
B. Execute application software instructions permanent storage medium than in the RAM
because
C. Is not necessary for wireless devices. A. Access is by use of a device
D. Is both A and B B. Access is sequential
18. What characteristic of ROM memory makes C. The medium can be taken out of the
it suitable for use in embedded systems? computer
A. too slow D. The medium is made of magnetic
B. it is non programmable material
C. it keeps information permanently 28. The BIOS-ROM is considered as memory
D. it has a high capacity. because
19. Cache memory acts between A. it contains boot instructions for the
A. CPU and RAM computer.
B. RAM and ROM B. it only works when power is turned on.
C. CPU and Hard Disk C. it is on during processing.
D. None of these D. it is used by processor for the power on
20. Generally Dynamic RAM is used as main self test (POST).
memory in a computer system as it 29. A PROM can be rewritten only when
A. Consumes less power A. some of the information to be written is
B. has higher speed already in the PROM.
C. has lower cell density B. part of the information in the PROM is to
D. needs refreshing circuitary be written
21. The memory unit that communicates directly C. all information in the PROM is part of
with the CPU is called the the information to be written.
A. main memory D. all of the above.
B. Secondary memory 30. To read data from memory the CPU puts address
C. shared memory of memory location in the
D. auxiliary memory. A. MAR and sets the read/write line to 0.
22. Interrupt driven input output leads to B. MDR and sets the read/write line to 1.
A. Wastage of CPU time C. MAR and sets the read/write line to
B. Optimum use of CPU time D. MDR and sets the read/write line to 0.
C. Adequate execution of real time
processes

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