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Faults in Digital Testing Systems

A fault model identifies targets for testing. A fault model makes analysis possible models are often easier to work with models are portable models can be used for simulation, thus avoiding expensive hardware / actual circuit implementation. LOGICAL fault models represent the effect of physical faults on the behaviour of the modeled system.

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356 views

Faults in Digital Testing Systems

A fault model identifies targets for testing. A fault model makes analysis possible models are often easier to work with models are portable models can be used for simulation, thus avoiding expensive hardware / actual circuit implementation. LOGICAL fault models represent the effect of physical faults on the behaviour of the modeled system.

Uploaded by

kumarbsnsp
Copyright
© Attribution Non-Commercial (BY-NC)
Available Formats
Download as PPT, PDF, TXT or read online on Scribd
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FAULTS IN DIGITAL TESTING SYSTEMS

CONTENTS
Why model faults? Types of faults Stuck-at faults Fault detection and Redundancy Sensitization and Detectability Conclusion

Why Model Faults?


I/O function tests inadequate for manufacturing (functionality versus component and interconnect testing) A fault model identifies targets for testing. A fault model makes analysis possible Models are often easier to work with Models are portable Models can be used for simulation, thus avoiding expensive hardware/actual circuit implementation

TYPES OF FAULTS
i. ii. Logical Fault Models Structural faults & Functional faults Intermittent faults Single and multiple faults

LOGICAL FAULT MODELS


They represent the effect of physical faults on the behaviour of the modeled system. Factors affecting faults One, that affect the logical function Delay faults that affect the operating speed of the system. Types 1) Explicit fault model 2) Implicit fault model

Explicit Fault model:


A fault universe in which every fault is individually identified and hence the faults could be explicitly enumerated.

Implicit Fault Model:


A fault universe got by collectively identifying the faults of interest typically defining the characterizing properties.

STRUCTURAL AND FUNCTIONAL FAULTS


Faults defined in conjunction with structural models are called structural faults Changes the interconnection among components. Faults defined in conjunction with functional models are called functional faults Change the truth table of a component.

INTERMITTENT FAULTS
They Depend on the frequency and statistical details of their occurrence The data is not available and so online testing is the only solution to detect intermittent or transient faults.

THE SHORT & OPEN


A short is formed by connecting two lines that are not to be connected. A short between 2 signal lines creates a logic function.The logical fault representing such a short is called bridging fault. An open is formed by breaking the connection between the signal lines.

STUCK AT FAULT
If a line is shorted with Power or Gnd leading to the line taking a fixed logical value then it is a stuck-at fault denoted by s-a-v, v is in {0,1}. A line with only one fan-out takes a constant value and hence appear as a stuck fault.

MULTIPLE STUCK AT FAULT


A multiple stuck-at fault means that any set of lines is stuck-at some combination of (0,1) values. The total number of single and multiple stuck-at faults in a circuit with k single fault sites is 3k-1.

FAULT DETECTION AND REDUNDANCY


Combinational Circuits - terminologies
Z(x) be a logic function realized by a combinational circuit N, to an arbitrary input vector x. t denotes a specific input vector and Z(t) is the response of N to t. For a multiple output function Z(t) is also a vector

CONTD
A circuit with fault f transforms N to Nf. So the circuit realizes Zf(x) instead of Z(x). Let t be a test vector. Then,
A test (vector) t detects a fault f iff Zf(t) is different from Z(t)

Z: {x1x2,x2x3} Zf : {x1+x2, (x1+x2)x3}

For a single output circuit, a test t that detects a fault f makes Z(t) = 0 and Zf(t) = 1 or vice versa. The set of all tests that detect f is given by the solutions of the equation Z(x) EXOR Zf(x) = 1

Z: (x2+x3)x1 + ~x1x4 and let f be x4:s-a-0 Zf: (x2+x3)x1 Z EXOR Zf = 1

SENSITIZATION
A line whose value in the test t changes in the presence of the fault f is said to be sensitized to the fault f by test t. A path composed of sensitized lines is called a sensitized path.

DETECTABILTY
A fault f is said to be detectable if there exist a test t that detects f otherwise f is an undetectable fault. Undetectable faults-These are not harmless, as they would prevent the detection of other faults.

Y1=~y1x+~y1y2 Y2=xy1(~y2)+~xy2+~y1y2

UNDETECTABLE BRIDGING FAULTS

A combinational Undetectable Simplification circuit with an fault Rule undetectable stuck fault is redundant. AND(NAND) input s- Remove Input a-1 We may remove at least one gate input AND(NAND) input s- Remove gate, a-0 replace by 0(1) or a gate and continue with OR(NOR) input s-a-0 Remove Input simplification.
OR(NOR) input s-a-1 Remove gate, replace by 1(0)

CIRCUIT MINIMIZATION

IRREDUNDANT CIRCUIT
A circuit in which all stuck faults are detectable is called an irredundant circuit. Simplification can be in the form of combining two inverters into a single line etc. Redundancy can also be used to reduce hazards in circuits.

CONCLUSIONS
Fault analysis becomes logical rather than a physical problem Many different physical faults may be modeled as the same logical fault decrease in complexity Most fault models are technology independent and so the models need not change with the rapidly changing technology.

REFERENCE
Digital systems testing and testable design by Miron Abramovici

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