BASIC COMPUTER

ORGANIZATION AND DESIGN

 Architecture vs. Organization
• Architecture:
– Also known as Instruction Set Architecture (ISA)
– Programmer visible part of a processor:
instruction set, registers, addressing modes, etc.
• Organization:
– High-level design: how many caches? how many
arithmetic and logic units? What type of
pipelining, control design, etc.
– Sometimes known as micro-architecture
 Functional Units

Arithmetic
Input and
logic

Memory

Output Control

I/O Processor

Basic functional units of a computer.

 Arithmetic and Logic Unit
(ALU)
 Most computer operations are executed in
ALU of the processor.
 Load the operands into memory – bring them

to the processor – perform operation in ALU –

store the result back to memory or retain in
the processor.
 Registers
 Control Unit
 All computer operations are controlled by the control unit.
 The timing signals that govern the I/O transfers are also
generated by the control unit.
 Operations of a computer:
 Accept information in the form of programs and data through an input
unit and store it in the memory
 Fetch the information stored in the memory, under program control, into
an ALU, where the information is processed
 Output the processed information through an output unit
 INSTRUCTIO
Instruction codes

NS
• Program
– A sequence of (machine) instructions

• (Machine) Instruction
– A group of bits that tell the computer to perform a specific operation (a sequence of
micro-operation)

• The instructions of a program, along with any needed data are

stored in memory
• The CPU reads the next instruction from memory
• It is placed in an Instruction Register (IR)
• Control circuitry in control unit then translates the instruction into
the sequence of micro-operations necessary to implement it
• Ability to store and execute  differs from one to other
 Instruction codes

INSTRUCTION FORMAT

• A computer instruction is often divided into two parts

– An op-code (Operation Code) that specifies the operation for that
instruction
– An address that specifies the registers and/or locations in memory to
use for that operation

Instruction Format

15 14 12 11 0
I Op-code Address

Addressing
mode
 The processor : Data Path and
Control

Data
PC Address Register #
Register A
Instructions Bank L Address
U
Register #
Instruction Data Memory
Memory
Register #
Data
 PROCESSOR Instruction codes

REGISTERS
• A processor has many registers to hold instructions, addresses, data, etc….
• The processor has a register, the Program Counter (PC) that holds the
memory address of the next instruction to get
• Control unit stores instruction after reading it from memory is called as
Instruction Register (IR) .
• In a direct or indirect addressing, the processor needs to keep track of what
locations in memory it is addressing: The Address Register (AR) [Same as
MAR] is used for this
• When an operand is found, using either direct or indirect addressing, it is
placed in the Data Register (DR) [same as MDR]. The processor then uses this
value as data for its operation
• The Basic Computer has a Accumulator (AC) for manipulation of data .
 PROCESSOR Instruction codes

REGISTERS
• The significance of a general purpose register (GPR) is that it can be referred
to, in instructions
– e.g. load AC with the contents of a specific memory location; store the contents of AC into a
specified memory location

• Often a processor will need a scratch register to store intermediate results or

other temporary data; in the Basic Computer this is the Temporary Register
(TR)
• The Basic Computer uses a very simple model of input/output (I/O)
operations
– Input devices are considered to send characters of data to the processor
– The processor can send characters of data to output devices

• The Input Register (INPR) holds character from an input device.

• The Output Register (OUTR) holds character to be send to an output device.
 Stored Program Concept
• CPU consists of ALU & CU • Program + Data  on same memory
• Main Memory • But each memory location must be
addressed independently.
• INPUT & OUTPUT System
• Single path between main memory &
control unit, so control signal can’t
exchange simultaneously.

Von-neuman Architecture
 Basic Operational Concepts
A Typical Instruction
 ADD LOCA, R0
 Add the operand at memory location LOCA to the operand
in a register R0 in the processor.
 Place the sum into register R0.
 The original contents of LOCA are preserved.
 The original contents of R0 is overwritten.
 Instruction is fetched from the memory into the processor –
the operand at LOCA is fetched and added to the contents
of R0 – the resulting sum is stored in register R0.
Memory Access & ALU Operation

Example:-
 Load LOCA, R1

 Add R1, R0

 Whose contents will be overwritten?

 Connection Between the Processor and the Memory
Typical Operating Steps Memory

• Programs reside in the memory through

input devices
• PC is set to point to the first instruction
• The contents of PC are transferred to MAR MAR MDR
Control
• A Read signal is sent to the memory
PC R0
• The first instruction is read out and
R1
loaded into MDR IR
Processor

• The contents of MDR are transferred to IR

• Decode and execute the instruction Rn -
ALU
1
• Get operands for ALU n general purpose
 General-purpose register registers
 Memory (address to MAR – Read – MDR
to ALU)
• Perform operation in ALU
• Store the result back Figure 1.2. Connections between the processor and the memory.
 To general-purpose register
 To memory (address to MAR, result to 1. Instruction register (IR)
MDR – Write)
• During the execution, PC is incremented 2. Program counter (PC)
to the next instruction.

3. General-purpose register (R0 – Rn-1)

4. Memory address register (MAR)

5. Memory data register (MDR)

 Interrupt

• Normal execution of programs may be preempted if

some device requires urgent servicing.
• The normal execution of the current program must be
interrupted – the device raises an interrupt signal.
• Interrupt-service routine
• Current system information backup and restore (PC,
general-purpose registers, control information, specific
information)
 Bus Structures
• There are many ways to connect different parts inside a
computer together.
• A group of lines that serves as a connecting path for several
devices is called a bus.
• Address/data/control

Input Output Memory Processor

Figure 1.3. Single-bus structure.

 Performance
• The most important measure of a computer is how quickly it can execute
programs.
• Three factors affect performance:
 Hardware design
 Instruction set
 Compiler
• Processor time to execute a program depends on the hardware involved in
the execution of individual machine instructions.

Main Cache
memory memory Processor

Bus
 Processor Clock
• Clock :- Processor circuits are controlled by timing signal
• Clock cycle:- A regular time interval (Ex. Cycle length p)
• Clock rate (R):- Inverse of clock cycle { R = ⅟p } which is
measured in cycles per second.
• The execution of each instruction is divided into several
steps, each of which completes in one clock cycle.
• Hertz (Hz) – cycles per second
 Basic Performance
•
Equation
T – processor time required to execute a program that has
been prepared in high-level language
• N – number of actual machine language instructions needed
to complete the execution (note: loop)
• S – average number of basic steps needed to execute one
machine instruction. Each step completes in one clock cycle
• R – clock rate
 Note:- These are not independent to each other

N S
T
How to improve T ? R
Reduce N & S
Increase R
 Pipeline & Superscalar Operation
• If source program complied in fewer machine instruction
 Reduced Instruction Set Computers (RISC)
 Complex Instruction Set Computers (CISC)
• Goal – reduce N
• Instructions are not necessarily executed one after another.
• The value of S doesn’t have to be the number of clock cycles to execute one
instruction.
• Pipelining – overlapping the execution of successive instructions.
• Superscalar operation – multiple instruction pipelines are implemented in
the processor.
• Goal – reduce S
• Increase clock rate
 Improve the integrated-circuit (IC) technology to make the circuits faster
 Reduce the amount of processing done in one basic step
• Increases in R that are entirely caused by improvements in IC technology
affect all aspects of the processor’s operation equally except the time to
access the main memory.
 CISC vs. RISC Organizations

Microprogrammed
Control Unit Hardwared
Cache Control Unit
Microprogrammed
Control Memory Instruction Data
Cache Cache

Main Memory Main Memory

(a) CISC Organization (b) RISC Organization

 Compiler
• A compiler translates a high-level language program into a
sequence of machine instructions.
• To reduce N, we need a suitable machine instruction set
and a compiler that makes good use of it.
• Goal – reduce N×S
• A compiler may not be designed for a specific processor;
however, a high-quality compiler is usually designed for,
and with, a specific processor.
Multiprocessors & Multicomputer
• Multiprocessor
 Execute a number of different application tasks in parallel
 Execute subtasks of a single large task in parallel
 All processors have access to all of the memory – shared-
memory multiprocessor
 Cost – processors, memory units, complex interconnection
networks
• Multicomputer
 Each computer only have access to its own memory
 Exchange message via a communication network – message-
passing multicomputer
 UMA vs. NUMA
Computers

P1 P2 Pn P1 P2 Pn

Cache Cache Cache Cache Cache Cache

Bus
Main Main Main
Memory Memory Memory
Main
Memory

Network

(a) UMA Model (b) NUMA Model

 Memory Location, Addresses,&
Operation
• Memory consists of n bits

many millions of first word

storage cells, each second word

of which can store 1

bit data as 0/1. •
• Data is usually •
•
accessed in n-bit
i th word
groups as Word
( Where n is called
word length ). •
•
•
last word

Memory words.
Memory Location, Addresses
& Operation
• 32-bit word length example
32 bits

b 31 b 30 b1 b0

•
•
•
Sign bit: b 31= 0 for positive numbers
b 31= 1 for negative numbers

(a) A signed integer

8 bits 8 bits 8 bits 8 bits

ASCII ASCII ASCII ASCII

character character character character

(b) Four characters

Memory Location, Addresses
& Operation
• To retrieve information from memory, either for one
word or one byte (8-bit), addresses for each location are
needed.
• A k-bit address memory has 2k memory locations,
namely 0 to 2k - 1,  called as memory space.
• Example:-
• 24-bit memory: 224 = 16,777,216 = 16M (1M=220)
• 32-bit memory: 232 = 4G (1G=230)
• 1K(kilo)=210
• 1T(tera)=240
 Memory Location, Addresses &
Operation
• It is impractical to assign distinct addresses to individual bit
locations in the memory.
• The most practical assignment is to have successive
addresses refer to successive byte locations in the memory
called as  byte-addressable memory.
• Byte locations have addresses 0, 1, 2, …
• If word length is 32 bits, they successive words are located
at addresses 0, 4, 8,…, with each word consists of four
bytes.
Big-Endian & Little-Endian
Assignments
 Big-Endian & Little-Endian
Assignments
Big-Endian:- Lower byte addresses are used for the most significant bytes of the word
Little-Endian: - (opposite ordering ) Lower byte addresses are used for less significant bytes of word

Word
address Byte address Byte address

0 0 1 2 3 0 3 2 1 0

4 4 5 6 7 4 7 6 5 4

• •
• •
• •

k k k k k k k k k k
2 -4 2 -4 2 -3 2- 2 2 - 1 2 - 4 2- 1 2 - 2 2 -3 2 -4

(a) Big-endian assignment (b) Little-endian assignment

Byte and word addressing.

 Intel MultiCore Architecture
• Improving execution rate of a single-thread is still
considered important:
– Uses out-of-order execution and speculation.
• MultiCore architecture:
– Can reduce power consumption.
– (14 pipeline stages) is closer to the Pentium M (12 stages)
than the P4 (30 stages).
• Many transistors are invested in large branch predictors:
– To reduce wasted work (power).
Intel’s Dual Core Architectures
• The Pentium D is simply two Pentium 4 cpus:
– Inefficiently paired together to run as dual core.
• Core Duo is Intel's first generation dual core processor based
upon the Pentium M (a Pentium III-4 hybrid):
– Made mostly for laptops and is much more efficient than Pentium
D.
• Core 2 Duo is Intel's second generation (hence, Core 2)
processor:
– Made for desktops and laptops designed to be fast while not
consuming nearly as much power as previous CPUs.
• Intel has now dropped the Pentium name in favor of the Core
architecture.
Intel Core Processor
 Intel Core 2 Duo
• Code named
“conroe”
• Homogeneous cores
• Bus based chip
interconnect.
• Shared on-die Cache Source: Intel Corp.

Memory.
Classic OOO: Reservation Stations,
Issue ports, Schedulers…etc
Large, shared set associative,
prefetch, etc.
Core 2 Duo Microarchitecture
 Why Sharing On-Die
L2?

• What happens when L2 is too large?

 Xeon Vs. Opteron
Dual-Core Dual-Core Dual-Core Dual-Core
Dual- Dual-
Core Core

Dual-
Dual-
Core
PCI-E Core
PCI-E
Memory Bridge
Bridge
I/O Memory PCI-E
PCI-E
I/OHub
Hub Controller
Controller Bridge
Bridge
PCI-E
Hub
Hub PCI-E
Bridge
Bridge

PCI-E
PCI-E PCI-E
PCI-E
Bridge
Bridge Bridge
Bridge

XMB
XMB XMB
XMB XMB
XMB XMB
XMB

I/O
I/OHub
Hub

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