Chapter 13 Transceiver Design Example

13.1 System-Level Considerations

13.2 Receiver Design
13.3 TX Design
13.4 Synthesizer Design

Behzad Razavi, RF Microelectronics.

Prepared by Bo Wen, UCLA

Chapter Outline
System-Level
Specifications

RX NF, IP3, AGC, and I/Q

Mismatch
TX Output Power and P1dB
Synthesizer Phase Noise and
Spurs
Frequency Planning

RX Design

Broadband LNA
Passive Mixer
AGC

Synthesizer Design

VCO
Dividers
Charge Pump

Chapter13 Transceiver Design Example

TX Design

PA
Upconverter

Receiver: Noise Figure

11a/g specifies a packet error rate of 10%. Since TX baseband pulse shaping reduces the
channel bandwidth to 16.6 MHz, we return to

and obtain
for a sensitivity of -65 dBm (at 52 Mb/s).
In practice, signal detection in the digital baseband processor suffers from nonidealities,
incurring a loss of a few decibels. Moreover, the front-end antenna switch exhibits a loss
of around 1 dB.

Manufacturers typically target an RX noise figure of about 10 dB.

Chapter13 Transceiver Design Example

Receiver: Nonlinearity
We represent the desired, adjacent, and alternate
channels by A0 cos 0t, A1 cos 1t, and A2 cos 2t,
respectively. For a third-order nonlinearity of the form
y(t) = 1x(t) + 2x2(t) + 3x3(t), the desired output is given
by 1A0 cos 0t and the IM3 component at 0 by
33A12A2/4
We choose the IM3 corruption to be around
-15 dB to allow for other nonidealities:

The IP3 corresponding to the 1-dB compression point is satisfied if

compression by the desired signal is avoided. The IP3 arising from adjacent
channel specifications must be satisfied while the desired signal is only 3 dB
above the reference sensitivity.
Chapter13 Transceiver Design Example

Receiver: AGC Range

The receiver must automatically control its gain if the received signal level
varies considerably.
The challenge is to realize this gain range while maintaining a noise figure of
about 10 dB and an IIP3 of about -40 dBm.
Determine the AGC range of an 11a/g receiver so as to accommodate the ratedependent sensitivities.

Solution:
At first glance, we may say that the input signal level varies from -82 dBm to -65 dBm,
requiring a gain of 86 dB to 69 dB so as to reach 1 Vpp at the ADC input. However, a 64QAM
signal exhibits a peak-to-average ratio of about 9 dB; also, baseband pulse shaping to meet
the TX mask also creates 1 to 2 dB of additional envelope variation. Thus, an average input
level of -65 dBm in fact may occasionally approach a peak of -65 dBm+11 dB = -54 dBm. It is
desirable that the ADC digitize this peak without clipping. That is, for a -65-dBm 64QAM
input, the RX gain must be around 58 dB. The -82-dBm BPSK signal, on the other hand,
displays only 1 to 2 dB of the envelope variation, demanding an RX gain of about 84 dB.

Chapter13 Transceiver Design Example

ACG Range: Required RX Gain Switching and NF

and IIP3 Variations

The receiver gain range is also determined

by the maximum allowable desired input
level (-30dBm). The baseband ADC
preferably avoids clipping the peaks of the
waveforms.
The actual number of steps chosen here
depends on the design of the RX building
blocks and may need to be quite larger
than that depicted

Chapter13 Transceiver Design Example

Example of AGC Range: Choice of Gain

The choice of the gain in the above example guarantees that the signal level
reaches the ADC full scale for 64QAM as well as BPSK modulation. Is that
necessary?

Solution:
No, it is not. The ADC resolution is selected according to the SNR required for 64QAM
modulation (and some other factors). For example, a 10-bit ADC exhibits an SNR of about 62
dB, but a BPSK signal can tolerate a much lower SNR and hence need not reach the ADC full
scale. In other words, if the BPSK input is amplified by, say, 60 dB rather than 84 dB, then it
is digitized with 6 bits of resolution and hence with ample SNR ( 38 dB) . In other words, the
above AGC calculations are quite conservative.

Chapter13 Transceiver Design Example

Receiver: I/Q Mismatch

The I/Q mismatch study proceeds as follows.
(1) To determine the tolerable mismatch, we must apply in system simulations a 64QAM
OFDM signal to a direct-conversion receiver and measure the BER or the EVM. Such
simulations are repeated for various combinations of amplitude and phase mismatches,
yielding the acceptable performance envelope.
(2) Using circuit simulations and random device mismatch data, we must compute the
expected I/Q mismatches in the quadrature LO path and the downconversion mixers.
(3) Based on the results of the first two steps, we must decide whether the raw
matching is adequate or calibration is necessary.

A hypothetical image-reject receiver exhibits the above I/Q mismatch values.

Determine the image rejection ratio.
The gain mismatch, 2(A1 - A2)/(A1 + A2) (A1 - A2)/A1 = A/A, is obtained by raising 10 to the
power of (0.2 dB/20) and subtracting 1 from the result. Thus,

Chapter13 Transceiver Design Example

Transmitter
The transmitter chain must be linear enough to deliver a 64QAM OFDM signal
to the antenna with acceptable distortion.

High linearity:
(1)assign most of gain to last PA stage
(2)minimize the number of stages in the TX chain

An 11a/g TX employs a two-stage PA having a gain of 15 dB. Can a quadrature

upconverter directly drive this PA?
The output P1dB of the upconverter must exceed +24 dBm - 15 dB = +9 dBm = 1.78 Vpp. It is
difficult to achieve such a high P1dB at the output of typical mixers. A more practical approach
therefore attempts to raise the PA gain or interposes another gain stage between the
upconverter and the PA.
Chapter13 Transceiver Design Example

Frequency Synthesizer: Example of Reciprocal

Mixing ()
For the dual-band transceiver developed in this chapter, the synthesizer must
cover the 2.4-GHz and 5-GHz bands with a channel spacing of 20 MHz. In
addition, the synthesizer must achieve acceptable phase noise and spur levels.

Determine the required synthesizer phase noise for an 11a receiver such that
reciprocal mixing is negligible.

Solution:
We consider the high-sensitivity case, with the desired input at -82 dBm + 3 dB and the
adjacent and alternate channels at +16 dB and +32 dB, respectively. Figure below shows the
corresponding spectrum but with the adjacent channels modeled as narrow-band blockers
to simplify the analysis. Upon mixing with the LO, the three components emerge in the
baseband, with the phase noise skirts of the adjacent channels corrupting the desired
signal. Since the synthesizer loop bandwidth is likely to be much smaller than 20 MHz, we
can approximate the phase noise skirts by S(f) = /f2. Our objective is to determine .

Chapter13 Transceiver Design Example

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Frequency Synthesizer: Example of Reciprocal

Mixing()
If a blocker has a power that is a times the desired signal power, Psig , then the phase noise
power, PPN, between frequency offsets of f1 and f2 and normalized to Psig is given by

In the scenario of figure below, the total noise-to-signal ratio is equal to

where a1 = 39.8 (= 16 dB), f1 = 10 MHz, f2 =

30 MHz, a2 = 1585 (= 32 dB), f3 = 30 MHz, f4
= 50 MHz. We wish to ensure that
reciprocal mixing negligibly corrupts the
signal:

Chapter13 Transceiver Design Example

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Frequency Synthesizer Phase Noise

In the absence of reciprocal mixing, the synthesizer phase noise still corrupts
the signal constellation. For this effect to be negligible in 11a/g, the total
integrated phase noise must remain less than 1
Denoting the value of /(f - fc)2 at f = fc f1 by S0, we have = S0f12 and:

Chapter13 Transceiver Design Example

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Effect of reducing PLL bandwidth on phase noise

A student reasons that a greater free-running phase noise, S0, can be tolerated if
the synthesizer loop bandwidth is reduced. Thus, f1 must be minimized. Explain
the flaw in this argument.
Consider two scenarios with VCO phase noise profiles given by 1/f2 and 2/f2. Suppose the
loop bandwidth is reduced from f1 to f1/2 and S0 is allowed to rise to 2S0 so as to maintain P
constant.
In the former case,

And hence 1=f12S0. In the latter case,

and hence 2 = 0.5f12S0. It follows that the latter case demands a lower free-running phase
noise at an offset of f1, making the VCO design more difficult.
Chapter13 Transceiver Design Example

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Synthesizer Output Spurs

For an input level of -82 dBm+3 dB = -79 dBm, spurs in the middle of the
adjacent and alternate channels downconvert blockers that are 16 dB and 32
dB higher, respectively.
The spurs also impact the transmitted signal. To estimate the tolerable spur
level, we return to the 1 phase error mentioned above (for random phase
noise) and force the same requirement upon the effect of the (FM) spurs.
only with phase noise, n(t)
and only with a small FM spur:

For the total rms phase deviation to be less than 1 = 0:0175 rad, we have

The relative sideband level in xTX2(t) is equal to KVCOam/(2m) = 0:0124 = -38 dBc.
Chapter13 Transceiver Design Example

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Example of Spurs
A quadrature upconverter designed to generate a(t) cos[ct + (t)] is driven by an
LO having FM spurs. Determine the output spectrum.
Representing the quadrature LO phases by cos[ct + (KVCOam/m) cos mt ] and sin[ct +
(KVCOam/m) cosmt ], we write the upconverter output as

We assume KVCOam/m << 1 rad and expand the terms:

The output thus contains the desirable component and

the quadrature of the desirable component shifted to
center frequencies of c - m and c + m. The key
point here is that the synthesizer spurs are modulated
as they emerge in the TX path.
Chapter13 Transceiver Design Example

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Frequency Planning ()

Two separate quadrature VCOs for the to bands, with their outputs multiplexed
and applied to the feedback divider chain.
Floor plan imposes a large spacing between the 11a and 11g signal paths.
11a VCO must provide a tuning range of 15%. LO pulling proves serious.
Chapter13 Transceiver Design Example

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Frequency Planning ()
One quadrature VCO serving both
bands.
More compact floor plan.
LO pulling persists. It is desirable
to implement the 11g PA in fullydifferential form.

One differential VCO operating

from 2 4.8 GHz to 2 5.9 GHz
Compact floor plan.
A tuning range of 21%
Differential 11a and 11g PAs
A 2 circuit that robustly operates
up to 12GHz, preferably with no
inductors.
Chapter13 Transceiver Design Example

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Frequency Planning ()

We employ two VCOs, each with about half the tuning range but with some
overlap to avoid a blind zone.
A larger number of VCOs can be utilized to allow an even narrower tuning
range for each, but the necessary additional inductors complicate the routing.
Chapter13 Transceiver Design Example

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Examples of Floor Planning

Explain why the outputs of the two 2 circuits in the previous architecture with a
VCO and a divider for the two bands are multiplexed. That is, why not apply the
fVCO=4 output to the N stage in the 11a mode as well?
Driving the N stage by fVCO=4 is indeed desirable as it eases the design of this circuit.
However, in an integer-N architecture, this choice calls for a reference frequency of 10MHz
rather than 20MHz in the 11a mode, leading to a smaller loop bandwidth and less
suppression of the VCO phase noise.

The MUX following the two VCOs in the above architecture with two VCOs must
either consume a high power or employ inductors. Is it possible to follow each
VCO by a 2 circuit and perform the multiplexing at the dividers outputs?
The two multiplexers do introduce additional I/Q mismatch, but calibration removes this
error along with other blocks
contributions. Note that the new 2
circuit does not raise the power
consumption because it is turned
off along with VCO2 when not
needed.
Chapter13 Transceiver Design Example

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How Synthesizer is Shared Between the TX and RX

Path?

The synthesizer outputs directly drive both paths.

In practice, buffers may be necessary before and after the long wires.
Chapter13 Transceiver Design Example

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Example of I/Q Mismatches after Long Interconnects

Differential I and Q signals experience deterministic mismatches as they travel on
long interconnects. Explain why and devise a method of suppressing this effect.
Consider the arrangement shown in (a). Owing to the finite resistance and coupling
capacitance of the wires, each line experiences an additive fraction of the signal(s) on its
immediate neighbor(s) (b). Thus, I and Q depart from their ideal orientations. To suppress
this effect, we rearrange the wires as shown in (c) at half of the distance between the end
points, creating a different set of couplings. Illustrated in (d) are all of the couplings among
the wires, revealing complete cancellation.

(a)

Chapter13 Transceiver Design Example

(b)

(c)

(d) 21

Receiver Design: LNA Design ()

Is it possible to employ only one LNA for the two bands?

Equating Rin to RS and making a substitution

in the denominator, we have

Suppose (gm1 + gm2)(rO1||rO2) >> 1.

First term should be on the order of 10 to 20 , and the second, 30 to 40 . And we can
compute the gain equals -2.8.
Chapter13 Transceiver Design Example

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Receiver Design: LNA Design ()

Modified to have a higher gain:

the input resistance is given by the feedback resistance divided by one plus the loop gain:

If Rin = RS and RM >> gm3-1, then the gain is simply equal to 1/2 times the voltage gain of the
inverter:
Chapter13 Transceiver Design Example

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Example of Input Capacitance of LNA

The large input transistors in the previous figure present an input capacitance, Cin,
of about 200 fF (including the Miller effect of CGD1 + CGD2). Does this capacitance
not degrade the input match at 6 GHz?
Since (Cin)-1 130 is comparable with 50 , we expect Cin to affect S11 considerably.
Fortunately, however, the capacitance at the output node of the inverter creates a pole that
drops the open-loop gain at high frequencies, thus raising the closed-loop input impedance.

Shown here is the LNA gain as a function of the

input level at 6 GHz. By virtue of the feedback,
the LNA achieves a P1dB of about -14 dBm.

Chapter13 Transceiver Design Example

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Simulated Characteristics of 11a/g LNA

The worst-case |S11|, NF, and gain are equal to -16.5 dB, 2.35 dB, and 14.9 dB,
respectively.
Chapter13 Transceiver Design Example

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Mixer Design
In this transceiver design, we have some flexibility because (a) 65-nm CMOS technology can
provide rail-to-rail LO swings at 6 GHz, allowing passive mixers, and (b) the RX linearity is
relatively relaxed, allowing active mixers.

Transistors M3 and M4 present a load capacitance of CL (2/3)WLCox 130 fF to the mixer

devices. The differential noise measured between A and B is thus given by

Chapter13 Transceiver Design Example

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Simulated NF of the Mixer

Figure below plots the simulated double-sideband noise figure of the mixer of figure above
with respect to a 50- source impedance

For a 6-GHz LO, the NF is dominated by the flicker noise of the baseband amplifier at 100kHz offset. For a 2.4-GHz LO, the thermal noise floor rises by 3 dB. The simulations assume
a rail-to-rail sinusoidal LO waveform.
Chapter13 Transceiver Design Example

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Overall 11a/g Receiver Design

We finally arrive at the overall receiver design shown below:

Chapter13 Transceiver Design Example

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Simulated NF of the Overall Receiver

The RX noise figure varies from 7.5 dB to 6.1 dB at 2.4 GHz and from 7 dB to
4.5 dB at 6 GHz. These values are well within our target of 10 dB.

Chapter13 Transceiver Design Example

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Examples of Issues in Mixer Design

How is the receiver sensitivity calculated if the noise figure varies with the
frequency?
A simple method is to translate the NF plot to an output noise spectral density plot and
compute the total output noise power in the channel bandwidth (10 MHz). In such an
approach, the flicker noise depicted in above simulation contributes only slightly because
most of its energy is carried between 100 kHz and 1 MHz. In an OFDM system, on the other
hand, the flicker noise corrupts some subchannels to a much greater extent than other
subchannels. Thus, system simulations with the actual noise spectrum may be necessary.

The input impedance, Zmix, in previous mixer may alter the feedback LNA input
return loss. How is this effect quantified?
The LNA S11 is obtained using small-signal ac simulations. On the other hand, the input
impedance of passive mixers must be determined with the transistors switching, i.e., using
transient simulations. To study the LNA input impedance while the mixers are switched, the
FFT of Iin can be taken and its magnitude and phase plotted. With the amplitude and phase of
Vin known, the input impedance can be calculated at the frequency of interest.
Chapter13 Transceiver Design Example

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Coarse AGC

Dominated by the baseband

differential pair, the RX P1dB is quite
lower than that of the LNA. It is
therefore desirable to lower the mixer
gain as the average RX input level
approaches -30 dBm

This is accomplished by
inserting transistors MG1- MG3
between the differential outputs
of the mixer.

Chapter13 Transceiver Design Example

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Coarse AGC: Gain Settings

Owing to their small dimensions, MG1-MG3 suffer from large threshold

variations. It is therefore preferable to increase both the width and length of
each device by a factor of 2 to 5 while maintaining the desired on-resistance.
The characteristics above indicate that the RX P1dB hardly exceeds -18 dBm
even as the gain is lowered further.
Chapter13 Transceiver Design Example

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Examples of AGC
What controls D1-D3?
The digital control for D1-D3 is typically generated by the baseband processor. Measuring the
signal level digitized by the baseband ADC, the processor determines how much attenuation
is necessary.

What gain steps are required for the fine AGC?

The fine gain step size trades with the baseband ADC resolution. To understand this point,
consider the example shown in figure below, where the gain changes by h dB for every 10dB change in the input level. Thus, as the input level goes from, say, -39.9 dBm to -30.1 dBm,
the gain is constant and hence the ADC input rises by 10 dB. The ADC must therefore (a)
digitize the signal with proper resolution when the input is around -39.9 dBm, and (b)
accommodate the signal without clipping when the input is around -30.1 dBm.
Now consider the gain
switching occurs for every
5-dB change in the input
level. In this case, the ADC
must provide 5 dB of
additional resolution
(dynamic range).
Chapter13 Transceiver Design Example

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Example of AGCs Linear-in-dB Gain

In AGC design, we seek a programmable gain that is linear in dB, i.e., for each
LSB increase in the digital control, the gain changes by h dB and h is constant.
Explain why.
The baseband ADC and digital processor measure the signal amplitude and adjust the digital
gain control. Let us consider two scenarios for the gain adjustment as a function of the
signal level. As shown below, in the first scenario the (numerical) gain is reduced by a
constant (numerical) amount (10) for a constant increase in the input amplitude (5 mV). In
this case, the voltage swing sensed by the ADC (= input level RX gain) is not constant,
requiring nearly doubling the ADC dynamic range as the input varies from 10 mVp to 30 mVp.

In the second scenario, the RX gain is reduced by a constant amount in dB for a constant
logarithmic increase in the signal level, thereby keeping the ADC input swing constant. Here,
for every 5 dB rise in the RX input, the baseband processor changes the digital control by 1
LSB, lowering the gain by 5 dB. It is therefore necessary to realize a linear-in-dB gain control
mechanism.
Chapter13 Transceiver Design Example

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Fine AGC

The gain is reduced by raising the degeneration resistance.

In the circuit above (left), the nonlinearity of MG1-MGn may manifest itself for
large input swings.
Chapter13 Transceiver Design Example

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Simulated RX Performance with VGA

We observe that (a) the RX P1dB drops from -26 dBm to -31 dBm when the VGA
is added to the chain, and (b) the noise figure rises by 0.2 dB in the low-gain
mode. The VGA design thus favors the NF at the cost of P 1dBwhile providing a
maximum gain of 8 dB.
A student seeking a higher P1dB notes that the NF penalty for D1D2D3D4 = 0011 is
negligible and decides to call this setting the high-gain mode. That is, the
student simply omits the higher gain settings for 0000 and 0001. Explain the issue
here.
In the high-gain mode, the VGA provides a gain of only 4 dB. Consequently, the noise of
the next stage (e.g., the baseband filter) may become significant.
Chapter13 Transceiver Design Example

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TX Design: PA Design
The PA must deliver +16 dBm (40 mW) with an output P1dB of +24 dBm. The corresponding
peak-to-peak voltage swings across a 50- antenna are 4 V and 10 V, respectively. We
assume an off-chip 1-to-2 balun and design a differential PA that provides a peak-to-peak
swing of 2 V, albeit to a load resistance of 50 /22 = 12.5

What P1dB is necessary at node X (or Y ) in figure above?

The balun lowers the P1dB from +24 dBm (10 Vpp) across the antenna to 5 Vpp for VXY . Thus,
the P1dB at X can be 2.5 Vpp (equivalent to +12 dBm).
The interesting (but troublesome) issue here is that the PA supply voltage must be high
enough to support a single-ended P1dB of 2.5 Vpp even though the actual swings rarely reach
this level.
Chapter13 Transceiver Design Example

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Quasi-Differential Cascode Stage

The choice of Vb is
governed by a tradeoff between linearity
and device stress.
The circuit must reach
compression first at
the output rather than
at the input.
The gain of the above
stage must be
maximized.
Study the feasibility of the above design for a voltage gain of (a) 6 dB, or (b) 12 dB
With a voltage gain of 6 dB, as the circuit approaches P1dB, the single-ended input peak-topeak swing reaches 2.5 V/2 = 1.25 V!! This value is much too large for the input transistors,
leading to a high nonlinearity. For a voltage gain of 12 dB, the necessary peak-to-peak input
swing near P1dB is equal to 0.613 V, a more reasonable value. Of course, the input transistors
must now provide a transconductance of gm = 4/(6:25 ) = (1.56 )-1, thus demanding a very
large width and a high bias current.
Chapter13 Transceiver Design Example

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Internal Node Voltage Waveforms/Compression

Characteristic and Drain Efficiency
The design meets two criteria:
(1) the gain falls by no more than 1 dB
when the voltage swing at X (or Y )
reaches 2.5 Vpp
(2) the transistors are not stressed for the
average output swing, 1 Vpp at X (or Y ).

Chapter13 Transceiver Design Example

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Predriver
The input capacitance of the PA is about 650 fF, requiring a driving inductance of about 1 nH
for resonance at 6 GHz. With a Q of 8, such an inductor exhibits a parallel resistance of
300. The predriver must therefore have a bias current of at least 2.3 mA so as to generate a
peak-to-peak voltage swing of 0.68 V. However, for the predriver not to degrade the TX
linearity, its bias current must be quite higher.

Designed for resonance at 6 GHz with a Q of 8, the predriver suffers from a low
gain at 5 GHz.
Chapter13 Transceiver Design Example

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Example of AC Coupling Between Predriver and

Output Stage
A student decides to use ac coupling between the predriver and the PA so as to
define the bias current of the output transistors by a current mirror. Explain the
issues here.
Figure below depicts such an arrangement. To minimize the attenuation of the signal, the
value of Cc must be about 5 to 10 times the PA input capacitance, e.g., in the range of 3 to 6
pF. With a 5% parasitic capacitance to ground, Cp, this capacitor presents an additional load
capacitance of 150 to 300 fF to the predriver, requiring a smaller driving inductance. More
importantly, two coupling capacitors of this value occupy a large area.

Chapter13 Transceiver Design Example

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Common-Mode Stability
Quasi-differential PAs exhibit a higher common-mode gain than differential gain, possibly
suffering from CM instability.

The circuit above (left) is generally stable from the stand point of differential
signals because the 25- resistance seen by each transistor dominates the
load, avoiding a negative resistance at the gate.
For CM signals, on the other hand, the circuit above (left) collapses to above
(right). The 50- resistor vanishes, leaving behind an inductively-loaded
common-source stage, which can exhibit a negative input resistance. To
ensure stability, a positive common-mode resistance must drive this stage.
Chapter13 Transceiver Design Example

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Lossy Network Used to Avoid CM Instability

We provide the cascode gate bias through a lossy network. Here, we generate
Vb by means of a simple resistive divider, but, to dampen resonances due to LB
and LG, we also add R1 and R2.
Chapter13 Transceiver Design Example

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Upconverter
The upconverter must translate the baseband I and Q signals to a 6-GHz center frequency
while driving the 40-m input transistors of the predriver.

Since the gate bias voltage of M5-M8 is around 0.6 V, the mixer transistors
suffer from a small overdrive voltage if the LO swing reaches only 1.2 V.
We must therefore use ac coupling between the mixers and the predriver.
Chapter13 Transceiver Design Example

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Problem of Large Beat Swing at Gate of V/I

Converter Transistors
Each passive mixer generates a double-sideband output, making it more difficult to
achieve the output P1dB required of the TX chain.

The TX is tested with a single baseband tone (rather than a modulated signal).
The gate voltage of M5 thus exhibits a beat behavior with a large swing,
possibly driving M5 into the triode region.
We wish to sum the signals before they reach the predriver.
Chapter13 Transceiver Design Example

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Final TX Design

The mixer outputs are shorted to generate a single-sideband signal and avoid
the beat behavior described above. This summation is possible owing to the
finite on-resistance of the mixer switches.

Chapter13 Transceiver Design Example

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TX Compression Characteristic

We define the conversion gain as the differential voltage swing delivered to the
50- load divided by the differential voltage swing of xBB,I(t) [or xBB,Q(t)].
The TX reaches its output P1dB at VBB,pp = 890 mV, at which point it delivers an
output power of +24 dBm. The average output power of +16 dBm is obtained
with VBB,pp 350 mV.
Chapter13 Transceiver Design Example

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Synthesizer Design: VCO Design ()---Preliminary 12

GHz VCO
We choose the tuning range of the VCOs as follows. One VCO, VCO1, operates from 9.6 GHz
to 11 GHz, and the other, VCO2, from 10.8 GHz to 12 GHz. We begin with VCO2

Assume a single-ended load inductance of 0.75 nH, Q = 10. Yielding a singleended peak-to-peak output swing of 1.2 V. We choose a width of 10 m for
cross-coupled transistors. Finally we add enough constant capacitance to
obtain an oscillation frequency of about 12 GHz.
Chapter13 Transceiver Design Example

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Synthesizer Design: VCO Design ()---Simulation

Result of Preliminary Design
We wish to briefly simulate the performance of the circuit before adding the tuning
devices.

Simulations suggest a single-ended peak-to-peak swing of about 1.2 V. Also,

the phase noise at 1-MHz offset is around -109 dBc/Hz, well below the required
value. The design is thus far promising.
However, the phase noise is sensitive to the tail capacitance.
Chapter13 Transceiver Design Example

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Synthesizer Design: VCO Design ()---Add

Capacitance for Tuning
Now, we add a switched capacitance of 90 fF to each side so as to discretely tune the
frequency from 12 GHz to 10.8 GHz.

The size of the switches in series with

the 90-fF capacitors must be chosen
according to the trade-off between their
parasitic capacitance in the off state and
their channel resistance in the on state.
A helpful observation in simulations is
that the voltage swing decreases
considerably if the on-resistance is not
sufficiently small.
Simulations indicate that the frequency
can be tuned from 12.4 GHz to 10.8 GHz
but the single-ended swings fall to about
0.8 V at the lower end. To remedy the
situation, we raise the tail current to
2mA.
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Synthesizer Design: VCO Design ()---Add

Varactors
In the next step, we add varactors to the VCO and decompose the switched capacitors into
smaller units, thus creating a set of discretely-spaced continuous tuning curves with some
overlap.

This step of the design demands some iteration in

the choice of the varactors size and the number
and values of the unit capacitors.
We still have floating switches even though they
are not shown.
To obtain a wide continuous tuning range, the
gate of the varactor is capacitively coupled to the
core and biased at Vb 0.6 V.
Chapter13 Transceiver Design Example

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Synthesizer Design: VCO Design ()---Tuning

Characteristics and Phase Noise
Figure below shows VCOs tuning characteristics obtained from simulations and phase
noise with all of the capacitors switched into the tank.

The control can operate properly across this range. We note that KVCO varies
from about 200 MHz/V to 300 MHz/V.

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Synthesizer Design: VCO Design ()---Replace Ideal

Tail Current with Current Mirror
In the last step of our VCO design, we replace the ideal tail current source with a current
mirror.

This arrangement incorporates a channel length of 0.12 m to improve the

matching between the two transistors in the presence of a VDS difference. The
width of MSS is chosen so as to create a small overdrive voltage, allowing the
VGS to be approximately equal to VDS ( 500 mV).

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Synthesizer Design: VCO Design ()---Raised

Phase Noise
The current mirror drastically raises the phase noise of the VCO, from -111 dBc/Hz to -100
dBc/Hz at 10.8 GHz and from-109 dBc/Hz to-98 dBc/Hz at 12.4 GHz (both at 1-MHz offset)

Most of the phase noise now arises from the thermal and flicker noise of MREF
and MSS.
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Synthesizer Design: VCO Design ()---Modification

to Suppress the Noise
A simple modification can suppress the contribution of MREF . As shown above, we insert a
low-pass filter between the two transistors, suppressing the noise of MREF (and IREF ).

To obtain a corner frequency well below 1 MHz:

(1) bias MS with a small overdrive voltage, which is provided by the wide
diode-connected transistor Mb;
(2) select a width of 0.2 m and a length of 10 m for MS;
(3) choose a value of 5 pF for Cb.
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Effect of Rb Thermal Noise ()

A student reasons that, since the thermal noise of Rb in the previous topology,
where switched-capacitor array is added to VCO, modulates the varactor voltage,
the value of Rb must be minimized. Is this reasoning correct?
Resistor Rb has two effects on the VCO: it lowers the Q of the tank and its noise modulates
the frequency.

Consider the simplified circuit shown above, where L/2, Rp/2, and CT represent the singleended equivalent of the tank (including the transistor capacitances and the switched
capacitors). We know that Cc and Cvar transform Rb to a value given by

where the Q associated with this network is assumed greater than about 3. For Cc 10Cvar,
we have Req 1.2Rb. Thus, Rb must be roughly 10 times Rp/2 to negligibly reduce the tank Q.
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Effect of Rb Thermal Noise ()

But, can we use a very small Rb? In that case, the above expression for Req does not apply
because the Q associated with Cc, Cvar, and Rb is small. We must employ a large value for Rb.
The output phase noise of the VCO due to noise on the control voltage can be expressed as

For offset frequencies below -3dB 1/(RbCc), the noise of Rb directly modulates the varactor,
as if it were in series with Vcont . We make the following observations: (1) the gain from each
resistor noise voltage to the output frequency is equal to KVCO/2, where KVCO denotes the gain
from Vcont ; (2) a two-sided thermal noise spectrum of 2kTRb yields a phase noise spectrum
around zero frequency given by Sn = 2kTRb(KVCO/2)2/2; (3) for an RF output of the form
Acos(ct + n), the relative phase noise around the carrier is still given by Sn; (4) the phase
noise power must be doubled to account for the two Rbs. The output phase noise is equal to

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Example of VCO and Capacitors in Synthesizer Loop

How does the synthesizer loop decide which VCO to use and how many
capacitors to switch into the tank?
The synthesizer begins with, say, VCO2 and all capacitors included in the tank. The control
voltage, Vcont, is monitored by a simple analog comparator . If Vcont exceeds, say, 1.1 V, and
the loop does not lock, then the present setting cannot achieve the necessary frequency.
One capacitor is then switched out of the loop and the loop is released again. This
procedure is repeated (possibly switching to VCO1 if VCO2 runs out of steam) until lock is
obtained for Vcont 1.1 V.

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Multiplexing Two VCOs

The outputs of the two VCOs must be multiplexed. With rail-to-rail swings available, simple
inverters can serve this purpose.

Each inverter is sized according to an estimated fanout necessary to drive the

subsequent divide-by-2 circuit.
The VCO outputs have a CM level equal to VDD and are therefore capacitively
coupled to the MUX.
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Divider Design: Divide-by-2 Circuit

The multiplexed VCO outputs must be divided by two so as to generate quadrature outputs.
With rail-to-rail swings available at the MUX output, we seek a simple and efficient topology.

This topology employs dynamic logic; leakage currents eventually destroy the
stored state if CK is low for a long time.
The latch is based on ratioed logic, requiring careful sizing.

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Below-Ground Swings at the Latch Output

The latch of above topology produces a low level below ground. Explain why.
Suppose the clock has gone high and X and Y have reached ground and VDD, respectively.
Now, the clock falls and is coupled through CGD5 to P, drawing a current from M1 and hence
X. Thus, VX falls. If M5 is a wide device to draw a large initial current, then this effect is more
pronounced.

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Divide-by-2 Circuit: Driving a Large Load

Capacitance
As with other latches, the above circuit may fail if loaded by a large load capacitance. For
this reason, we immediately follow each latch in the divide-by-2 circuit by inverters.

The inverters present a small load to the latch but must drive a large
capacitance themselves, thereby producing slow edges.
Frequency dividers typically demand a conservative design because:
(1) the layout parasitics tend to lower the speed considerably
(2) in the presence of process and temperature variations, the divider must
handle the maximum frequency arriving from the VCO
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Dual-Modulus Divider
The pulse-swallow counter necessary for the synthesizer requires a prescaler, which itself
employs a dual-modulus divider. Such a divider must operate up to about 6.5 GHz.

The Chang-Park-Kim flipflop shown in

(a) provides only a Q output. We
modify it to that shown in (b), where
FF1 is preceded by an inverter.
We also wish to merge the AND gate
with the second flipflop so as to
improve the speed (c)

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3/4 Circuit
We must now add an OR gate to the above topology to obtain a 3/4 circuit. Again, we prefer
to merge this gate with either of the flipflops.

The modulus control OR gate is embedded within the AND structure.

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3/4 Circuit: Simulation Result

A student observes that the circuit above presents a total transistor width of 6 m
to the clock. The student then decides to halve the width of all of the transistors,
thus halving both the clock input capacitance and the power consumption.
Describe the pros and cons of this approach.
This linear scaling indeed improves the performance. In fact, if the load seen by the main
output could also be scaled proportionally, then the maximum operation speed would also
remain unchanged.
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Loop Design
The CP and LPF are designed based on the lowest value of KVCO and the highest value of the
divide ratio, M.
We begin with a loop bandwidth of 500 kHz and a charge pump current of 1 mA. Thus,
2.5n = 2(500 kHz) and hence n = 2(200 kHz). We have

We instead choose Ip = 2 mA and C1 = 27 pF, trading area for power consumption. Setting the
damping factor to unity,
For the charge pump, we return to the gate-switched topology as it affords the maximum
voltage headroom.

The gate-switched
topology still proves
rather slow, primarily
because of the small
overdrive of M3 and M4

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Simulated I/V Characteristic of the Charge Pump

In this test the Up and Down inputs are both asserted and a voltage source tied
between the output node and ground is varied from Vmin (= 0.1V) to Vmax (1.1 V).
Ideally equal to zero, the maximum current flowing through this voltage source
reveals the deterministic mismatch between the Up and Down currents and the
ripple resulting therefrom.
In this design, the maximum mismatch occurs at Vout = 1.1 V and is equal to 60
A, about 3%.
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Loop Simulation: Time Contraction

We wish to scale down the lock time of the loop by a large factor, e.g., K = 100.
To this end, we raise fREF by a factor of K and reduce C1, C2, and M by a factor of
K.
Note that time contraction does not scale R1, Ip, or KVCO, and it retains the value
of while scaling down the loop time constant, (n)-1 = 4M/(R1IpKVCO), by a
factor of K.
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Loop Simulation: Behavioral Model

In addition to time contraction, we also employ a behavioral model for the VCO with the
same value of KVCO and fout

The PFD, the CP, and the loop filter incorporate actual devices, thus producing
a realistic ripple. The loop locks in about 150 ns, incurring a peak-to-peak
ripple of nearly 30 mV.
We observe that our choice of the loop parameters has yielded a well-behaved
lock response. This simulation takes about 40 seconds.
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Example of Time Contraction on Voltage Ripple

How is the control voltage ripple scaled with time contraction scaling?
Since both C1 and C2 are scaled down by a factor of K while the PFD/CP design does not
change, the ripple amplitude rises by a factor of K in the time-contracted loop.

Given that the amplitude falls 100-fold in the unscaled loop, we must determine whether the
resulting sidebands at 5-MHz offset have a sufficiently small magnitude.
The ripple can be approximated by a train of impulses. In fact, if the area under the ripple is
given by, e.g., V0T, then the relative magnitude of the sidebands is equal to:

V0TKVCO/(2)
The area under the ripple scaled down by a factor of 100 and multiplied by KVCO/(2) yielding
a relative sideband magnitude of -64.4 dBc at the output of the 12-GHz VCO. Thus, the 6-GHz
carrier exhibits a sideband around -70 dBc, an acceptable value.
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References ()

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References ()

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