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STA_Assignment_1

STA Assignment

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sakethvarma239
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© © All Rights Reserved
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62 views

STA_Assignment_1

STA Assignment

Uploaded by

sakethvarma239
Copyright
© © All Rights Reserved
Available Formats
Download as PDF, TXT or read online on Scribd
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Assignment on setup and hold

1. Compute the setup slack and hold slack for the following design

D Q Combo D Q
logic
FF FF
1 2

Clk

Specification
Clock period = 6ns
Tclk-q(max) = 1ns
Tclk-q(min) = 0.8ns
Tcombo(max) = 3ns
Tcombo(min) = 1.8ns
Tsetup/Thold = 0.2ns
2
2. Compute the setup slack and hold slack for the following design

D Q Combo D Q
logic
FF FF
1 2

Clk

Specification
Clock period = 10ns
Tclk-q(max) = 1.2ns
Tclk-q(min) = 0.5ns
Tcombo(max) = 2ns
Tcombo(min) = 1.1ns
Tsetup/Thold = 0.3ns
3
3. Compute the setup slack and hold slack for the following design

D Q Combo D Q
logic
FF FF
1 2

Clk

Specification
Clock period = 10ns
Tclk-q(max) = 0.9ns
Tclk-q(min) = 0.7ns
Tcombo(max) = 1.1ns
Tcombo(min) = 0.4ns
Tsetup/Thold = 0.3ns
4
4. Compute the setup slack and hold slack for the following design

D Q Combo D Q
logic
FF FF
1 2

Clk

Specification
Clock period = 10ns
Tclk-q(max) = 1.1ns
Tclk-q(min) = 0.7ns
Tcombo(max) = 1.0ns
Tcombo(min) = 0.8ns
Tsetup/Thold = 0.4ns
5
5.Find the maximum frequency in the following circuit

D Q Combo D Q
logic
FF FF
1 2

Clk

Specification
Tclk-q(max) = 1.5ns
Tclk-q(min) = 1.1ns
Tcombo(max) = 2ns
Tcombo(min) = 1.7ns
Tsetup/Thold = 0.1ns

6
6. Compute the setup slack and hold slack for the following design
Buf1
Inv1
D Q D Q

FF1 FF2

Buf1
Clk

Specification
Clock period = 10ns
Delay of Buf1, max = 0.7ns
Delay of Buf1, min = 0.3ns
Delay of Buf2, max = 0.8ns
Delay of Buf2, min = 0.2ns
Delay of Inv1, max = 0.7ns
Delay of Inv1, min = 0.3ns
Tclk-q(max) = 1.2ns
Tclk-q(min)
7 = 0.5ns
Tsetup/Thold = 0.1ns
7. Compute the setup slack and hold slack for the following design
Buf 3
Inv1
D Q D Q

FF1 FF2

Buf 2
Buf1 Buf 4
Clk

Specification

Clock period = 4ns


Delay of Inv1, max = 0.07ns
Delay of Buf1, max = 0.1ns Delay of Buf3, max = 0.05ns
Delay of Inv1, min = 0.03ns
Delay of Buf1, min = 0.03ns Delay of Bu3, min = 0.03ns
Tclk-q(max) = 0.2ns
Delay of Buf2, max = 0.04ns Delay of Buf4, max = 0.08ns
Tclk-q(min) = 0.05ns
Delay of Buf2, min = 0.01ns Delay of Buf4, min = 0.02ns
Tsetup/Thold = 0.1ns

8
8. Compute the setup slack and hold slack for the
following design
Inv 1 Inv 2

D Q D Q

FF1 FF2

Buf 2
Buf1 Buf 3

Specification

Clock period = 8ns Delay of INV 1, max = 0.05ns


Delay of Buf1, max = 0.02ns Delay of INV 1, min = 0.02ns
Delay of Buf1, min = 0.01ns Delay of INV 2, max = 0.07ns
Delay of Buf2, max = 0.04ns Delay of INV 2, min = 0.04ns
Delay of Buf2, min = 0.03ns Tclk-q(max) = 0.2ns
9
Delay of Buf3, max = 0.07ns Tclk-q(min) = 0.05ns
Delay of Buf3, min = 0.03ns Tsetup/Thold = 0.1ns

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