Savitribai Phule Pune University

Savitribai Phule Pune University

Second Year of Computer Engineering (2019 Course) (With effect from Academic Year 2020-21)
Semester-III
Course Teaching Scheme Examination Scheme and Marks
Code Course Name (Hours/Week) Credit

Mid-Sem

End-Sem
Tutorial
Practical
Theory

Total

Total
TUT
TW

OR

TH
PR

PR
210241 Discrete Mathematics 03 - 01 30 70 - - - 100 03 -- 01 04
210242 Fundamentals of Data 03 - - 30 70 - - - 100 03 - - 03
Structures
210243 Object Oriented 03 - - 30 70 - - - 100 03 - - 03
Programming
210244 Computer Graphics 03 - - 30 70 - - - 100 03 - - 03
210245 Digital Electronics and 03 - - 30 70 - - - 100 03 - - 03
Logic Design
210246 Humanity and Social - - 01 - - - - - - - - - -
Science
210247 Data Structures Lab - 04 - - - 25 50 - 75 - 02 - 02
210248 OOP and Computer - 04 - - - 25 50 - 75 - 02 - 02
Graphics Lab
210249 Digital Electronics Lab - 02 - - - 25 - - 25 - 01 - 01
210250 Business Communication - 02 - - - 25 - - 25 - 01 - 01
Skills Lab
210251 Audit Course 3 - - - - -- - -- - - - -
Total Credit 15 06 01 22
Total . 15 12 02 150 350 100 100 - 700 - - - -
Semester-IV
Course Teaching Scheme Examination Scheme and Marks
Code Course Name (Hours/Week) Credit
Mid-Sem

End-Sem
Tutorial
Practical
Theory

Total

Total
TUT
TW

OR

TH
PR

PR

210252 Mathematics III 03 - 01 30 70 - - - 100 03 -- 01 04

210253 Data Structures and 03 - - 30 70 - - - 100 03 - - 03
Algorithms
210254 Software Engineering 03 - - 30 70 - - - 100 03 - - 03
210255 Microprocessor 03 - - 30 70 - - - 100 03 - - 03
210256 Principles of Programming 03 - - 30 70 - - - 100 03 - - 03
Languages
210257 Data Structures and - 04 - - - 25 50 - 75 - 02 - 02
Algorithms Lab
210258 Microprocessor Lab - 04 - - -- 75 25 50 - 02 - 02
210259 Code of Conduct - - 01 - -- - - - - - - -
210260 Project Based Learning - 04 - - -- 50 50 - - 02 - 02
210261 Audit Course 4 - - - - -- - - - - - - -
Total Credit 15 06 01 22
Total . 15 12 02 150 350 100 100 - 700 - - - -

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SE (Computer Engineering) syllabus (2019 Course)
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Savitribai Phule Pune University

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Second Year of Computer Engineering (2019 Course)
210245: Digital Electronics and Logic Design
Teaching Scheme: Credit Examination Scheme:
TH: 03 Hours/Week 03 Mid_Semester(TH): 30 Marks
End_Semester(TH): 70 Marks
Prerequisite Courses, if any: 104010 Basic Electronics Engineering
Companion Course, if any: 210249 Digital Electronics Lab
Course Objectives:
 To study number systems and develop skills for design and implementation of combinational
logic circuits and sequential circuits
 To understand the functionalities, properties and applicability of Logic Families.
 To introduce programmable logic devices and ASM chart and synchronous state machines.
 To basics of microprocessor.

Course Outcomes:
On completion of the course, learner will be able to–
CO1: Simplify Boolean Expressions using K Map.
CO2: Design and implement combinational circuits.
CO3: Design and implement sequential circuits.
CO4: Develop simple real-world application using ASM and PLD.
CO5: Choose appropriate logic families IC packages as per the given design specifications.
CO6: Explain organization and architecture of computer system
Course Contents
Unit I Minimization Technique (06 Hours)
Logic Design Minimization Technique -: Minimization of Boolean function using K-map(up to 4
variables) and Quine Mc-Clusky Method, Representation of signed number- sign magnitude
representation ,1’s complement and 2’s complement form (red marked can be removed), Sum of
product and Product of sum form, Minimization of SOP and POS using K-map.
#Exemplar/Case Studies Digital locks using logic gates
Mapping of Course Outcomes for Unit I CO1
Unit II Combinational Logic Design (06 Hours)
Code converter -: BCD, Excess-3, Gray code, Binary Code. Half- Adder, Full Adder, Half Subtractor, Full
Subtractor, Binary Adder (IC 7483), BCD adder, Look ahead carry generator, Multiplexers (MUX):
MUX (IC 74153, 74151), Cascading multiplexers, Demultiplexers (DEMUX)- Decoder (IC 74138, IC
74154), Implementation of SOP and POS using MUX, DMUX, Comparators (2 bit), Parity generators
and Checker.
#Exemplar/Case Studies Combinational Logic Design of BCD to 7-segment display
Controller
Mapping of Course Outcomes for Unit II CO1, CO2
Unit III Sequential Logic Design (06 Hours)
Flip-Flop: SR, JK,D,T; Preset &Clear, Master Slave JK Flip Flops, Truth Tables and Excitation tables,
Conversion from one type to another type of Flop Flop. Registers: SISO, SIPO, PISO, PIPO, Shift
Registers, Bidirectional Shift Register, Ring Counter , Universal Shift Register Counters: Asynchronous
Counter, Synchronous Counter, BCD Counter, Johnson Counter, Modulus of the counter ( IC
7490),Synchronous Sequential Circuit Design :Models- Moore and Mealy, State diagram and State
Table ,Design Procedure, Sequence Generator and detector.
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#Exemplar/Case Studies Electronic Voting Machine (EVM)

Mapping of Course Outcomes for Unit CO2,CO3
III
Unit IV Algorithmic State Machines and Programmable (06 Hours)
Logic Devices
Algorithmic State Machines: Finite State Machines (FSM) and ASM, ASM charts, notations,
construction of ASM chart and realization for sequential circuits.
PLDS:PLD, ROM as PLD, Programmable Logic Array (PLA), Programmable Array Logic (PAL), Designing
combinational circuits using PLDs.

#Exemplar/Case Studies Wave form generator using MUX controller method

Mapping of Course Outcomes for Unit CO2, CO3, CO4
IV
Unit V Logic Families (06 Hours)
Classification of logic families: Unipolar and Bipolar Logic Families, Characteristics of Digital ICs:
Fan-in, Fan-out, Current and voltage parameters, Noise immunity, Propagation Delay, Power
Dissipation, Figure of Merits, Operating Temperature Range, power supply requirements.
Transistor-Transistor Logic: Operation of TTL NAND Gate (Two input ), TTL with active pull up, TTL
with open collector output, Wired AND Connection, Tristate TTL Devices, TTL characteristics.
CMOS: CMOS Inverter, CMOS characteristics, CMOS configurations- Wired Logic, Open drain outputs.
#Exemplar/Case Studies To study the various basic gate design using TTL/CMOS
logic family
Mapping of Course Outcomes for Unit V CO3
Unit VI Introduction to Computer Architecture (06 Hours)
Introduction to Ideal Microprocessor – Data Bus, Address Bus, Control Bus. Microprocessor based
Systems – Basic Operation, Microprocessor operation, Block Diagram of Microprocessor. Functional
Units of Microprocessor – ALU using IC 74181, Basic Arithmetic operations using ALU IC 74181, 4-bit
Multiplier circuit using ALU and shift registers. Memory Organization and Operations, digital circuit
using decoder and registers for memory operations.
#Exemplar/Case Studies Microprocessor based system in Communication
/Instrumentation Control
Mapping of Course Outcomes for Unit VI CO2, CO3, CO6
Learning Resources
Text Books:
1. Modern Digital Electronics by R.P.Jain, 4th Edition, ISBN 978-0-07-06691-16 Tata McGraw Hill
2. Digital Logic and Computer Design by Moris Mano, Pearson , ISBN 978-93-325-4252-5
Reference Books:
1. John Yarbrough, ―Digital Logic applications and Design, Cengage Learning, ISBN – 13: 978-81-
315-0058-3
2. D. Leach, Malvino, Saha, ―Digital Principles and Applications‖, Tata McGraw Hill, ISBN –
13:978-0-07-014170-4.
3. Anil Maini, ―Digital Electronics: Principles and Integrated Circuits‖, Wiley India Ltd, ISBN:978-
81-265-1466-3.
4. Norman B & Bradley, ―Digital Logic Design Principles, Wiley India Ltd, ISBN:978-81-265-1258-
MOOC Courses:
1. Digital Circuits, by Prof. Santanu Chattopadhyay ,
https://swayam.gov.in/nd1_noc19_ee51/preview
2. Digital Circuits and Systems , Prof. S. Srinivasan
https://nptel.ac.in/courses/117/106/117106086/

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@The CO-PO mapping table

PO PO1 PO2 PO3 PO4 PO5 PO6 PO7 PO8 PO9 PO10 PO11 PO12
CO1 3 - 2 - - - - - - - - -
CO2 3 1 3 - - - - - - - - -
CO3 3 1 3 - - - - - - - - -
CO4 3 - 2 1 - - - - - - - -
CO5 3 2 - - - - - - - - - -
CO6 3 - - - - - - - - - - -

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Savitribai Phule Pune University

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Second Year of Computer Engineering (2019 Course)
210249: Digital Electronics Laboratory
Teaching Scheme: Credit Examination Scheme:
PR: 02 Hours/Week 01 TW: 25 Marks

Guidelines for Instructor's Manual

The instructor ‘s manual is to be developed as a hands-on resource and reference. The
instructor's manual need to include prologue (about University/program/ institute/
department/foreword/ preface), University syllabus, conduction & Assessment guidelines, topics
under consideration-concept, objectives, outcomes, data sheets of various ICs
Guidelines for Student's Laboratory Journal
The laboratory assignments are to be submitted by student in the form of journal. Journal
consists of prologue, Certificate, table of contents, and handwritten write-up of each assignment
(Title, Objectives, Problem Statement, Outcomes, software & Hardware requirements, Date of
Completion, Assessment grade/marks and assessor's sign, Theory- Concept, circuit diagram, pin
configuration, conclusion/analysis).

As a conscious effort and little contribution towards Green IT and environment awareness,
attaching printed papers as part of write-ups and program listing to journal may be avoided.
Guidelines for Laboratory /TW Assessment
Continuous assessment of laboratory work is done based on overall performance and Laboratory
performance of student. Each Laboratory assignment assessment should assign grade/marks
based on parameters with appropriate weightage. Suggested parameters for overall assessment
as well as each Laboratory assignment assessment include- timely completion, performance,
innovation, efficiency, punctuality and neatness.
Guidelines for Laboratory Conduction
The instructor is expected to frame the assignments by understanding the prerequisites,
technological aspects, utility and recent trends related to the topic. The assignment framing
policy need to address the average students and inclusive of an element to attract and promote
the intelligent students. The instructor may set multiple sets of assignments and distribute among
batches of students. It is appreciated if the assignments are based on real world
problems/applications. Student should perform at least 12 experiments with all experiments from
group A and any 5 assignments from group Band one from group C assignments.
Suggested List of Laboratory Experiments/Assignments
Sr.
Group A
No.
1 To Realize Full Adder/ Subtractor using a) Basic Gates and b) Universal Gates
2 Design and implement Code Converters-Binary to Gray and BCD to Excess-3
3 Design and Realization of BCD Adder using 4-bit Binary Adder (IC 7483).
Realization of Boolean Expression for suitable combination logic using MUX 74151
4
/74153, DMUX 74154/74138
5 To Verify the truth table of two bit comparators using logic gates.
6 Design & Implement Parity Generator and checker using EX-OR.
Group B

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7 Design and Realization: Flip Flop conversion

8 Design of 2 bit and 3 bit Ripple Counter using MS JK flip-flop.
9 Design of Synchrous 3 bit Up and Down Counter using MSJK Flip Flop / D Flip Flop
10 Realization of Mod -N counter using ( Decade Counter IC 7490 ) .
Design and implement Sequence generator (for Prime Number/odd and even ) using MS
11
JK flip-flop
12 Design and implement Sequence detector using MS JK flip-flop
Group C
13 Study of Shift Registers ( SISO,SIPO, PISO, PIPO)
14 Design of ASM chart using MUX controller Method.

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SE (Computer Engineering) syllabus (2019 Course)