UNIT - 4

1. What is the primary role of an Instruction Set Architecture (ISA)?

a) Configuring cache memory layouts
b) Controlling hardware operation directly
c) Serving as an interface between software and hardware
d) Defining the operating system kernel structure

2. Which component translates ISA instructions into control signals for execution?
a) Pipeline
b) Cache memory
c) Compiler
d) Microcode

3. What is the main difference between CISC and RISC architectures?

a) RISC instructions are executed in one clock cycle.
b) RISC uses a large number of complex instructions.
c) CISC architectures do not use microcode.
d) CISC has simpler instruction decoding than RISC.

4. In which architecture is microcode most commonly found?

a) Von Neumann
b) CISC
c) Harvard
d) RISC

5. The Von Neumann architecture is characterized by:

a) No use of microcode
b) Unified storage for instructions and data
c) High-speed parallel execution
d) Separate storage for instructions and data

6. What key characteristic of Harvard architecture makes it different from Von Neumann?
a) Separate memory for instructions and data
b) No use of control hazards
c) Simplified instruction set
d) The absence of pipelines

7. Which characteristic is NOT a part of ISA design?

a) Cache memory structure
b) Data types supported
c) Instruction formats
d) Number of registers
8. Which stage of a pipeline fetches the instruction from memory?
a) Write-back
b) Execute
c) Decode
d) Fetch

9. What is the main goal of pipelining in microarchitecture?

a) Increasing instruction throughput
b) Reducing instruction size
c) Improving memory allocation
d) Increasing the clock speed

10. What causes a pipeline stall?

a) Cache misses
b) Overflow in the arithmetic unit
c) Excessive branching
d) Instructions completing out of order

11. What is a structural hazard in a pipeline?

a) Instruction fetch alignment issues
b) A hardware resource conflict
c) Cache memory failure
d) Incorrect instruction decoding

12. Which technique can resolve a data hazard in a pipeline?

a) Branch prediction
b) Operand forwarding
c) Increasing clock speed
d) Cache prefetching

13. Which hazard occurs due to dependency between instructions?

a) Control hazard
b) Instruction hazard
c) Structural hazard
d) Data hazard

14. What is the primary cause of a control hazard?

a) Cache line replacement
b) Instructions changing the flow of control
c) Data dependencies between instructions
d) Resource conflicts in the pipeline
15. Which mechanism helps reduce control hazards in a pipeline?
a) Operand forwarding
b) Clock cycle optimization
c) Branch prediction
d) Loop unrolling

16. What type of control hazard is introduced by jump instructions?

a) Jump hazard
b) Data hazard
c) Branch hazard
d) Conditional hazard

17. A superscalar processor is characterized by its ability to:

a) Execute multiple instructions per clock cycle
b) Increase cache memory
c) Use Harvard architecture exclusively
d) Eliminate control hazards completely

18. Which cache mapping method reduces cache conflicts significantly?

a) Fully associative
b) Direct mapping
c) Two-way set associative
d) Instruction mapping

19. What is the primary metric used to measure cache performance?

a) Access latency
b) Hit rate
c) Cache width
d) Memory bandwidth

20. What ensures proper alignment during instruction fetching?

a) Word-aligned memory access
b) Operand forwarding
c) Clock cycle synchronization
d) Superscalar execution
 UNIT – 5
1. Which mechanism is used to define the legal range of addresses for a process
in memory protection?
a) Stack pointer
b) Base and bound registers
c) Program counter
d) Translation Lookaside Buffer (TLB)

2. What is the primary function of memory protection in operating systems?

a) Optimize memory access speed
b) Prevent unauthorized access to memory
c) Improve processor efficiency
d) Enable multitasking

3. In a page-based memory system, which component maps virtual addresses to

physical addresses?
a) Base register
b) Memory Management Unit (MMU)
c) Program counter
d) Interrupt controller

4. What is the role of the Translation Lookaside Buffer (TLB)?

a) Cache page table entries for faster memory access
b) Perform context switching
c) Handle I/O interrupts
d) Allocate memory dynamically

5. Which of the following correctly describes internal fragmentation in memory

systems?
a) Unused memory outside allocated space
b) Fragmentation caused by paging
c) Unused memory within allocated space
d) Overlapping of memory regions

6. What is the primary goal of superscalar processors?

a) Increase memory capacity
b) Execute multiple instructions per clock cycle
c) Reduce power consumption
d) Improve cache performance

7. In an I2O2 processor, what does the "2" in "I2" indicate?

a) Number of ALUs
b) Number of issue units
c) Number of instructions issued
d) Number of output units
8. Which architectural feature allows out-of-order processors to improve
performance?
a) Instruction pipelining
b) Register renaming
c) Branch prediction
d) Loop unrolling

9. How does a superscalar processor handle data dependencies?

a) By stalling the pipeline
b) Through speculative execution
c) By scheduling instructions dynamically
d) Using fixed instruction order

10. Which of the following is a characteristic of VLIW (Very Long Instruction Word)
architectures?
a) Dynamic instruction scheduling
b) Hardware-dependent parallelism
c) Compiler-dependent parallelism
d) Single instruction stream

11. What is the primary difference between an interrupt and an exception?

a) Interrupts are hardware-triggered, while exceptions are software-triggered
b) Interrupts are synchronous, while exceptions are asynchronous
c) Interrupts are software-triggered, while exceptions are hardware-triggered
d) Both are asynchronous events

12. What is meant by instruction by-passing in pipeline processors?

a) Skipping non-essential instructions
b) Resolving hazards by forwarding data
c) Avoiding branch instructions
d) Flushing the pipeline

13. What is the role of an interrupt vector table?

a) Maps interrupt requests to service routines
b) Maps exceptions to memory locations
c) Manages memory allocation during interrupts
d) Handles virtual memory translation

14. What is an advantage of masking interrupts in a system?

a) Prevents processor starvation
b) Ensures high-priority tasks are completed
c) Reduces system overhead
d) Increases throughput

15. How does out-of-order execution help improve CPU performance?

a) It allows the CPU to execute non-dependent instructions earlier
b) It bypasses unused instructions
 c) It prioritizes I/O operations
d) It increases clock speed

16. What is the main purpose of branch prediction in processors?

a) Reduce power consumption
b) Decrease cache miss rate
c) Minimize control hazards
d) Improve clock speed

17. Which type of branch prediction uses historical data to predict outcomes?
a) Static prediction
b) Dynamic prediction
c) Direct mapping
d) Speculative prediction

18. What does a 2-bit branch predictor improve upon compared to a 1-bit
predictor?
a) Improved accuracy for loops
b) Reduced hardware complexity
c) Decreased latency
d) Enhanced pipeline depth

19. In which scenario would a branch predictor likely fail?

a) Predicting always-taken branches
b) Predicting frequently changing conditions
c) Predicting unconditional branches
d) Predicting nested loops

20. What is the significance of branch target buffers (BTBs) in branch prediction?
a) Cache predicted outcomes for branch instructions
b) Store branch instruction addresses
c) Maintain a list of active branches
d) Predict outcomes of arithmetic operations
 UNIT – 6
1. What is the primary advantage of cache pipelining?
a) Reduced power consumption
b) Increased cache size
c) Improved throughput
d) Reduced clock cycles per instruction

2. What is the primary role of write buffers in a memory system?

a) To temporarily store cache victim blocks
b) To increase read bandwidth
c) To reduce write latency by holding pending writes
d) To prefetch instructions for execution

3. In a multilevel cache hierarchy, which cache is closest to the CPU?

a) L1 cache
b) L2 cache
c) Victim cache
d) Prefetch cache

4. Which of the following best describes a victim cache?

a) Stores prefetched data for future use
b) Holds evicted cache blocks to reduce miss penalties
c) Acts as a buffer for simultaneous read/write operations
d) Replaces the L1 cache for performance enhancement

5. Prefetching in cache design primarily aims to:

a) Reduce cache hit latency
b) Improve cache write efficiency
c) Eliminate the need for a write buffer
d) Load data into cache before it is needed

6. Software memory optimization techniques are often used to:

a) Reduce hardware complexity
b) Increase instruction-level parallelism
c) Minimize CPU power consumption
d) Enhance cache utilization

7. What is a key feature of non-blocking caches?

a) They allow simultaneous read and write operations
b) They eliminate cache miss penalties
c) They support multiple outstanding memory accesses
d) They increase cache coherence efficiency

8. In vector processors, compiler optimization often focuses on:

a) Reducing clock speed
 b) Increasing instruction dependency
c) Improving data alignment and parallelism
d) Lowering pipeline hazards

9. Which hardware optimization is critical for GPU performance?

a) Maximizing memory bandwidth
b) Reducing cache size
c) Increasing CPU clock speed
d) Implementing branch prediction

10. A major difference between scalar processors and vector processors is:
a) Scalar processors execute one instruction per cycle, while vector processors
execute multiple instructions.
b) Scalar processors handle one data element at a time, while vector processors
handle multiple data elements.
c) Scalar processors require higher memory bandwidth compared to vector
processors.
d) Scalar processors are optimized for SIMD operations.

11. Which of the following describes SIMD in multithreading?

a) Executes a single instruction on multiple data elements
b) Executes multiple instructions on a single data element
c) Executes independent threads on multiple cores
d) Executes instructions sequentially to maintain consistency

12. In GPUs, coarse-grained multithreading is used to:

a) Hide latency caused by memory stalls
b) Improve cache coherence
c) Increase the size of each thread
d) Ensure sequential instruction execution

13. Multithreading improves performance by:

a) Increasing pipeline depth
b) Reducing instruction fetch penalties
c) Overlapping the execution of multiple threads
d) Maximizing single-threaded execution time

14. Sequential consistency in parallel programming ensures that:

a) All threads execute in parallel without dependencies
b) Memory operations appear in a globally consistent order
c) Locks are never required for synchronization
d) Only atomic operations are used

15. A lock in parallel programming is used to:

a) Reduce the number of active threads
b) Optimize memory usage during execution
c) Minimize thread context switching
d) Prevent simultaneous access to shared resources
16. Atomic operations in parallel programming ensure:
a) Multiple instructions are executed simultaneously
b) Reduced memory bandwidth usage
c) Coherence across cache levels
d) Operations are completed without interruption

17. Memory fences in parallel programming are used to:

a) Prevent deadlocks in shared resources
b) Ensure proper ordering of memory operations
c) Increase multithreading efficiency
d) Decrease memory coherence overhead

18. Which is a characteristic of a semaphore in parallel programming?

a) It allows multiple threads to access a shared resource concurrently
b) It prevents deadlocks in lock mechanisms
c) It provides exclusive access to shared resources
d) It is always implemented as a hardware-level primitive

19. Which cache coherence protocol ensures that multiple processors maintain a
consistent view of memory?
a) MESI protocol
b) SIMD protocol
c) Non-blocking protocol
d) Prefetching protocol

20. In small multiprocessor systems, bus implementation is critical for:

a) Increasing processor clock speed
b) Reducing cache size
c) Managing interprocessor communication
d) Eliminating pipeline hazards