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Lecture Ic Fabrication

Integrated Circuits Fabrication

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0% found this document useful (0 votes)
14 views

Lecture Ic Fabrication

Integrated Circuits Fabrication

Uploaded by

smr549152
Copyright
© © All Rights Reserved
Available Formats
Download as PDF, TXT or read online on Scribd
You are on page 1/ 39

Integrated Electronics

Lecture
IC Fabrication

1
Contents
• Integrated Circuits
• Advantages of ICs
• Classification of ICs
• Basic processes involved in fabricating
Monolithic ICs
• Packaging of ICs

2
Integrated Circuits
• Complete circuits composed of active and
passive components over single
semiconductor chip of silicon known as ICs.
• Mostly silicon material is used to fabricate ICs
but for special applications gallium arsenide
and other compound semiconductor materials
are also utilized.

3
Advantages of ICs
1. Practically size of an IC is thousand times smaller than the
discrete circuits.
2. Thousands of silicon wafers consisting millions of
components can be produced known as mass production.
Due to this cost of IC is very low.
3. Number of components are fabricated on silicon wafer,
the weight of IC reduces as compare to discrete circuits.
4. IC operates at low voltages. The power consumption of IC
is very low.
5. Effect of parasitic capacitances are minimized in ICs,
hence operating speed is higher.
6. Reliability, accuracy and life of ICs is high.

4
Classification of ICs
• Depending upon the function utility, the ICs
are classified as linear and digital ICs.
• Structure point of view ICs can be divided as:
– Monolithic ICs
– Thick-thin film ICs
– Hybrid ICs

5
Monolithic ICs
• All active and passive components along their
interconnections are manufactured on a single
silicon chip.
• It has power limitations, hence they are
preferred in low power applications.

6
Thick-thin Film ICs
• Thick and thin film IC’s are comparatively
larger than monolithic IC’s and smaller than
discrete circuits.
• They find their use in high power applications.
• Such devices have to be externally connected
on to its corresponding pins.
• Passive components like resisters and
capacitors can be integrated.

7
Hybrid ICs
• The circuit is fabricated by interconnecting a
number of individual chips.
• It is used for high power applications.
• Hybrid ICs combine two or more monolithic
ICs in one package.
• Combine monolithic ICs with thick-thin film.

8
Basic processes involved in fabricating
Monolithic ICs
1. Silicon wafer (substrate) preparation
2. Epitaxial growth
3. Oxidation
4. Photolithography
5. Diffusion
6. Ion implantation
7. Isolation technique
8. Metallization
9. Assembly processing & packaging

9
Silicon wafer (substrate) preparation
• The first important process in IC fabrication is the
formation of silicon wafer through the crystal
growth. This process is subdivided into number of
sub-process.
1. Silicon Crystal ingots growing
2. Ingot trimming & grinding
3. Ingot slicing
4. Wafer etching
5. Wafer polishing
6. Wafer cleaning

10
Czochralski Crystal Growth
• The single crystal silicon can be obtain by using
this method.
• Used for silicon crystal growth from which silicon
wafers are produced.
• The apparatus used for crystal growth is called
puller.
• The puller have some subsystem namely
– Crystal Pulling Mechanism
– Ambient Control
– Control System

11
Czochralski Crystal Growth
• The furnace consists a
crucible (a container
that can withstand very
high temperature).
• The crucible is made up
of fused silica (SiO2) as
this material is
chemically unreactive
with another silicon.

12
Making silicon boules
Czochralski process:

Melting of Introduction of Beginning of Crystal pulling Formed crystal


polysilicon seed crystal crystal growth

What is silicon?
en.wikipedia.org
http://mrsec.wisc.edu
en.wikipedia.org

Wafers are cut from boules, which are large logs


of uniform silicon.

Looking at this picture, where


do you think silicon boules are
made? Why do you think so?
Czochralski Crystal Growth
• High purity semiconductor silicon is melted in
a crucible, usually made of quartz.
• Dopant impurity atom such as boron or
phosphorous can be added to molten silicon
in precise amounts to dope the silicon.
• P-type and N-type material formed.
• The crystal rod is slowly pulled upward.
• The standard ingot is about 150mm and
length is about 2m weight about 60kg.
15
Ingot Trimming & Grinding
• First seed is separated circular ingot.
• The top and bottom ends are cutoff.
• Silicon is hard so industrial grade diamond is used
to shape it.
• This is called Ingot trimming and grinding
Ingot Slicing
• Actually ingots are oversized so with the help of
diamond tool the ingot is groomed to precise
diameter.
• The slices of ingot are called wafers.

16
Wafer Etching
• Etching is used in micro fabrication to chemically
remove layers from the surface of a wafer during
manufacturing or after the photolithography
process.
• Etching is a critically important process module,
and every wafer undergoes many etching steps
before it is complete.
• Due to various process during trimming, grinding
wafer gets contaminated at edge so by using
chemical etching all damages are removed.
17
Wafer Cleaning and Polishing
• The wafers are cleaned, ruined and dried for
use in the fabrications of discrete devices and
ICs.
• Wafers are cleaned by using HC-H2O2 acquires
metallic impurities can be removed and
dipped in water.

18
Epitaxial Growth
• Epitaxy refers to the deposition of a crystalline
over layer on a crystalline substrate.
• Epitaxy is crystalline growth process in which the
foundation layer i-e substrate works as seed
crystal.
• The epitaxial layer formed on the substrate may
be either n-doped, p-doped or intrinsic.
• Epitaxial growth of pure silicon can be
represented by following chemical reaction.
SiCl4(g) + 2H2(g) ↔ Si(s) + 4HCl(g)

19
Epitaxial Growth
• Two types of epitaxy
• Homoepitaxy: When epitaxial layer and the
substrate on which the epitaxial layer is to be
formed are having same material then the
process is called Homoepitaxy.
• Hetroepitaxy: is a kind of epitaxy performed
with materials that are different from each other.
In heteroepitaxy, a crystalline film grows on a
crystalline substrate or film of a different
material.
20
Thermal Oxidation
• Process in which a thin layer of silicon dioxide
(SiO2) formed on a surface of silicon wafer using
thermal growth techniques.
• For thin oxides with low charge density at
interface, the oxides are grown in dry oxygen
called dry oxidation.

• For thick layer of oxide, steam of water vapor is


used at high pressure for oxidation called wet
oxidation.
21
Thermal Oxidation

22
Chemical Vapor Deposition (CVD)
• Chemical process used to produce high-purity,
high-performance solid materials. The process
is often used in the semiconductor industry to
produce thin films.
• The film is formed on surface of substrate by
thermal decomposition or the reaction of
various gasses compounds.
• Epitaxial layer is formed.

23
Diffusion
• The process of doping i-e adding impurity to
silicon wafers.
• Diffusion is used to form bases, emitters and
resistors in bipolar device and to form source
and drain regions in MOS.
• The dopant can be added into the silicon
wafer.

24
Ion Implementation
• The conductivity of semiconductor when small
impurity is added to it (doping).
• Ion implementation is the process of adding
dopant to silicon substrate.
• It is controllable, reproducible and also there are
no unwanted side effects.
• It is a low temperature process the dopant atoms
are vaporized.
• They are accelerated by an accelerator and then
bombarded on silicon substrate.

25
Photolithography
• To produce extremely small circuits and to
develop pattern on silicon wafer is called
photolithography.
• Using electron beam lithography or x-ray
lithography, to achieve dimensions less than
1µm.
• The process is subdivided into
– Photomask Generation
– Lithography

26
27
Metallization
• Process in which a thin layer of metal is
formed which is used to make
interconnections between components and
outside world.
• Three types of metallization
– Gate Metallization
– Contact Metallization
– Interconnection Metallization

28
Metallization
• Some certain requirements of metallization.
1. Metal layer should be low resistivity
2. Formation of layer should be easy
3. Layer should not react with final wafer
4. Metal should not contaminated devices, wafers
5. Device characteristic should be good
6. Should be stable

29
Metallization Process
• Involves heating the coating metal to its boiling
point in a vacuum chamber, then letting
condensation deposit the metal on the
substrate's surface.
• Resistance heating, electron beam, or plasma
heating is used to vaporize the coating metal.
• Vacuum metallizing was used to deposit
aluminum on the large glass mirrors of
reflecting telescopes.

30
Metallization Process

31
Packaging of ICs
• The final series of operations to transform the
wafer into individual chips, ready to connect
to external circuits and prepared to withstand
the harsh environment of the world outside
the clean room.
• Accomplished after all of the processing steps
on the wafer have been completed.

32
Design Issues in IC Packaging
• Electrical connections to external circuits
• Materials to encase chip and protect it from
the environment (humidity, corrosion,
temperature, vibration, mechanical shock)
• Heat dissipation
• Performance, reliability, and service life
• Cost

33
Manufacturing Issues in IC Packaging
• Chip separation - cutting wafer into individual
chips
• Connecting it to the package
• Encapsulating the chip
• Circuit testing

34
IC Package Design
• Topics related to the design of an integrated
circuit package:
– Number of input/output terminals required for an
IC of a given size
– Materials used in IC packages
– Package styles

35
Input/Output (I/O) Terminals
in IC Packaging
• The basic problem is to connect many internal
circuits on the chip to I/O terminals so that the
appropriate electrical signals can be
communicated to the outside world.
• As the number of devices in the IC increases, the
required number of I/O terminals also increases
• The problem is aggravated by IC trends:
– Decreases in device size
– Increases in number of devices in IC

36
Major IC Package Styles
• Dual in-line package (DIP)
• Square package
• Pin grid array

37
IC Packaging Features
• Maximum pin count
• Dimensions
• Pitch (Spacing between centers of adjacent
pins)
• Encapsulation material
• Mode of mounting
• Maximum power dissipation

38
END OF LECTURE

39

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