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Memory Organization and Structure-1

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165 views

Memory Organization and Structure-1

This notes is useful for Bs and intermediate program.

Uploaded by

tehzain24
Copyright
© © All Rights Reserved
Available Formats
Download as PDF, TXT or read online on Scribd
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Memory Organization and Structure

(Segmented and linear model)


Memory Hierarchy Design and its Characteristics
In the Computer System Design, Memory Hierarchy is an enhancement to organize the memory
such that it can minimize the access time. The Memory Hierarchy was developed based on a
program behavior known as locality of references.

Types of Meomory Hierarchy design:


1. External Memory or Secondary Memory:
Comprising of Magnetic disk, Optical Disk, Magnetic Tape, i.e. peripheral storage devices
which are accessible by the processor via I/O Module.
2. Internal Memory or Primary Memory:
Comprising of Main memory, Cache Memory, &CPU registers. This is directly accessible
by the processor.

Characteristics of Memory Hierarchy Design:


1. Capacity: It is the global volume of information can store. As we move from top to
bottom in the Hierarchy, the access time increases.
2. Access Time: It is the time interval between read/write request and the availability of the
data. As we move from top to bottom in the Hierarchy, the access time increases.
3. Performance: Earlier when the computer system was designed without Memory
Hierarchy design, the speed gap increases between the CPU registers and Main Memory
due to large difference in access time. This results in lower performance of the system and
thus, enhancement was required. This enhancement was made in the form of Memory
Hierarchy Design because of which the performance of the system increases.
4. Cost per bit: As we move from bottom to top in the Hierarchy, the cost per bit increases
i.e. Internal Memory is costlier than External Memory.
Difference between Byte Addressable Memory and Word
Addressable Memory
o Memory is a storage component in the Computer used to store application programs.
Memory Chip is divided into equal parts called as “CELLS”. Each Cell is uniquely identified by
a binary number called as “ADDRESS”. For example, the Memory chip configuration is
represented as ‘64K X 8’ as shown in the figure given below:
Memory Chip Representation

64K X 8

This indicates the number of cells in This indicates the size of the cell (the
the memory chip i.e. 64k cells(here) number of bits that can be stored in
the cell) i.e. 8 bits (here)

o The following information can be obtained from the memory chip representation shown
above:
o Data Space in the Chip = 64K X 8
2. Data Space in the Cell = 8 bits
3. Address Space in the Chip = 16 bits
o The default memory configuration in the Computer design is Byte Addressable.
BYTE ADDRESSABLE MEMORY WORD ADDRESSABLE MEMORY
When the data space in the cell = 8 When the data space in the cell = word
bits then the corresponding address length
space is called as Byte Address. of CPU then the corresponding address space
is called as Word Address.
Based on this data storage i.e. Bytewise Based on this data storage i.e. Wordwise
storage, the memory chip configuration is storage, the memory chip configuration is
named as Byte Addressable Memory. named as Word Addressable Memory.

Segmented Model:
Segmentation is the process in which the main memory of the computer is logically divided
into different segments and each segment has its own base address. It is basically used to
enhance the speed of execution of the computer system, so that the processor is able to fetch
and execute the data from the memory easily and fast.

Need for Segmentation:


The Bus Interface Unit (BIU) contains four 16 bit special purpose registers (mentioned below)
called as Segment Registers.

• Code segment register (CS): is used for addressing memory location in the code
segment of the memory, where the executable program is stored.

• Data segment register (DS): points to the data segment of the memory where the
data is stored.

• Extra Segment Register (ES): also refers to a segment in the memory which is
another data segment in the memory.

• Stack Segment Register (SS): is used for addressing stack segment of the memory.
The stack segment is that segment of memory which is used to store stack data.
The number of address lines in 8086 is 20, 8086 BIU will send 20bit address, so as to access one
of the 1MB memory locations. The four segment registers actually contain the upper 16 bits of
the starting addresses of the four memory segments of 64 KB each with which the 8086 is
working at that instant of time. A segment is a logical unit of memory that may be up to 64
kilobytes long. Each segment is made up of contiguous memory locations. It is an independent,
separately addressable unit. Starting address will always be changing. It will not be fixed.
Note that the 8086 does not work the whole 1MB memory at any given time. However, it works
only with four 64KB segments within the whole 1MB memory.
Below is the one way of positioning four 64 kilobyte segments within the 1M byte memory
space of an 8086.
Types Of Segmentation:
1. Overlapping Segment – A segment starts at a particular address and its maximum
size can go up to 64kilobytes. But if another segment starts along with this 64kilobytes
location of the first segment, then the two are said to be Overlapping Segment.

2. Non-Overlapped Segment – A segment starts at a particular address and its


maximum size can go up to 64kilobytes. But if another segment starts before this
64kilobytes location of the first segment, then the two segments are said to be Non-
Overlapped Segment.

Rules of Segmentation
Segmentation process follows some rules as follows:
• The starting address of a segment should be such that it can be evenly divided by 16.
• Minimum size of a segment can be 16 bytes and the maximum can be 64 kB.
Advantages of the Segmentation: The main advantages of segmentation are
as follows:
o It provides a powerful memory management mechanism.
o Data related or stack related operations can be performed in different segments.
o Code related operation can be done in separate code segments.
o It allows to processes to easily share data.
o It allows to extend the address ability of the processor, i.e. segmentation allows
the use of 16 bit registers to give an addressing capability of 1 Megabytes.
Without segmentation, it would require 20 bit registers.
o It is possible to enhance the memory size of code data or stack segments beyond
64 KB by allotting more than one segment for each area.

Linear Memory Model:


A linear memory model, also known as the flat memory model refers to a memory addressing
technique in which memory is organized in a single contiguous address space. This means that
the processing unit can access these memory locations directly as well as linearly.
To better understand a linear memory model, we should understand two basic components:
address and data.
o Address is a hexadecimal number which is used to denote the exact place of a memory
chunk. Data is the value stored in that memory.
o In a linear memory model, the entire memory space is linear, sequential and contiguous.
The address ranges from 0 to MaxByte -1, where MaxBytes is the maximum limit of
memory. Each program uses one 32-bit linear memory space, that means 2^32 = 4GB of
memory can be addressed using this memory model. The operating system then translates
these linear addresses to physical addresses using paging schemes.

Features of Linear Model:


1. Simple interface for programmers, clean design.
2. Greatest flexibility due to uniform access speed (segmented memory page switches
usually incur varied latency due to longer accesses of other pages, either due to extra
CPU logic in changing page, or hardware requirements).
3. Minimum hardware and CPU real estate for simple controller applications.
4. Maximum execution speed.
5. Not suitable for general computing or multitasking operating systems unless enhanced
with additional memory management hardware/software; but this is almost always the
case in modern CISC processors, which implement advanced memory management and
protection technology over a flat memory model. Linux e.g. uses a flat memory model,

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