Embedded Systems

Chapter 8 - AVR Interrupts

Dr. Adnan Ismail Al-Sulaifanie

Department of Electrical and Computer Engineering

University of Duhok, Iraq

Outline

ä Discuss the need and uses of interrupts in the microcontroller-based systems

ä Discuss the interrupt structure of the AVRs.

ä Learn how to enable/disable interrupts.

ä Learn how to write interrupt service routine for timers and external devices.

References

1. Mazidi, The AVR Microcontroller and Embedded Systems Using Assembly

and C, chapter 11

1
1 Introduction

ä There are two ways to determine whether peripheral devices require attention or
services of the microcontroller: polling and interrupt.

ä Polling is based on software. It requires the microcontroller to continuously monitor

the status of a peripheral device and provides services when the device requires
service.

ä This method is useful when the processor has to do only one task (or a few) and
response time is not an issue.

ä The problems with the polling method are the following:

1. It wastes microcontroller time by monitoring the device continuously.

2. Priorities cannot be assigned to devices because the status can be monitored
one by one for all devices irrespective of their priority and importance.
3. It makes the system slower because high-priority device has to wait for its turn
when lower priority devices are being polled and serviced.

ä Interrupt method is preferred over polling method.

ä Interrupt is an event that causes the processor to suspend its present task, and
transfer the control to another program called Interrupt Service Routine (ISR) or
interrupt handler. After completing the executing of ISR, the control is transferred
back again to the main program.

ä An interrupt is initiated through a signal generated by an event that causes the

controller to stop temporarily its current program-execution activities and perform
the task to service that event.

ä The interrupts allow the microcontroller to respond to the asynchronous events

while another task is being executed. The asynchronous event means we do not
know in advance when they will occur.

ä Interrupts provide many advantages over polling method:

1. Efficient time utilization (no continuous monitoring is required).

2. It supports priority assignment depending on the importance of the connected
devices.
3. It makes the system faster because more important activities are handled im-
mediately.
4. More devices can be served.
5. The system can be programmed to ignore any or all devices while handling
critical tasks.

2
2 AVR interrupts

2.1 Interrupt Vector Table

ä AVRs have up to or more interrupts (2 external).

ä Reset is a special type of interrupt but it is not included in the list.

ä Each interrupt has a vector address called interrupt vector.

ä The term interrupt vector refers to the starting address of the ISR.

ä The supported interrupts and their starting address of ATmega328P is shown below:

# Address Source Vector name Interrupt Definition

1 0x0000 RESET Restart microcontroller

2 0x0002 INT0 INT0_vect External Interrupt Request 0
3 0x0004 INT1 INT1_vect External Interrupt Request 1
4 0x0006 PCINT0 PCINT0_vect Pin Change Interrupt Request 0
5 0x0008 PCINT1 PCINT1_vect Pin Change Interrupt Request 1
6 0x000A PCINT2 PCINT2_vect Pin Change Interrupt Request 2
7 0x000C WDT WDT_vect Watchdog Time-Out Interrupt
8 0x000E TIMER2 COMPA TIMER2_COMPA_vect Timer/Counter2 Compare Match A
9 0x0010 TIMER2 COMPB TIMER2_COMPB_vect Timer/Counter2 Compare Match B
10 0x0012 TIMER2 OVF TIMER2_OVF_vect Timer/Counter2 Overflow
11 0x0014 TIMER1 CAPT TIMER1_CAPT_vect Timer/Counter1 Capture Event
12 0x0016 TIMER1 COMPA TIMER1_COMPA_vect Timer/Counter1 Compare Match A
13 0x0018 TIMER1 COMPB TIMER1_COMPB_vect Timer/Counter1 Compare Match B
14 0x001A TIMER1 OVF TIMER1_OVF_vect Timer/Counter1 Overflow
15 0x001C TIMER0 COMPA TIMER0_COMPA_vect Timer/Counter0 Compare Match A
16 0x001E TIMER0 COMPB TIMER0_COMPB_vect Timer/Counter0 Compare Match B
17 0x0020 TIMER0 OVF TIMER0_OVF_vect Timer/Counter0 Overflow
18 0x0022 SPI, STC SPI_STC_vect SPI Serial Transfer Complete
19 0x0024 USART, RX USART_RX_vect USART Rx Complete
20 0x0026 USART, UDRE USART_UDRE_vect USART Data Register Empty
21 0x0028 USART, TX USART_TX_vect USART Tx Complete
22 0x002A ADC ADC_vect ADC Conversion Complete
23 0x002C EE Ready EE_READY_vect EEPROM Ready
24 0x002E Analog comp ANALOG_COMP_vect Analog Comparator
25 0x0030 TWI TWI_vect Two-Wire Serial Interface
26 0x0032 SPM ready SPM_READY_vect Store Program Memory Ready

ä Global interrupt enable/disable is controlled through I-bit in SREG.

3
 SEI ; enable interrupt
CLI ; disable interrupt

ä Each interrupt can be enabled/disabled individually using mask register of the in-
terrupt source.

2.2 Interrupt Handling and Execution

1. Complete execution of current instruction.

2. PC =⇒ STACK

3. Address(ISR) =⇒ PC

4. Execute ISR until reaching RETI instruction.

5. STACK =⇒ PC

6. Resume execution of main program

ä When any interrupt is generated (or asserted), it forces the microcontroller to jump
to a fixed address in the vector table.

ä There are only two bytes reserved for ISR of each interrupt.

ä When an interrupt is used, RJMP is written at the address of ISR as shown below:

.ORG 0x0000
JMP MAIN

.ORG 0x001A ; starting address of ISR for TIMER0 OVF

RJMP T0ISR

.ORG 0x0100 ; starting address of main program

MAIN: .....
.....
.....
HERE RJMP HERE

T0ISR : ...
...
RETI

4
2.3 External Interrupts

ä AVRs have two or three external interrupts depending on the family member.

ä Before using these interrupts, it is necessary to configure its related registers:

Reg. D7 D6 D5 D4 D3 D2 D1 D0
EICRA - - - - ISC11 ISC10 ISC01 ISC00
EIMSK – – – – – – INT1 INT0
EIFR – – – – – – INTF1 INTF0

1. Select trigger level of the interrupt pin in EICRA register

ISC01-ISC00 Mode (interrupt generated)

00 The low level on the INTn pin.
01 Any logical change on the INTn pin.
10 The falling edge on the INTn pin.
11 The rising edge on the INTn pin.

2. Enable individual interrupt by setting the corresponding bit in EIMSK register.

3. Enable global interrupt (SEI)

ä The flag INTFn is cleared when the interrupt routine is executed. Alternatively, the
flag can be cleared by writing ’1’ to it. This flag is always cleared when INTn is
configured as a level interrupt.

Example 1 - Assume that the INT1 pin is connected to a switch that is normally
high. Whenever it goes low, it should turn on a LED. The LED is connected to PA.3 and
is normally off. When it is turned on it should stay on for a fraction of a second. As long
as the switch is pressed low, the LED should stay on.

.ORG 0x0000
JMP MAIN

.ORG 0x0004 ; starting address of INT1 ISR

JMP ISR1 ; jump to starting address of INT1 ISR

.ORG 0x0100 ; starting address of main program

MAIN: SEI ; enable global interrupt SREG(I) = 1
CBI DDRD, 3 ; DDRD(3) = 0, PD3 = INT1
SBI EIMSK, 1 ; enable INT1
SBI DDRA, 3 ; DDRA(3) = 1, PA.3 is output
HERE: RJMP HERE ; still here unless interrupted

5
ISR1: SBI PORTA, 3 ; PA.3 = 1 , turn LED on
LDI R24, 0XFF delay loop
LDI R25, 0XFF delay loop
BACK: SBIW R25:R24, 0x01
BREQ BACK ;
CBI PORTA, 3 ; PA.3 = 0 , turn LED off
RETI

2.4 Interrupt Vector Summary

0x0002 External Interrupt Request 0 (INT0)

0x0004 External Interrupt Request 1 (INT1)
0x0006 Pin Change Interrupt Request 0
0x0008 Pin Change Interrupt Request 0
0x000a Pin Change Interrupt Request 1
0x000c Watchdog Time-out Interrupt
0x000e Timer/Counter2 Compare Match A (OCF2A = 1)
0x0010 Timer/Counter2 Compare Match B (OCF2B = 1)
0x0012 Timer/Counter2 Overflow (TOV2 = 1)
0x0014 Timer/Counter1 Capture Event
0x0016 Timer/Counter1 Compare Match A (OCF1A = 1)
0x0018 Timer/Counter1 Compare Match B (OCF1B = 1)
0x001A Timer/Counter1 Overflow (TOV1 = 1)
0x001C TimerCounter0 Compare Match A (OCF0A = 1)
0x001E TimerCounter0 Compare Match B (OCF0B = 1)
0x0020 Timer/Couner0 Overflow (TOV0 = 1)
0x0022 SPI Serial Transfer Complete
0x0024 USART Rx Complete

6
0x0026 USART, Data Register Empty
0x0028 USART Tx Complete
0x002A ADC Conversion Complete
0x002C EEPROM Ready
0x002E Analog Comparator
0x0030 Two-wire Serial Interface
0x0032 Store Program Memory Read