Slide #2 - The AVR Microcontroller
Slide #2 - The AVR Microcontroller
Data
Memory
• Still very much like Harvard architecture with
separate data and program memory systems
Program
Memory • Fixed data can be stored in instruction memory
can accessed like read-only data with special
instructions i.e. to this instructions data and
instruction address can be common
Computer Architecture:
🔿 CISC has a large collection of instructions that range from simple to very complex and specialized in
the assembly language level. The objective of the approach is to reduce number of instructions on
each program.
🔿 It emphasizes on building complex instructions directly in the hardware because the hardware is
always faster than software.
🔿 It helps reduce program code by embedding multiple operations on each program instruction, this in
turn makes the CISC processor more complex BUT slower in instructions processing.
🔿 Instructions in CISC are complex, and they occupy more than a single word in memory. CISC (as in
RISC) has access to memory operands via registers, however CISC also has instructions to directly
access memory operands.
🔿 It is designed to decrease memory costs because large programs or instruction required large
memory space to store the data, thus increasing the memory requirement, and a large collection of
memory increases the memory cost.
ESE DEPT., MJIIT, UTM
Reading material
SMJE318-SEM2/2021-2022
8
RISC – Reduced Instruction Set Computer
🔿 An architecture with a simple collection and highly customized set of instructions.
🔿 Each instruction is simple and requires only one clock cycle, and each cycle contains
three parameters: fetch, decode and execute. But is also used to perform various
complex instructions by combining them into simpler ones.
🔿 Although program size can be relatively high, pipelining in RISC is carried out
relatively simply and efficiently due to the execution of instructions being done in a
uniform interval of time (i.e. one click). Therefore faster processing.
🔿 RISC synthesizes (breaks down) complex data types and supports few simple data
types. Thus, making use of simple addressing modes and fixed length instructions
for efficient pipelining.
🔿 RISC does not allow direct access to memory locations, for fast processing RISC
processors have a large number of registers.
ESE DEPT., MJIIT, UTM
Reading material
SMJE318-SEM2/2021-2022
CISC vs RISC
RISC CISC
AVR Families Package Program Data Data Peripheral Timers ADC -DAC
memory Memory EEPROM Set
-Flash (RAM) (I/O pins)
(bytes)
ATtiny series 6-32 pins 1K – 8K 64 - 512 64 - 512 Limited Max. 2 ADC: 4 / 8
(6 / 12)
ATmega series 28-100 pins 8K – 128K 1K – 8K 0.5K – 4K Extensive Max. 6 ADC: 8 / 16
23/32/54/86
Special purpose 16K – 1K – 4K 0.5K – 4K For specific Max. 4 Replaced by
128K applications special features
AT mega 64 4 PA-AU
AT-Atmel Packaging and standard
(manufacturer)
mega – AVR μC series Power parameter description
AVR : A microcontroller
originally manufactured by a
company name, ATMEL,
which is currently already
acquired by Microchip
Electronics.
The microcontroller is
embedded on Arduino board.
🔿 Most Arduino boards consist of an Atmel 8-bit AVR microcontroller with varying
amounts of flash memory, pins, and features.
🔿 Programming AVR μCs on Arduino boards are made easy because the μC are pre-
loaded with boot loader that simplifies uploading programs to the on-chip flash
memory. The default bootloader of the Arduino Uno is the Optiboot bootloader where
boards are loaded with program code via a serial connection (e.g. USB, RS 232) to
another computer.
🔿 The Arduino IDE tools and ecosystem supports processors other than just Atmel AVR
chips. For instance the Arduino Dude uses an ARM Cortex-M3 processor.