S.

No Practical Description Date Teachers Sign

1. Study of Multiplexer and Demultiplexer

Study of Half Adder and Subtractor

2.

Study of Full Adder and Subtractor

3.

WAP to add two 8 bit numbers and store the

4. result at memory location 2000
WAP to multiply two 8 bit numbers stored at
memory location 2000 and 2001 and stores the
5. result at memory location 2000 and 2001.

WAP to add two 16-bit numbers. Store the

6. result at memory address starting from 2000.

WAP which tests if any bit is '0' in a data byte

specified at an address 2000. If it is so, 00
7. would be stored at address 2001 and if not so
then FF should be stored at the same address.

Assume that 3 bytes of data are stored at

consecutive memory addresses of the data
memory starting at 2000. Write a program
8. which loads register C with (2000), i.e. with
data contained at memory address2000, D with
(2001), E with (2002) and A with (2001).

Sixteen bytes of data are specified at

consecutive data-memory locations starting at
9. 2000. Write a program which increments the
value of all sixteen bytes by 01.
WAP to add t 10 bytes stored at memory
10. location starting from 3000. Store the result at
memory location 300A
 Experiment NO.1
Q.1 Study of Multiplexer and Demultiplexer ?
Ans: Multiplexer
A multiplexer is a combinational circuit that has 2n input lines and a single output line. Simply,
the multiplexer is a multi-input and single-output combinational circuit. The binary information
is received from the input lines and directed to the output line. On the basis of the values of the
selection lines, one of these data inputs will be connected to the output.

Unlike encoder and decoder, there are n selection lines and 2n input lines. So, there is a total
of 2N possible combinations of inputs. A multiplexer is also treated as Mux.

There are various types of the multiplexer which are as follows:

2×1 Multiplexer:
In 2×1 multiplexer, there are only two inputs, i.e., A0 and A1, 1 selection line, i.e., S0 and single
outputs, i.e., Y. On the basis of the combination of inputs which are present at the selection line
S0, one of these 2 inputs will be connected to the output. The block diagram and the truth table
of the 2×1 multiplexer are given below.

BLOCK DIAGRAM
Truth Table:

The logical expression of the term Y is as follows:

Y=S0'.A0+S0.A1

Logical circuit of the above expression is given below:

4×1 Multiplexer:
In the 4×1 multiplexer, there is a total of four inputs, i.e., A0, A1, A2, and A3, 2 selection lines, i.e.,
S0 and S1 and single output, i.e., Y. On the basis of the combination of inputs that are present at
the selection lines S0 and S1, one of these 4 inputs are connected to the output. The block
diagram and the truth table of the 4×1 multiplexer are given below.

Block Diagram:
Truth Table:

The logical expression of the term Y is as follows:Y=S1' S0'

A0+S1' S0 A1+S1 S0' A2+S1 S0 A3

Logical circuit of the above expression is given below:

8 to 1 Multiplexer
In the 8 to 1 multiplexer, there are total eight inputs, i.e., A0, A1, A2, A3, A4, A5, A6, and A7, 3
selection lines, i.e., S0, S1and S2 and single output, i.e., Y. On the basis of the combination of
inputs that are present at the selection lines S0, S1, and S2, one of these 8 inputs are
connected to the output. The block diagram and the truth table ofthe 8×1 multiplexer are
given below.

Block Diagram:
Truth Table:

The logical expression of the term Y is as follows:

Y=S0'.S1'.S2'.A0+S0.S1'.S2'.A1+S0'.S1.S2'.A2+S0.S1.S2'.A3+S0'.S1'.S2 A4+S0.S1'.S2 A5+S0'.S1.S2

.A6+S0.S1.S3.A7

Logical circuit of the above expression is given below:

8 ×1 multiplexer using 4×1 and 2×1 multiplexer
We can implement the 8×1 multiplexer using a lower order multiplexer. To implement the 8×1
multiplexer, we need two 4×1 multiplexers and one 2×1 multiplexer. The 4×1 multiplexer has 2
selection lines, 4 inputs, and 1 output. The 2×1 multiplexer has only1 selection line.

For getting 8 data inputs, we need two 4×1 multiplexers. The 4×1 multiplexer produces one
output. So, in order to get the final output, we need a 2×1 multiplexer. The block diagram of
8×1 multiplexer using 4×1 and 2×1 multiplexer is given below.

16 to 1 Multiplexer
In the 16 to 1 multiplexer, there are total of 16 inputs, i.e., A0, A1, …, A16, 4 selection lines, i.e., S0,
S1, S2, and S3 and single output, i.e., Y. On the basis of the combination of inputs that are
present at the selection lines S0, S1, and S2, one of these 16 inputs will be connected to the
output. The block diagram and the truth table of the 16×1

Block Diagram:
Truth Table:
The logical expression of the term Y is as follows:

Y=A0.S0'.S1'.S2'.S3'+A1.S0'.S1'.S2 '.S3+A2.S0'.S1'.S2.S3'+A3.S0'.S1 '.S2.S3+A4.S0'.S1.S2'.S3'+A

5.S0 '.S1.S2'.S3+A6.S1.S2.S3'+A7.S0 '.S1.S2.S3+A8.S0.S1'.S2'.S3'+A9 .S0.S1'.S2'.S3+Y10.S0.S1'.S
2.S3 '+A11.S0.S1'.S2.S3+A12
S0.S1.S2 '.S3'+A13.S0.S1.S2'.S3+A14.S0.S1 .S2.S3'+A15.S0.S1.S2'.S3

Logical circuit of the above expression is given below:

16×1 multiplexer using 8×1 and 2×1 multiplexer

We can implement the 16×1 multiplexer using a lower order multiplexer. To implementthe
8×1 multiplexer, we need two 8×1 multiplexers and one 2×1 multiplexer. The 8×1
multiplexer has 3 selection lines, 4 inputs, and 1 output. The 2×1 multiplexer has only 1
selection line.

For getting 16 data inputs, we need two 8 ×1 multiplexers. The 8×1 multiplexer produces one
output. So, in order to get the final output, we need a 2×1 multiplexer. The block diagram of
16×1 multiplexer using 8×1 and 2×1 multiplexer is given below.

De-Multiplexer is a combinational circuit that performs the reverse operation of

Multiplexer. It has single input, ‘n’ selection lines and maximum of 2n outputs. The input
will be connected to one of these outputs based on the values of selection lines.
Since there are ‘n’ selection lines, there will be 2n possible combinations of zeros and ones.
So, each combination can select only one output. De-Multiplexer is also calledas De-Mux.

1x4 De-Multiplexer
1x4 De-Multiplexer has one input I, two selection lines, s1 & s0 and four outputs Y3, Y2, Y1
&Y0. The block diagram of 1x4 De-Multiplexer is shown in the following figure.
The single input ‘I’ will be connected to one of the four outputs, Y 3 to Y0 based on the values
of selection lines s1 & s0. The Truth table of 1x4 De-Multiplexer is shown below.

Selection Inputs Outputs

S1 S0 Y3 Y2 Y1 Y0

0 0 0 0 0 I

0 1 0 0 I 0

1 0 0 I 0 0

1 1 I 0 0 0

From the above Truth table, we can directly write the Boolean functions for each output
as
Y3=s1s0I�3=�1�0�
Y2=s1s0′I�2=�1�0′�
Y1=s1′s0I�1=�1′�0�
Y0=s1′s0′I�0=�1′�0′�
We can implement these Boolean functions using Inverters & 3-input AND gates. The
circuit diagram of 1x4 De-Multiplexer is shown in the following figure.

We can easily understand the operation of the above circuit. Similarly, you can
implement 1x8 De-Multiplexer and 1x16 De-Multiplexer by following the same
procedure.

Implementation of Higher-order De-Multiplexers

Now, let us implement the following two higher-order De-Multiplexers using lower- order
De-Multiplexers.

 1x8 De-Multiplexer
 1x16 De-Multiplexer
1x8 De-Multiplexer
In this section, let us implement 1x8 De-Multiplexer using 1x4 De-Multiplexers and 1x2
De-Multiplexer. We know that 1x4 De-Multiplexer has single input, two
 election lines and four outputs. Whereas, 1x8 De-Multiplexer has single input, three
selection lines and eight outputs.

So, we require two 1x4 De-Multiplexers in second stage in order to get the final eight
outputs. Since, the number of inputs in second stage is two, we require 1x2 DeMultiplexer
in first stage so that the outputs of first stage will be the inputs of second stage. Input of this
1x2 De-Multiplexer will be the overall input of 1x8 De- Multiplexer.

Let the 1x8 De-Multiplexer has one input I, three selection lines s 2, s1 & s0 and outputs Y7 to Y0.
The Truth table of 1x8 De-Multiplexer is shown below.

Selection Inputs Outputs

s2 s1 s0 Y7 Y6 Y5 Y4 Y3 Y2 Y1 Y0

0 0 0 0 0 0 0 0 0 0 I

0 0 1 0 0 0 0 0 0 I 0

0 1 0 0 0 0 0 0 I 0 0

0 1 1 0 0 0 0 I 0 0 0

1 0 0 0 0 0 I 0 0 0 0

1 0 1 0 0 I 0 0 0 0 0

1 1 0 0 I 0 0 0 0 0 0

1 1 1 I 0 0 0 0 0 0 0

We can implement 1x8 De-Multiplexer using lower order Multiplexers easily by

considering the above Truth table. The block diagram of 1x8 De-Multiplexer is shown in
the following figure.
The common selection lines, s1 & s0 are applied to both 1x4 De-Multiplexers. The outputs
of upper 1x4 De-Multiplexer are Y 7 to Y4 and the outputs of lower 1x4 De- Multiplexer are
Y3 to Y0.
The other selection line, s2 is applied to 1x2 De-Multiplexer. If s2 is zero, then one of the
four outputs of lower 1x4 De-Multiplexer will be equal to input, I based on the values of
selection lines s1 & s0. Similarly, if s 2 is one, then one of the four outputs of upper 1x4
DeMultiplexer will be equal to input, I based on the values of selectionlines s1 & s0.

1x16 De-Multiplexer
In this section, let us implement 1x16 De-Multiplexer using 1x8 De-Multiplexers and 1x2
De-Multiplexer. We know that 1x8 De-Multiplexer has single input, three selection lines
and eight outputs. Whereas, 1x16 De-Multiplexer has single input, four selection lines and
sixteen outputs.

So, we require two 1x8 De-Multiplexers in second stage in order to get the final sixteen
outputs. Since, the number of inputs in second stage is two, we require 1x2 DeMultiplexer
in first stage so that the outputs of first stage will be the inputs of

second stage. Input of this 1x2 De-Multiplexer will be the overall input of 1x16 De-
Multiplexer.

Let the 1x16 De-Multiplexer has one input I, four selection lines s 3, s2, s1 & s0 and outputs
Y 15 to Y0. The block diagram of 1x16 De-Multiplexer using lower order Multiplexers is
shown in the following figure.

The common selection lines s2, s1 & s0 are applied to both 1x8 De-Multiplexers. The outputs
of upper 1x8 De-Multiplexer are Y15 to Y8 and the outputs of lower 1x8 DeMultiplexer
are Y7 to Y 0.

The other selection line, s3 is applied to 1x2 De-Multiplexer. If s3 is zero, then one of the
eight outputs of lower 1x8 De-Multiplexer will be equal to input, I based on the values of
selection lines s2, s1 & s0. Similarly, if s3 is one, then one of the 8 outputs of upper 1x8 De-
Multiplexer will be equal to input, I based on the values of selectionlines s2, s1 & s0.
 Experiment NO.2
Q.2 Study of half adder and subtracter ?

Ans: A combinational logic circuit which is designed to add two binary digits is called
as a half adder. The half adder provides the output along with a carry value (if any). The
half adder circuit is designed by connecting an EX-OR gate and one AND gate. It has two
input terminals and two output terminals for sum and carry. The block diagram and circuit
diagram of a half adder are shown in Figure-1.

In the case of a half adder, the output of the EX-OR gate is the sum of two bits and the
output of the AND gate is the carry. Although, the carry obtained in one addition will not be
forwarded in the next addition because of this it is known as half adder.

Truth Table of Half Adder

The following is the truth table of the half-adder −

Inputs Outputs

A B S (Sum) C (Carry)

0 0 0 0

0 1 1 0

1 0 1 0

1 1 0 1
Characteristic Equations of Half-Adder
The characteristic equations of half adder, i.e., equations of sum (S) and carry (C) areobtained
according to the rules of binary addition. These equations are given below
−

The sum (S) of the half-adder is the XOR of A and B. Thus,

Sum,S=A⊕B=AB′+A′BSum,S=A⊕B=AB′+A′B
The carry (C) of the half-adder is the AND of A and B. Therefore,

Carry,C=A⋅B

A half-subtractor is a combinational logic circuit that have two inputs and two outputs (i.e.
difference and borrow). The half subtractor produces the difference between the two
binary bits at the input and also produces a borrow output (if any). In the subtraction (A-B),
A is called as Minuend bit and B is called as Subtrahend bit. The block diagram and logic
circuit diagram of the half subtractor is shown in Figure-3.

Hence, from the logic circuit diagram, it is clear that a half subtractor can be realized using
an XOR gate together with a NOT gate and an AND gate.

Truth Table of Half Subtractor

The following is the truth table the half-subtractor −

Inputs Outputs

A B d (Difference) b (Borrow)

0 0 0 0
0 1 1 1

1 0 1 0

1 1 0 0

Characteristic Equation of Half Subtractor

The characteristic equations of the half subtractor, i.e. equations of the difference (d) and
borrow output (b) are obtained by following the rules of binary subtraction. These
equations are given below −

The difference (d) of the half subtractor is the XOR of A and B. Therefore,

Difference,d=A⊕B=A′B+AB′Difference,d=A⊕B=A′B+AB′
The borrow (b) of the half subtractor is the AND of A’ (compliment of A) and B. Therefore,

Borrow,b=A′B
 Experiment NO.3
Q.3 : What is a Full Adder? Study of full Adder and subtractor ?
Ans:
A combinational logic circuit that can add two binary digits (bits) and a carry bit, and
produces a sum bit and a carry bit as output is known as a full-adder.

In other words, a combinational circuit which is designed to add three binary digits and
produces two outputs (sum and carry) is known as a full adder. Thus, a full adder circuit adds
three binary digits, where two are the inputs and one is the carry forwarded from the
previous addition. The block diagram and circuit diagram of the full adder are shown in
Figure-2.

Hence, the circuit of the full adder consists of one EX-OR gate, three AND gates andone OR
gate, which are connected together as shown in the full adder circuit in Figure-2.

Truth Table of Full Adder

The following is the truth table of the full-adder circuit −

Inputs Outputs

A B Ci n S (Sum) C (Carry)

0 0 0 0 0

0 0 1 1 0
 0 1 0 1 0

0 1 1 0 1

1 0 0 1 0

1 0 1 0 1

1 1 0 0 1

1 1 1 1 1

Hence, from the truth table, it is clear that the sum output of the full adder is equal to 1
when only 1 input is equal to 1 or when all the inputs are equal to 1. While the carry output
has a carry of 1 if two or three inputs are equal to 1.

Characteristic Equations of Full Adder

The characteristic equations of the full adder, i.e. equations of sum (S) and carry output
(Cout) are obtained according to the rules of binary addition. These equations are given
below −

The sum (S) of the full-adder is the XOR of A, B, and Cin. Therefore,

Sum,S=A⊕B⊕Cin=A′B′Cin+A′BC′in+AB′C′in+ABCinSum,S=A⊕B⊕Cin=A′B′Cin+A′BCin′+AB′
Cin′+ABCin

The carry (C) of the half-adder is the AND of A and B. Therefore,

Carry,Cout=AB+ACin+BCin

A full-subtractor is a combinational circuit that has three inputs A, B, bin and two outputs
d and b. Where, A is the minuend, B is subtrahend, bin is borrow produced by the previous
stage, d is the difference output and b is the borrow output.

Since, the half subtractor can only be used to find the difference of LSBs (Least
Significant Bits) of two binary numbers. Thus, if there is any borrow during the
subtraction of the LSBs, it will affect the subtraction of the next bits of numbers. To
overcome this problem of the half subtractor, a full subtractor is realized. The block
diagram and circuit diagram of a fullsubtractor is shown in Figure-4.
Therefore, we can realize the full-subtractor using two XOR gates, two NOT gates,two AND
gates, and one OR gate.

Truth Table of Full-Subtractor

The following is the truth table of the full-subtractor −

Inputs Outputs

A B bin d (Difference) b (Borrow)

0 0 0 0 0

0 0 1 1 1

0 1 0 1 1

0 1 1 0 1

1 0 0 1 0

1 0 1 0 0

1 1 0 0 0

1 1 1 1 1
Characteristic Equations of Full Subtractor
The characteristic equations of the full subtractor, i.e. equations of the difference (d) and
borrow output (b) are obtained by following the rules of binary subtraction. These
equations are given below −

The difference (d) of the full subtractor is the XOR of A, B, and b in. Therefore,

Difference,d=A⊕B⊕bin=A′B′bin+AB′b′in+A′Bb′in+ABbinDifference,d=A⊕B⊕bin=A′B′bi
n+AB′bin′+A′Bbin′+ABbin

The borrow (b) of the full subtractor is given by,

Borrow,b=A′B′bin+A′Bb′in+A′Bbin+ABbinBorrow,b=A′B′bin+A′Bbin′+A′Bbin+ABbin
Or

Borrow,b=A′B(bin+b′in)+(AB+A′B′)bin=A′B+(A⊕B)′binBorrow,b=A′B(bin+bin′)+(AB+A′B′
)bin=A′B+(A⊕B)′bin

Conclusion
In this tutorial, we discussed in detail about adders and subtractors in digital electronics.
We may conclude the above discussion in the following points −

 A combinational logic circuit which is designed to add two binary digits is

called as a half adder.
 A combinational logic circuit that can add two binary digits (bits) and a carry
bit, and produces a sum bit and a carry bit as output is known as afull-adder.
 A half-subtractor is a combinational logic circuit that have two inputs and two
outputs (i.e. difference and borrow).
 A full-subtractor is a combinational circuit that has three inputs A, B, binand two
outputs d and b.
Both adders and subtractors are the crucial logic circuits in arithmetic logic units of
microprocessors and microcontrollers. This is because, they perform the two most basic
arithmetic operations, i.e., addition and subtraction of binary numbers. Another important point
to note about the adder and subtractor is that they both are the combinational logic circuits,
i.e., their outputs depend on the present inputs only, butnot on the past history.
 Experiment:4
Q.4: WAP to add two 8 bit numbers and store the resultat memory
location 2000 ?
Ans: Problem – Write an assembly language program to add two 8 bit numbers
stored at address 2050 and address 2051 in 8085 microprocessor.The starting
address of the program is taken as 2000.

Algorithm –
algorithm :
1. Load the first number from memory location 2050 to
accumulator.
2. Move the content of accumulator to register H.
3. Load the second number from memory location 2051 to
accumulator.
4. Then add the content of register H and accumulator using“ADD”
instruction and storing result at 3050
5. The carry generated is recovered using “ADC” command andis
stored at memory location 3051
Program –

Memory Address Mnemonics Comment

2000 LDA 2050 A<-[2050]

2003 MOV H, A H<-A

2004 LDA 2051 A<-[2051]

2007 ADD H A<-A+H

2008 MOV L, A L←A

2009 MVI A 00 A←00

200B ADC A A←A+A+carry

200C MOV H, A H←A

200D SHLD 3050 H→3051, L→3050

 2010 HLT

Explanation –

1. LDA 2050 moves the contents of 2050 memory location tothe

accumulator.
2. MOV H, A copies contents of Accumulator to register H to A
3. LDA 2051 moves the contents of 2051 memory location tothe
accumulator.
4. ADD H adds contents of A (Accumulator) and H register (F9). The
result is stored in A itself. For all arithmetic instructions A is by
default an operand and A stores the result as well
5. MOV L, A copies contents of A (34) to L
6. MVI A 00 moves immediate data (i.e., 00) to A
7. ADC A adds contents of A(00), contents of register specified(i.e A)
and carry (1). As ADC is also an arithmetic operation, Ais by default
an operand and A stores the result as well

8. MOV H, A copies contents of A (01) to H

9. SHLD 3050 moves the contents of L register (34) in 3050
memory location and contents of H register (01) in 3051
memory location
10. HLT stops executing the program and halts any further
execution
 Experiment : 5
Q.5:WAP to multiply two 8 bit numbers stored at memory location
2000 stores the results at memorylocations 2000 and 2001 ?
Ans: Problem Statement
Write 8085 Assembly language program to multiply two 8-bit numbers stored in
memory location and store the 16-bit results into the memory.

Discussion
The 8085 has no multiplication operation. To get the result of multiplication, weshould
use the repetitive addition method.

After multiplying two 8-bit numbers it may generate 1-byte or 2-byte numbers, sowe are
using two registers to hold the result.

We are saving the data at location 8000H and 8001H. The result is storing at
location 8050H and 8051H.

Input
Address Data

... ...

8000 DC

8001 AC

... ...

Flow Diagram
 Program
Address HEX CodesLabels Mnemonics Comments

F000 21, 00, 80 LXI H,8000H Load first operand address

F003 46 MOV B, M Store first operand to B

F004 23 INX H Increase HL pair

F005 AF XRA A Clear accumulator

F006 4F MOV C, A Store 00H at register C

F007 86 LOOP ADD M Add memory element with Acc

F008 D2, 0C, F0 JNC SKIP When Carry flag is 0, skip next task

F00B 0C INR C Increase C when carry is 1

F00C 05 SKIP DCR B Decrease B register

F00D C2, 07, F0 JNZ LOOP Jump to loop when Z flag is not 1

F010 21, 50, 80 LXI H,8050H Load Destination address

F013 71 MOV M, C Store C register content into memory

F014 23 INX H Increase HL Pair

F015 77 MOV M, A Store Acc content to memory

F016 76 HLT Terminate the program

Output
Address Data

... ...

8050 93

8051 D0

. .

. .

. .
 Experiment NO.6
Q.6 Wap to add two 16-bit numbers. Store the result at
memory address starting from 2000.
Ans: Problem – Write a program to add two 16-bit numbers where
starting address is 2000 and the numbers are
at 3000 and 3002 memory address and store resultinto 3004
and 3006 memory address.

Algo-
1. Load 0000H into CX register (for carry)
2. Load the data into AX(accumulator) from memory 3000
3. Load the data into BX register from memory 3002
4. Add BX with Accumulator AX
5. Jump if no carry
6. Increment CX by 1
7. Move data from AX(accumulator) to memory 3004
8. Move data from CX register to memory 3006
9. Stop
Program –
 Memory Mnemonics Operands Comment

2000 MOV CX, 0000 [CX] <- 0000

2003 MOV AX, [3000] [AX] <- [3000]

2007 MOV BX, [3002] [BX] <- [3002]

200B ADD AX, BX [AX] <- [AX] + [BX]

200D JNC 2010 Jump if no carry

200F INC CX [CX] <- [CX] + 1

2010 MOV [3004], AX [3004] <- [AX]

2014 MOV [3006], CX [3006] <- [CX]

2018 HLT Stop

Explanation –
1. MOV is used to load and store data.
2. ADD is used to add two numbers where their one number is in
accumulator or not.
3. JNC is a 2-bit command which is used to check whether the carryis
generated from accumulator or not.
4. INC is used to increment an register by 1.
5. HLT is used to stop the program.
6. AX is an accumulator which is used to load and store the data.
7. BX, CX are general purpose registers where BX is used for storingsecond
number and CX is used to store carry.
 Experiment no.7
Q.7 Wap to which tests if any bit is “0” in a data byte specified at
an address 2000. If it is so, 00 would be stored at address 2001 and
if not so then FF should bestored the same address.
Ans:
 Experiment :8
Q.8 Assume that 3 bytes of data are stored at consective memory
address of the data memory starting at 2000. Write a program
which a program which loads register C with (2000) , i.e with data
contained at memory address 2000, D with (2001), Ewith (2002)
and A with (2001).
Ans: Problem – Write an assembly level program in 8085 microprocessorto
exchange a block of 4 bytes starting from address 2001 with data starting from
address 3001.

Algorithm –
1. Take a count equal to 4
2. Store the starting address of both blocks in 2 different registerpairs
3. Now exchange the contents at the addresses in both register pairs
4. Increment the values of both register pairs
5. Decrements count by 1
6. If count is not equal to 0
7. repeat steps 3 to 5
 MEMORY
ADDRESS MNEMONICS COMMENTS

2500 LXI D 2001 D <= 20, E <= 01

2503 LXI H 3001 H <= 20, L <= 01

2506 MVI C 04 C <= 04

2508 MOV B, M B <= M[ H-L ]

2509 LDAX D A <= M[ D-E ]

250A MOV M, A M[ H-L ] <= A

250B MOV A, B A <= B

250C STAX D M[ D-E ] <= A

250D INX H [ H-L ] <= [ H-L ] + 1

250E INX D [ D-E ] <= [ D-E ] + 1

250F DCR C C <= C – 1

JUMP TO 2508 IF C NOT EQUAL

2510 JNZ 2508
TO 0

2513 HLT STOP THE PROGRAM

Explanation –
1. LXI D 2001 – Loads register pair, that is in this case, D=20 andE=01
LXI H 3001 – H=30 and L=01
2. MVI C 04 – Assigns immediate data, eg.- here C=04MVI A
45 – assigns A(accumulator) with 45, A=45
3. MOV B, M – Here M is the data in H – L register pair and it servesas an
address. Copies content at address stored in M to register B

4. LDAX D – Here Accumulator is loaded with the data stored at

address formed by register pair D – E
5. MOV M, A – Here A’s content is copied to address which is storedin M.
MOV A, B – Copies content of register B to A
6. STAX D – Stores the content of A (accumulator) in the address
 formed by register pair D – E.
7. INX H – Increment the content of register pair H – L
8. INX H – Increment the content of register pair D – E
9. DCR C – Decrements the content of register C
10. JNZ 2508 – If value of register C is not equal to 0 then jump toaddress
2508
11. HLT – Stop execution of program
 Experiment : NO.9
Q.9 sixteen bytes of data are specified at consecutive
data-memory location starting at 2000. Write a program
which incerement the values of all sixteen bytes 01 ?
Ans: Increment by 1 (inc)
inc{bwl} r/m[8|16|32]
Operation

r/m[8|16|32] + 1 -> r/m[8|16|32]

Description

Adds 1 to the operand and does not change the carry flag. Use the
add instruction with an immediate value of 1 to change the carry
flag.
Example

Add 1 to the contents of the byte at the effective address

(addressed by the ESI register plus an offset of 1):
incb 1(%esi)

Add 1 to the 16-bit contents of the AX register:

incw %ax

Add 1 to the 32-bit contents at the effective address

(addressed by the EDI register):
incl 4(%edi)
 Experiment no.10
Q.10 Wap to add 10 bytes stored at memory location starting from
3000 storethe result at memory location 300A ?
Discussion
The data are stored at location 8010H to 8019H and 9010H to 9019H. The location 8000H
is holding the number of bytes to exchange. In this case number of bytes are 10D so it will
be 0AH.

The logic is very simple, The HL and DE register pair is pointing the first and second data
block respectively. By taking the data we are just swapping the values of each memory
locations. Then repeating this process to swap two blocks completely.

Input
Address Data

... ...

8000 0A

... ...

8010 00

8011 11

8012 22

8013 33
Address Data

8014 44

8015 55

8016 66

8017 77

8018 88

8019 99

... ...

9010 84

9011 63

9012 12

9013 47

9014 48

9015 AD

9016 BC

9017 2A

9018 8F

9019 99

... ...
Flow Diagram
Program
Address HEX Codes Labels Mnemonics Comments

F000 21, 10, 80 LXI H, 8000H Point 8000Hto get byte count

F003 4E MOV C, M Load Count from memory

F004 21, 10, 80 LXI H,8010H Point first block address

F007 11, 10, 90 LXI D,9010H Point second block address

F00A 46 LOOP MOV B, M Take element from first block to B

F00B 1A LDAX D Take element from second block to Acc

F00C 77 MOV M, A Store Acc content to second block

F00D 78 MOV A, B Load B to A

F00E 12 STAX D Store into second block

F00F 23 INX H Point to next address of first block

F010 13 INX D Point to next address of second block

F011 0D DCR C Decrease the count variable

F012 C2, 0A, F0 JNZ LOOP When block is not completed, jump to LOOP

F015 76 HLT Terminate the program

Output
Address Data

... ...

8010 84
Address Data

8011 63

8012 12

8013 47

8014 48

8015 AD

8016 BC

8017 2A

8018 8F

8019 99

... ...

9010 00

9011 11

9012 22

9013 33

9014 44

9015 55

9016 66

9017 77

Address Data

9018 88