8085 microprocessor

microprocessing interface
8085 microprocessor

what is 8085 microprocessor

The Intel 8085 is an 8-bit microprocessor introduced by
Intel in 1977. It was binary compatible with the more-
famous Intel 8080 but required less supporting
hardware, thus allowing simpler and less expensive
microcomputer systems to be built.

8085 is pronounced as "eighty-eighty-five"

microprocessor. It is an 8-bit microprocessor designed
by Intel in 1977 using NMOS technology
 Features of 8085
• 8-bit microprocessor i.e. accepts 8-bit data simultaneously
• Single-chip N-MOS device implemented with 6500 transistors
• Require single +5V power supply
• Clock frequency in the range of 3MHz-5MHz
• 8-bit data bus and 16-bit address bus
• 74 instructions with the following addressing modes: Register, direct, immediate, indirect, and implied
• Provides 16 address lines hence access 64K Bytes of memory, program as well as data memory
• Provides 5 hardware interrupts TRAP, RST 7.5, RST 6.5, RST 5.5, and INTR.
• Provides on-chip clock generator hence does not require external clock generator
 Features of 8085
• Provides on-chip clock generator hence does not require external clock generator
• Perform arithmetic and logical operations
• Provides control signals to control the bus cycles
• Provides two serials I/O lines with SOD and SID hence serial peripherals can be interfaced
with 8085 directly
• Supports mechanism that allows 8085 to increase its interrupt handling capacity
• Provides 8-bit accumulator , flag register , 6 general-purpose register(B,C,D,E,H,L) , 2
special purpose 16- bit registers(SP,PC)
• The data bus(D0-D7) multiplexed with lower 8-bit address bus(A0-A7) hence requires
external hardware to separate data lines from the address linee.
8085 Pin Diagram

The 8085 pin diagram consists of 40 pins of

the microprocessor. The pins can be
categorized into six groups-address and
data bus, control signals, status signals,
power supply, and serial input/output ports
 8085 Pin Diagram

X1 AND X2 Address Bus (or) Data

Bus (AD0-AD7)
Represent the crystal oscillator which will provide
The address bus pins or data bus pins range from AD0 to AD7,
frequency for the microprocessor.They are
and these pins are called multiplexing lines that can do both
associated with the exterior oscillator for generating
addresses as well as data transfer.
the required as well as appropriate operation of a
clock.
Address Bus (A8-A15) Address Latch Enable (ALE)

The address bus pins range from A8 to A15 The address bus pins or data bus pins range from
and these pins do the data transfer only. AD0 to AD7, and these pins are called
. multiplexing lines that can do both addresses as
well as data transfer.
 Cont...

Status Signal (IO/M) Status Signals (S0-S1)

It tells us whether the address is intended for

memory or input/output. In the case when we get The status signals S0, and S1 give different
a positive signal it represents that we have got i/o functions as well as status based on their status.
read or i/o write and when we get a negative
signal it represents memory activation

RD WR
The RD is an energetic low signal and it is used for
controlling the microprocessor READ operation. It has the power to control the microprocessor’s write
When the RD pin goes small then the 8085 operations. When the WR pin goes small the data will
microprocessor understands the information from be written to the I/O device or memory.
the I/O device or memory.
.
 Cont....

READY HOLD

The READY pin is for ensuring whether a device

is set for accepting or transferring data. When The HOLD pin specifies when any device is demanding the
the pin is high the device is ready for transfer, if use of an address as well as a data bus.
it is not then the microprocessor stays until this
pin goes high.

HLDA
INTA
Itis the response signal of HOLD and is
used to specify whether this signal is INTA stands for interrupt acknowledgement.
obtained or not. This signal will go low Whenever an interrupt signal comes, then it should
after the implementation of HOLD demand. be recognized by INTA. It is an active-low signal tha
. is for zero it will process and for one it won’t.
 Continued.

RST 5.5, RST 6.5, RST 7.5 TRAP

These are the restart maskable interrupts or TRAP is a non-maskable interrupt, and it
Vectored Interrupts which are used for the doesn’t allow or stop a program. TRAP has
insertion of an inner restart function repeatedly. maximum precedence between interrupts.
All these interrupts are maskable.
.
RESET IN

RST (RESET) OUT

It is used to reset the program counter toward
zero. It also rearranges interrupt enable as It will reset all the devices connected to the
well as HLDA flip-flops (FFs). microprocessor.
 Continued.

SID & SOD

CLK

This is the 19th pin in the 8085 Pin Diagram in Microprocessor.

This is the 30th pin in the 8085 Pin Diagram in
Sometimes CLK signal has to be generated from microprocessors that
Microprocessor. These two pins are used for serial can be used in favour of other peripherals or else other digital
data communication. In the serial input data, the integrated circuits. This is offered with a CLK pin.
information is uploaded into the 7th bit of the
accumulator while RIM instruction is performed.
RIM(Read interrupt mask) verifies whether the
VSS and VCC
interrupt is covered or not covered. In the serial
o/p data the output of the data is sent toward the This is the 31st pin in the 8085 Pin Diagram in
7th bit of the accumulator whenever an Microprocessor. VSS is a ground pin whereas Vcc is
instruction of SIM is performed. a +5v pin.
Architecture of 8085
Registers in 8085 microprocessor

A. General Purpose Registers

The 8085 has six general-purpose registers to store 8-bit data; these are
identified as- B, C, D, E, H, and L. These can be combined as register pairs – BC, DE,
and HL, to perform some 16-bit operation. These registers are used to store or
copy temporary data, by using instructions, during the execution of the program.

B. Specific Purpose Registers

: The accumulator is an 8-bit register (can store 8-bit data) that is the
part of the arithmetic and logical unit (ALU). After performing arithmetical or
logical operations, the result is stored in accumulator. Accumulator is also defined
as register A.
Registers in 8085 microprocessor

B. Specific Purpose Registers

. registers: The flag register is a special purpose register and it is completely
Flag
different from other registers in microprocessor. It consists of 8 bits and only 5 of
them are useful. The other three are left vacant and are used in the future Intel
versions.These 5 flags are set or reset (when value of flag is 1, then it is said to be
set and when value is 0, then it is said to be reset) after an operation according to
data condition of the result in the accumulator and other registers. The 5 flag
registers are:
Registers in 8085 microprocessor
Flag registers
• Sign Flag: It occupies the seventh bit of the flag register, which is also known as the
most significant bit. It helps the programmer to know whether the number stored in
.
the accumulator is positive or negative. If the sign flag is set, it means that number
stored in the accumulator is negative, and if reset, then the number is positive.
• Zero Flag: It occupies the sixth bit of the flag register. It is set, when the operation
performed in the ALU results in zero(all 8 bits are zero), otherwise it is reset. It helps
in determining if two numbers are equal or not.
Registers in 8085 microprocessor
Flag registers
• Auxiliary Carry Flag: It occupies the fourth bit of the flag register. In an arithmetic
operation, when a carry flag is generated by the third bit and passed on to the fourth
.
bit, then Auxiliary Carry flag is set. If not flag is reset. This flag is used internally for
BCD(Binary-Coded decimal Number) operations. Note – This is the only flag register
in 8085 which is not accessible by user.
• Parity Flag: It occupies the second bit of the flag register. This flag tests for number of
1’s in the accumulator. If the accumulator holds even number of 1’s, then this flag is
set and it is said to even parity. On the other hand if the number of 1’s is odd, then it
is reset and it is said to be odd parity.
• Carry Flag: It occupies the zeroth bit of the flag register. If the arithmetic operation
results in a carry(if result is more than 8 bit), then Carry Flag is set; otherwise it is
reset
Registers in 8085 microprocessor

• Sign Flag (7th bit): It is reset(0), which means number stored in

. the accumulator is positive.
• Zero Flag (6th bit): It is reset(0), thus result of the operations
performed in the ALU is non-zero.
• Auxiliary Carry Flag (4th bit): We can see that b3 generates a
carry which is taken by b4, thus auxiliary carry flag gets set (1).
• Parity Flag (2nd bit): It is reset(0), it means that parity is odd. The
accumulator holds odd number of 1’s.
• Carry Flag (0th bit): It is set(1), output results in more than 8 bit.
Registers in 8085 microprocessor

C. Memory Registers
.There are two 16-bit registers used to hold memory addresses. The size of these
registers is 16 bits because the memory addresses are 16 bits. They are :-

• Program Counter: This register is used to sequence the execution of the

instructions. The function of the program counter is to point to the memory
address from which the next byte is to be fetched. When a byte (machine code) is
being fetched, the program counter is incremented by one to point to the next
memory location.
• Stack Pointer: It is used as a memory pointer. It points to a memory location in
read/write memory, called the stack. It is always incremented/decremented by 2
during push and pop operation.
 Interruption
q An interrupt is a signal that temporarily suspends the normal execution of a program and redirects the control to a
specific interrupt service routine.
q Interrupts allow the microprocessor to respond to external events, such as user input, system events, or hardware
signals, without the need for constant polling.
There are five interrupt signals
1. TRAP: It is a non-maskable interrupt that is generated by an external device, . highest priority and cannot be
disabled.
2. RST 7.5:- It is maskable interrupt that is generated by a software instruction. It has the second highest priority.
3. RST 6.5:- It is maskable interrupt that is generated by a software instruction. It has the third highest priority.
4. RST 5.5:- It is a maskable interrupt that is generated by a software instruction. It has the fourth highest priority.
5. INTR:- maskable interrupt that is generated by an external device, such as a keyboard or a mouse.
Types Interruption
 Classification of Interrupts
Interrupts Can be classified into Two types

1. Maskable interrupts
Maskable Interrupts are those which can be disabled or ignored by the microprocessor.
These interrupts are either edge-triggered or level-triggered, so they can be disabled.
INTR, RST 7.5, RST 6.5, RST 5.5 are maskable interrupts in 8085 microprocessor.

2. Non-Maskable interrupts
Non-Maskable Interrupts are those which cannot be disabled or ignored by microprocessor.
TRAP is a non-maskable interrupt.
It consists of both level as well as edge triggering and is used in
critical power failure conditions.
8085 Pin Diagram
Timing Diagrams of 8085

• It is one of the best way to understand to process of micro-

processor/controller. With the help of timing diagram we can understand
the working of any system, step by step working of each instruction and its
execution, etc.
• It is the graphical representation of process in steps with respect to time.
The timing diagram represents the clock cycle and duration, delay, content
of address bus and data bus, type of operation ie. Read/write/status
signals.
Timing Diagrams of 8085 cont.

Important terms related to timing diagrams:

1. Instruction cycle: this term is defined as the number of steps required by the cpu
to complete the entire process i.e Fetching and execution of one instruction. The
fetch and execute cycles are carried out in synchronization with the clock.
2. Machine cycle: It is the time required by the microprocessor to complete the
operation of accessing the memory devices or I/O devices. In machine cycle various
operations like opcode fetch, memory read, memory write, I/O read, I/O write are
performed.
3. T-state: Each clock cycle is called as T-states.
status signal and meaning

.
Opcode fetch Operation:
§ During T1 state, microprocessor uses IO/M’,
S0, S1 signals are used to instruct
microprocessor to fetch opcode.
§ Thus when IO/M(bar)=0, S0=S1= 1, it
indicates opcode fetch operation.
§ During this operation 8085 transmits 16-bit
address and also uses ALE signal for address
latching.
§ At T2 state microprocessor uses read signal
and make .data ready from that memory
location to read opcode from memory and at
the same time program counter increments
by 1 and points next instruction to be fetched.
Opcode fetch Operation:
§ In this state microprocessor also checks
READY input signal, if this pin is at low logic
level ie. '0' then microprocessor adds wait state
immediately between T2 and T3.
§ At T3, microprocessor reads opcode and store
it into instruction register to decode it further.
§ During T4 microprocessor performs internal
operation like decoding opcode and providing
necessary actions.
§ The opcode is decoded to know whether T5
.
or T6 states are required, if they are not
required then microprocessor performs next
operation.
Memory Write:

Operation:
§ It is used to send one byte into memory.
§ During T1, ALE is high and contains lower address
A0-A7 from AD0-AD7.
§ A8-A15 contains higher byte of address.
§ As it is memory operation, IO/M(bar) goes low.
§ During T2, ALE goes low, WR(bar) goes low and
Address is removed from AD0-AD7 and then data
appears on. AD0-AD7.
§ Data remains on AD0-AD7 till WR(bar) is low.
Memory Read: Operation:
§ It is used to fetch one byte from the memory.
§ It can be used to fetch operand or data from the
memory.
§ During T1, A8-A15 contains higher byte of address.
At the same time ALE is high. Therefore Lower byte
of address A0-A7 is selected from AD0-AD7.
§ Since it is memory read operation, IO/M(bar) goes
low.
§ During T2 ALE goes low, RD(bar) goes low. Address
is removed from AD0-AD7 and data D0-D7 appears
on AD0-AD7..
§ During T3, Data remains on AD0-AD7 till RD(bar) is
at low signal
IO Read: Operation:
§It is used to fetch one byte from an IO port.
§During T1, The Lower Byte of IO address is
duplicated into higher order address bus A8-
A15.
§ALE is high and AD0-AD7 contains address
of IO device.
§IO/M (bar) goes high as it is an IO operation.
§During T2, ALE goes low, RD (bar) goes low
and data appears on AD0-AD7 as input from
IO device..
§During T3 Data remains on AD0-AD7 till
RD(bar) is low.
IO Write:
Operation:
§It is used to write one byte into IO device.
§During T1, the lower byte of address is duplicated
into higher order address bus A8-A15.
§ALE is high and A0-A7 address is selected from
AD0-AD7.
§As it is an IO operation IO/M (bar) goes low.
§During T2, ALE goes low, WR (bar) goes low and
data appears on AD0-AD7 to write data into IO
device.
§During T3, Data remains on AD0-AD7 till WR(bar) is
low. .
Group Member:

Name ID
1. Segni Asrat.........................................................................9997/19
2.Bezawit Habte.....................................................................8164/19
3.Estifanos Alebel...................................................................0671/19
4. Birhanu Esubalew...............................................................9799/19
5.Eden Melese........................................................................5852/19
6.Jaber Kemal.........................................................................7355/19
.
 DILLA UNIVERSITY

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