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Handler's Classification

The document describes Handler's classification system for describing computer architectures. It uses three pairs of integers separated by operators to describe three levels of a computer: the processor control unit, bit-level circuit, and arithmetic logic unit. The classification system can describe features like pipelining, parallelism, and different operating modes. Examples are given applying the classification system to describe the CDC 6600, Texas Instruments ASC, and Cray-1 computer architectures in detail.

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2K views

Handler's Classification

The document describes Handler's classification system for describing computer architectures. It uses three pairs of integers separated by operators to describe three levels of a computer: the processor control unit, bit-level circuit, and arithmetic logic unit. The classification system can describe features like pipelining, parallelism, and different operating modes. Examples are given applying the classification system to describe the CDC 6600, Texas Instruments ASC, and Cray-1 computer architectures in detail.

Uploaded by

Harsh
Copyright
© © All Rights Reserved
Available Formats
Download as DOCX, PDF, TXT or read online on Scribd
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Handler's Classification

In 1977, Wolfgang Handler proposed an detailed notation for expressing the


parallelism and pipelining of computers. Handler's classification addresses the
computer at three distinct stages:

o Processor control unit (PCU),


o Bit-level circuit (BLC),
o Arithmetic logic unit (ALU),

The Processor control unit corresponds to a processor or CPU, the BLC


corresponds to the logic circuit needed to perform one- bit operations in the ALU
and the arithmetic logic unit corresponds to a functional unit or a processing
element.

Handler's classification uses the following three pairs of integers to explain a


computer: Computer = (p * p', a * a', b * b')

Whereas, p = number of PCUs

Whereas, p'= number of PCUs that can be pipelined

Whereas, a = number of ALUs controlled by each PCU

Where a'= number of ALUs that can be pipelined

Whereas, b = number of bits in ALU or processing element (PE) word

Whereas, b'= number of pipeline segments on all ALUs or in a single PE

The following operators and rules are used to show the relationship between a
variety of elements of the computer:

o The '*' operator is used to indicate that the units are pipelined or macro-
pipelined with a stream of data running through all the units.
o The '+' operator is used to denote that the units are not pipelined but work on
independent streams of data.
o The 'v' operator is used to denote that the computer hardware can work in
one of numerous modes.
o The '~' symbol is used to specify a range of values for any one of the
parameters.
o Peripheral processors are given away before the main processor using
another three pairs of integers. If the given value of the second element of
any pair is 1, it may be misplaced for brevity.

Handler's classification is the best elaborate by showing how the operators and
rules are used to classify numerous machines.

The CDC 6600 has only a single main processor supported by 10 I/O processors.
One control unit managed one ALU with a 60-bit word length. The ALU has 10
functional units which can be produced into a pipeline. The 10 peripheral I/O
processors may work in parallel with the CPU and with each other also. Every  I/O
processor contains one 12-bit ALU. The explanation for the 10 I/O processors is:

                      CDC 6600I/O = (10, 1, 12)

The explanation for the main processor is:

                      CDC 6600main = (1, 1 * 10, 60)

The I/O processors and the main processor can be regarded as forming a macro-
pipeline so the '*' operator is used to join the two structures:

CDC 6600 =  (central processor) *(I/O processors) =  (10, 1, 12) * (1, 1 * 10, 60)

Texas Instrument's Advanced Scientific Computer (ASC) have one controller


coordinating four arithmetic units. Every arithmetic unit is an eight stage pipeline
with 64-bit words. Therefore, we have:
                                    ASC = (1, 4, 64 * 8)

The Cray-1 is a 64-bit single processor computer whose ALU has twelve
functional units, eight of which can be joined together to from a pipeline.
Dissimilar functional units have from 1 to 14 segments, which can be pipelined
also. Handler's description of the Cray-1 is:

                                   Cray-1 =  (1, 12 * 8, 64 * (1 ~ 14))The '+'  and '*'operators


are used to join several separate pieces of hardware. The 'v' operator is of a
dissimilar form to the other two in that it is used to join the different operating
modes of a one piece of hardware.

While Flynn's classification is simple to use, Handler's classification is


cumbersome. The straight use of numbers in the nomenclature of Handler's
classification's build it much more abstract and hence hard.

Handler's classification is extremely geared towards the description of chains and


pipelines. While it is well able to explain the parallelism in a single processor, the
range of parallelism in multiprocessor computers is not addressed well.

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