Verilog HDL

VERILOG
• a HARDWARE DESCRIPTION LANGUAGE (HDL).
• Verilog, standardized as IEEE 1364, is a hardware description language (HDL)
used to model electronic systems.
• Used for describing a digital system (a memory or a microprocessor).
• Describe any digital hardware at any level using a HDL.
• Designs, which are described in HDL are independent of technology, very easy
for designing and debugging, and are normally more useful than schematics,
particularly for large circuits.
• Verilog supports a design at many levels of abstraction (The amount of
complexity by which a system is viewed or programmed).
• The major three are −
- Behavioral level
- Register-transfer level
- Gate level

 Programming Language. Verilog is case sensitive. All the key words are in
lower case.
• Behavioral level
- describes a system by concurrent algorithms (Behavioural).
- Every algorithm consists of a set of instructions that are executed one by one. A
module can be implemented in terms of the design algorithm.
- Functions, tasks and blocks are the main elements.
- This is the highest level of abstraction. The designer no need to have any
knowledge of hardware implementation.
• Register−Transfer Level
- Designs using the Register−Transfer Level specify the characteristics of a circuit
using operations and the transfer of data between the registers.
- RTL is a design abstraction which models a digital circuit in terms of the flow of
digital signals (data) between hardware registers, and the logical operations
performed on those signals.
- Commonly used for a combination of dataflow modeling and behavioral
modeling.
• Gate Level
- The module is implemented in terms of logic gates and interconnections
between these gates. Designer should know the gate-level diagram of the
design.
- All signals are discrete signals. They can only have definite logical values
(`0', `1', `X', `Z`).
- The usable operations are predefined logic primitives (basic gates).
- Gate level code is generated using tools like synthesis tools and its netlist is
used for gate level simulation and for backend.
- Gate-level modeling is used for implementing lowest level modules in a
design like, full-adder, multiplexers, etc. Verilog HDL has gate primitives for
all basic gates.
• Comments
There are two forms to represent the comments
- Single line comments begin with the token // and end with carriage return.
Ex.: //this is single line syntax
- - Multiline comments begins with the token /* and end with token */
- Ex.: /* this is multiline Syntax*/

• Numbers
- specify a number in binary, octal, decimal or hexadecimal format.
- Negative numbers are represented in 2’s compliment numbers.
- Verilog allows integers, real numbers and signed & unsigned numbers.
- The syntax is given by − <size> <radix> <value>
- Size or unsized number can be defined in <Size> and <radix> defines
whether it is binary, octal, hexadecimal or decimal.
• Identifiers
- Identifier is the name used to define the object, such as a function, module or
register.
- Identifiers should begin with an alphabetical characters or underscore
characters. Ex. A_Z, a_z,_
- Identifiers are a combination of alphabetic, numeric, underscore and $
characters. They can be up to 1024 characters long.

• Operators
- Operators are special characters used to put conditions or to operate the
variables.
- There are one, two and sometimes three characters used to perform
operations on variables. Ex. >, +, ~, &! =.
• Verilog Keywords
- Words that have special meaning in Verilog are called the Verilog keywords.
- For example, assign, case, while, wire, reg, and, or, nand, and module.
- They should not be used as identifiers.
- Verilog keywords also include compiler directives, and system tasks and functions.
• Parameter
- A parameter defines a constant that can be set when you instantiate a module. This
allows customization of a module during instantiation.
 DATA TYPES IN VERILOG
- Verilog supports only predefined data types.
- Include bits, bit-vectors, memories, integers, reals, events, and strength types.
- Verilog deals mainly in the domain of bits and bytes while describing the circuits.
- The real type is useful for delays and time and is also useful in higher level modeling such
as stochastic analysis and digital signal processing algorithms.
- The hardware types include net and reg types, (in general, can be seen as wires and
registers).
- Nets are continuously driven from continuous assignments or from structural elements
such as module ports, gates, transistors or user defined primitives.
- Regs are driven strictly from behavioral blocks.
- Nets are typically implemented as wires in hardware and regs may either be wires, or
temporaries or flip-flops (registers).
• Value Set
- Verilog consists of, mainly, four basic values. All Verilog data types, which are
used in Verilog store these values −
- bits and integers(32 bits), time (64 bits) : bit-vectors and integers can be
freely intermixed.
- Integers are defined to be 32 bits.
- Time values are 64 bits.
- The bits actually are of two types as :
- 4-state values or logic values (0,1,x,z);
0 (logic zero, or false condition) , 1 (logic one, or true condition)
x (unknown logic value) , z (high impedance state)
use of x and z is very limited for synthesis.
- 128-state types or floating point types (real numbers)
• Character strings
- Delay values
 These are single, double, triplet or n-tuple indicating rise, fall any other
transition delay transition values – (01) - change from 0 to 1.
 These may in user-define primitives or specify blocks Boolean/conditional
values – true /false OR 0/1 units.
• Wire
- used to represent a physical wire in a circuit and it is used for connection
of gates or modules.
- The value of a wire can only be read and not assigned in a function or
block.
- A wire cannot store value but is always driven by a continuous assignment
statement or by connecting wire to output of a gate/module.
Other specific types of wires are −
Wand (wired-AND) − here value of Wand is dependent on logical AND of all
the device drivers connected to it.
Wor (wired-OR) − here value of a Wor is dependent on logical OR of all the
device drivers connected to it.
Tri (three-state) − here all drivers connected to a tri must be z, except only one
(which determines value of tri).
 OPERATORS
• Arithmetic Operators
- These perform arithmetic operations.
- The + and - can be used as either unary (-z) or binary (x-y) operators.
Operators
+ (addition) - (subtraction)
* (multiplication) / (division)
% (modulus)
• Logical Operators
- Logical operators return a single bit 1 or 0.
- They can work on expressions, integers or groups of bits, and treat all values that are
nonzero as “1”. Logical operators are typically used in conditional (if ... else) statements
since they work with expressions.
Operators
! (logical NOT)
&& (logical AND)
|| (logical OR)
• Relational Operators
- Relational operators compare two operands and return a single bit 1or 0.
- These operators synthesize into comparators.
- Wire and reg variables are positive ; thus (-3’b001) = = 3’b111
Operators
< (less than) <= (less than or equal to)
> (greater than) >= (greater than or equal to)
== (equal to) != (not equal to)

• Shift Operators
- Shift operators shift the first operand by the number of bits specified by the second operand.
- Vacated positions are filled with zeros for both left and right shifts.
Operators
<< (shift left)
>> (shift right)
 MODULES
• Module Declaration
- A module is the principal design entity in Verilog.
- The first line of a module declaration specifies the name and port list (arguments).
- The next few lines specifies the i/o type (input, output or inout) and width of each port.
- The default port width is 1 bit. Then the port variables must be declared wire, wand,. . ., reg.
The default is wire.
- Typically inputs are wire since their data is latched outside the module.
- Outputs are type reg if their signals were stored inside an always or initial block.

Syntax
module module_name (port_list);
input [msb:lsb] input_port_list;
output [msb:lsb] output_port_list;
inout [msb:lsb] inout_port_list;
... statements ...
endmodule
• Module Instantiations
- Module declarations are templates from which one creates actual objects (instantiations).
- Modules are instantiated inside other modules, and each instantiation creates a unique object
from the template.
- The exception is the top-level module which is its own instantiation.
- The instantiated module’s ports must be matched to those defined in the template.
- This is specified:
(i) by name, using a dot(.) “ .template_port_name (name_of_wire_connected_to_port )”. or
(ii) by position, placing the ports in exactly the same positions in the port lists of both the
template and the instance.
Syntax for Instantiation
module_name
instance_name_1 (port_connection_list),
instance_name_2 (port_connection_list),
.......
instance_name_n (port_connection_list);
• Continuous Assignment
- The continuous assignment is used to assign a value onto a wire in a module.
- It is the normal assignment outside of always or initial blocks.
- Continuous assignment is done with an explicit assign statement or by assigning a value to
a wire during its declaration.
- Note that continuous assignment statements are concurrent and are continuously executed
during simulation.
- The order of assign statements does not matter.
- Any change in any of the right-hand-side inputs will immediately change a left-hand-side
output.

Syntax
wire wire_variable = value;
assign wire_variable = expression;
• Procedural Assignments
- Verilog procedural statements are used to model a design at a higher level of abstraction than
the other levels.
- They provide powerful ways of doing complex designs.
- However small changes n coding methods can cause large changes in the hardware
generated.
- Procedural statements can only be used in procedures.
- Procedural assignments are assignment statements used within Verilog procedures (always
and initial blocks).
- Only reg variables and integers can be placed left of the “=” in procedures.

Syntax for Procedural Assignment

variable = expression
• for Loops
- Similar to for loops in C/C++, they are used to repeatedly execute a statement or block of
statements.
- If the loop contains only one statement, the begin ... end statements may be omitted.

Syntax
for (count = value1;
count />= value2;
count = count +/- step)
begin
... statements ...
end
• while Loops
- The while loop repeatedly executes a statement or block of statements until
the expression in the while statement evaluates to false.
- To avoid combinational feedback during synthesis, a while loop must be
broken with an @(posedge/negedge clock) statement.
- If the loop contains only one statement, the begin ... end statements may be
omitted.
Syntax
while (expression)
begin
... statements ...
end
• if ... else if ... Else
- The if ... else if ... else statements execute a statement or block of statements depending on the result of the
expression following the if.
- If the conditional expressions in all the if’s evaluate to false, then the statements in the else block, if present, are
executed.
- There can be as many else if statements as required, but only one if block and one else block.
- If there is one statement in a block, then the begin .. end statements may be omitted.
- Both the else if and else statements are optional.
Syntax
if (expression)
begin
... statements ...
end
else if (expression)
begin
... statements ...
end
... more else if blocks ...
else
begin
... statements ...
end
• Case
- The case statement allows a multipath branch based on comparing the expression with a list of case choices.
- Statements in the default block executes when none of the case choice comparisons are true .
- If no comparisons , including default, are true, synthesizers will generate unwanted latches.
- If the defaults are dont cares, define them as ‘x’ and the logic minimizer will treat them as don’t cares.
Case choices may be a simple constant or expression, or a comma-separated list of same.
Syntax
case (expression)
case_choice1:
begin
... statements ...
end
case_choice2:
begin
... statements ...
end
... more case choices blocks ...
default:
begin
... statements ...
end
endcase
• Gate Level modeling
- Design a logic circuit using basic logic gates with Gate level modeling.
- Verilog supports coding circuits using basic logic gates as predefined
primitives. These primitives are instantiated like modules except that they are
predefined in Verilog and do not need a module definition.
Verilog code for AND gate using gate-level modeling
The code for the AND gate would be as follows.
module AND_2(output Y, input A, B);
The module command tells the compiler that we are creating something which
has some inputs and outputs. AND_2 is the identifier.
Identifiers are how we name the module.
The list in parenthesis is the port list containing input and output ports.
Then we write: module AND_2(output Y, input A, B);
and(Y, A, B); and(Y, A, B);
endmodule; endmodule
• Data flow modeling
- Compared to gate-level modeling, dataflow modeling in Verilog is a higher level of
abstraction. i.e. you don’t really need to know the circuit design.
- Because gate-level modeling becomes very complicated for a complex circuit.
Hence dataflow modeling is a very important way of implementing the design.
- One need to know is the Boolean logic equation of the output of the circuit in terms
of its inputs.
- Use continuous assignments in dataflow modeling in most of the designs.
- The continuous assignments are made using the keyword assign.
Verilog code for AND gate using data-flow modeling
module AND_2_data_flow (output Y, input A, B);
Then use assignment statements in data flow modeling. Using
assign Y = A & B; /* the and operation, the & logical operator performs a binary
multiplication of the inputs we write*/
endmodule // to terminate the module.
• Behavioral Modelling
- The highest level of abstraction in the Verilog HDL.
- Simulates the behavior of the circuits.
- Does not have to deal with complicated circuitry or equations. Just a simple truth table would suffice.
Verilog code for AND gate using behavioral modeling
module AND_2_behavioral (output reg Y, input A, B); // identifier as AND_2_behavioral, and the port list.
/* For behavioral level, use reg data type in the output ports and reg data object holds its value over
simulation data cycles. In Verilog, begin embarks and end concludes any block which contains more than
one statement in it.*/
always @ (A or B) /*Using the always statement, a procedural statement in Verilog, we run the program
sequentially.*/
// (A, B) is known as the sensitivity list or the trigger list, controls when the statements in the always block
are to be evaluated. @ is a part of the syntax, used before the sensitivity list.
begin
if (A == 1'b1 & B == 1'b1) // if both A and B are 1, then Y has to be 1, else 0.
begin Y = 1'b1;
end
else Y = 1'b0;
end
module AND_2_behavioral (output reg Y, input A, B);
always @ (A or B) RTL schematic of the AND gate
begin
if (A == 1'b1 & B == 1'b1)
begin Y = 1'b1;
end
else Y = 1'b0;
end
endmodule
module XOR_2_gate_level(output Y, input A, B);
xor (Y, A, B); Verilog code for XOR gate using
endmodule gate-level modeling (Construction)

module XOR_2_data_flow (output Y, input A, B);

assign Y = A ^ B; Verilog code for XOR gate using
endmodule dataflow modeling (Logic Equation)

module XOR_2_behavioral (output reg Y, input A, B);

always @ (A or B)
begin if (A == 1'b0 & B == 1'b0)
Verilog code for XOR gate using
begin Y = 1'b0; behavioral modeling (Truth Table)
end if (A == 1'b1 & B == 1'b1)
begin Y = 1'b0;
end
else Y = 1'b1;
end
endmodule