39

Example 2.13

Problem: Determine the output waveform for the truth table as shown below.

A B C J
0 0 0 1
0 0 1 1
0 1 0 0
0 1 1 1
1 0 0 0
1 0 1 1
1 1 0 0
1 1 1 1

Solution: The input waveforms are not in counting order. However, they
produce input combinations that are listed in the truth table. The output
waveform is a graph of the output result when the inputs change as specified
which is shown in Figure 2.22.

Figure 2.22 Example 2.13 Waveform

 40

Chapter 3

Combinational logic circuits using TTL devices

3.1 Multiplexer and Demultiplexer

Multiplexer ( Data Selector ) Demultiplexer ( Data Distributor )

Definition: It accepts several data inputs Definition: It takes a single input data
And allows only one of them at value and routes it to one of
a time to get through to the several outputs.
output.
Diagram: Data select (determines which Diagram: Data select (determines the
data input is connected to the destination of the data input).
output).
Q0
I0 Q
Data
I1 input QN-1 Data
Output
DEMUX output
IN-1 Z
Data MUX
inputs
Select
inputs
Select
inputs

Applications: Applications:
1. Data selection 1. Data routing
2. Logic function generation
 41

3.1.1 Multiplexer
3.1.1.1 Gate Equivalent Circuit of Multiplexer

Fig 3.1.1 shows that the data select control inputs (S1,S2) are responsible to
determining which data input (D0 to D3) is selected to transmitted to the data-output
line(Y).

D
Data D
Inputs DD Data
Output

S1 S0 Data select control

input determines
which data input is
connected to the
Fig 3.1.1 Block diagram of 4:1 Multiplexer

The S1,S0 inputs will be a binary code that corresponds to the data-input line that you
want to select. If S1=0,S0=0, then D0 is selected. Fig 3.1_2 lists the codes for input data
selection.

Selec Input Output

t s Y
S1 S0
0 0 D0
0 1 D1
1 0 D2
1 1 D3

Multiplexer logic expression: Y = S .S .D + S .S D + S .S .D + S .S .D

1 0 0 1 0 1 1 0 2 1 0 3

Fig 3.1.2 4:1 Multiplexer Logic Expression and Truth Table

With reference to the logic expression shown above, the gate equivalent circuits of
multiplexer is built as shown in fig 3.1_3. In the fig 3.1_3, 1’s and 0’s were placed on the
diagram show the levels that occur when selecting input, d1. Notice that AND gate 1 will be
enabled, passing d1 to output, while all other AND gates are disabled.
 42

D0

D1

D2

D3

Fig 3.1.3 4:1 Multiplexer Built from Logic Gates

3.1.1.2 Operational Description of 74151 and 74150 IC (Multiplexer)

The operation of the multiplexer circuit is defined in the function table of the sheet
which can be found from the data sheet booklet. The 74151 consists of the following signals:

1. Data inputs, labelled D0 through D7, are used to transfer data to the output of the
multiplexer. There are 2nd data inputs, where n is the number of select inputs,
2. Multiplexed data output, an active-HIGH output, labelled Y and an active-LOW
output, labelled W.
3. Select input, three select inputs to address 23 or 8 data inputs. The addresses
range from 000 to 111. The select inputs for the 74151 are C, B and A with C the
most significant bit (MSB) and A the least significant bit (LSB) of the address.
4. Strobe input, an active-LOW input, labelled S is used to engage or disengage the
multiplexer from operation.
5. Logic symbol of 74151 is shown in the following figure.
 43

Example 3.1.1 Data Selection Application

Problem: A 4:1 data selection to transmit data from one of the four data inputs to a
single output. The input waveforms are given, and the circuit is shown in Fig
3.1-5. Determine the output waveform.

Solution: The output waveform, given in fig 3.1.4, matches the input waveform of the
selected device.

Figure 3.1.4 Data Selection Application

 44

Example 3.1.2 Cascading Multiplexer

Problem: The block diagram of 16:1 MUX is given and is shown below. By using
74151s and any other logic necessary to implement this implement this 16:1
Multiplexer.

Block diagram of 16:1 Multiplexer

Solution: The 74151 is an eight data inputs selector. In order to sixteen data inputs, two
units of 74151 are needed. The schematic diagram of 16:1 MUX us shown in
figure 3.1.5.

Figure 3.1.5 Schematic diagram of 16:1 Multiplexer

 45

Example 3.1.3 : Logic Function Generator

Problem: Implement the logic function specified in the Table 3.1-1 using the 74151 8:1
MUX. Compare this method with a discrete logic gate implementation.

Inputs Output
R S T M
0 0 0 1
0 0 1 0
0 1 0 1
0 1 1 1
1 0 0 1
1 0 1 1
1 1 0 0
1 1 1 0

Table 3.1-1

Solution: Notice from the truth table that M is a 1 for the following input variable
combinations: 000, 010, 100, 101 . For all other combinations, M is 0. For this
function to be implemented with the data selector, the data input selected by each
of the above-mentioned combinations must be connected to HIGH (Vcc) through a
pull-up resistor. All other data inputs must be connected to a LOW (ground) as
shown in figure 3.1.6.

Figure 3.1-6 74151 MUX of a Three Variable Logic Function Generator

The implementation of this function with logic gates would require five 3-input AND
gates, one 5-input OR gate, and three inverters unless the expression can be simplified.
 46

Example 3.1.4
Problem: Implement the logic function for the truth table in the Table 3.1-2 by using a
74151 8-input data selector/multiplexer.

INPUTS OUTPUT
A3 A2 A1 A0 Q
0 0 0 0 0
0 0 0 1 0
0 0 1 0 1
0 0 1 1 1
0 1 0 0 0
0 1 0 1 1
0 1 1 0 1
0 1 1 1 1
1 0 0 0 0
1 0 0 1 0
1 0 1 0 1
1 0 1 1 0
1 1 0 0 1
1 1 0 1 0
1 1 1 0 0
1 1 1 1 0

Table 3.1-2

Solution: The implementation is shown in Figure 3.1.7.

Figure 3.1-7 Data selector / Multiplexer connected as a 4–variable logic function generator
 47

3.1.2 Demultiplexer ( DMUX )

3.1.1.1 Gate Equivalent Circuit of Demultiplexer

The block diagram of the 1.4 Demultiplexer is shown in figure 3.1.8.

Figure 3.1-8 block Diagram of 1:4 Demultiplexer

The logic output equation and truth table description of the operation of
Demultiplexer (Active-HIGH output) is illustrated in Table 3.1.3. The gate
equivalent circuits of demultiplexer is built as shown in Figure 3.1.9.

Data Address Output

D S1 S0 Y0 Y1 Y2 Y3
D 0 0 D 0 0 0
D 0 1 0 D 0 0
D 1 0 0 0 D 0
D 1 1 0 0 0 D
Yo = S1 .S 0 .D........Y1 = S1 .S 0 .D.........Y2 = S1 .S 0 .D........Y3 = S1 .S 0 .D

Table 3.1.3 1:4 Demultiplexer Logic Expression and Truth Table

Figure 3.1-9 1:4 Demultiplexer Built from Logic Gates

 48

Example 3.1-5 Demultiplexer

The serial data input waveform (data input) and the data-sheet input (S1 and
S0) are shown in figure 3.1-10. Determine the data output waveforms on Y0 through
Y3 for the demultiplexer (1:4 DMUX ) shown in figure 3.1.10.

Figure 3.1-10 input and outputs waveform

3.1.2.2 Demultiplexer Integrated Circuit Specification

Table 3.1.4 lists the common TTL decoder/demultiplexer Ics. Those ICs that
contain two separate decoder/demultiplexers are listed as dual devices.

IC DECODER DMUX Output Active-

State
74138 3:8 1:8 LOW
74154 4 : 16 1 : 16 LOW
74139 Dual 2 : 4 Dual 1 : 4 LOW
74155 Dual 2 : 4 Dual 1 : 4 LOW

Table 3.1.4 TTL decoder/demultiplexer ICs

 49

Example 3.1.6 Cascading Demultiplexer

Problem: The block diagram of 1:16 DMUX is given and shown in figure 3.1-11. By
using 74138s and any other logic necessary to implement this 1:16
Demultiplexer.

Figure 3.1.11 Block diagram of 1:16 Demultiplexer

Solution: The schematic diagram of 1:16 MUX is shown in figure 3.1-12.

Selected Inputs Selected Selected

S3 S2 S1 S0 Data outputs IC
range
0 X X X D0⇒D7 U1
1 X X X D8⇒D15 U2

Figure 3.1-12 Schematic diagram of 16:1 Multiplexer

 50

3.2 Decoders

A decoder is a logic circuit that convert an N-bit binary input code into M output lines
such that each output lines will be activated for only one of the possible combinations of
input. Figure 3.2.1 shows the general decoder diagram with N inputs and M outputs.

Figure 3.2.1 General decoder diagram

Many common decoder/demultiplexers available as standard transistor- transistor logic (TTL) MSI
logic chips are listed in Tables 3.1-5.

Decoders are implemented with the same IC that functions as a demultiplexers. The
select inputs provide the address for both the demultiplexing and decoding functions. The
data input used by the demultiplexer is used as an enable input by the decoder. The major
difference is that the decoder has no data input.

3.1.2 Gate Equivalent Circuits

A decoder is identified by the number of select inputs to the decoded outputs, such as
the 2:4 decoder shown as a block diagram in Figure 3.2-2. A decoder with n select inputs
can address up to 2n outputs. The operation of the 2:4 decoder is specified in the function
tables shown in Figure 3.2.3. A logic circuit can be constructed from the equations derived
from the decoder operation specified the function tables in Figure 3.2.4.

Figure 3.2.2 2:4 Decoder or 2-Bit Decoder

 51

Select Inputs Decoded Outputs

S1 S0 Y0 Y1 Y2 Y3
0 0 0 1 1 1
0 1 1 0 1 1
1 0 1 1 0 1
1 1 1 1 1 0

Y0 = S1 .S 0 .............Y1 = S1 .S 0 .........Y2 = S1 .S 0 ...........Y3 = S1S 0

Figure 3.2-3 2:4 Active-LOW Decoder Operation

Figure 3.2.4 Active-LOW Decoder Circuits from Logic Gates

 52

3.3 Encoders
Encoder circuits perform the opposite function of decoder circuits. An encoder has
a number of input lines, only one of which is activated at a given time, and produces an N-bit
output code, depending on which input is activated. Figure 3.3-1 is the general diagram for an
encoder with M inputs and N outputs.

Figure 3.3.1 General encoder diagram

3.3.1 Gate Equivalent Circuit

Encoders have several input, but they convert only one input at a time into a
binary code. The basic 4:2 encoder block diagram in Figure 3.3-2 shows that four inputs can
be encoded with two output bits since 22 is 4. The encoding operation is shown in Figure 3.3-
3 for active-LOW input encoding. The logic functions of the encoder outputs are derived
from the truth table. Encoding circuits built from logic gates can be obtained from the logic
equations derived from the function table, as shown in Figure 3.3.4.

Figure 3.3-2 4:2 Encoder

 53

Active-LOW Inputs Outputs

I0 I1 I2 I3 B A
0 1 1 1 0 0
1 0 1 1 0 1
1 1 0 1 1 0
1 1 1 0 1 1

B = I 0 I1 I 2 I 3 + I 0 I1 I 2 I 3
A = I 0 I1 I 2 I 3 + I 0 I 1 I 2 I 3

Figure 3.3.3 Active-LOW Encoding Operation

Figure 3.3-4 Encoder Built from Logic Gates

3.3.2 Priority Encoding

Priority encoding is a technique used to ensure that when two or more inputs are
activated, the output code will correspond to the highest-numbered input.
 54

Active-LOW Encoded
Inputs Outputs
I0 I1 I2 I3 B A
0 1 1 1 0 0
x 0 1 1 0 1
x x 0 1 1 0
x x x 0 1 1

B = I 2I3 + I3
A = I1 I 2 I 3 + I 3

Figure 3.3-5 Priority Encoders

 55

PART 2

DIGITAL ELECTRONICS FOR APPLICATIONS

 55

CHAPTER 8
FLIP-FLOPS AND RELATED DEVICES

8-1 LATCHES
The latch is a type of bistable storage device that is normally placed in a category
separate from that of flip fops. Latches are basically similar to flip-flops because they are
bistable devices that can reside in either of two states by virtue of a feedback arrangement, in
which the outputs are connected back to the opposite inputs. The main difference between
latches and flip-flops is in the method used for changing their state.

The S-R Latch

A latch is a type of bistable multivibrator. An active-HIGH input S-R (SET-RESET)
latch is formed with two cross-coupled NOR gates as shown in Figure 8-1(a); an active-LOW
input S-R latch is formed with two cross-coupled NAND gates as shown in Figure 8-1(b).
Notice that the output of each gate is connected to an input of the opposite gate. This
produces the regenerative feedback that is characteristic of all multivibrators.

(a)Active HIGH input (S-R) latch (b)Active LOW input S − R latch

Figure 8-1 Two versions of SET-RESET (S-R) latches.

To understand the operation of the latch, we will use the NAND gate S − R latch in
Figure 8-1(b). This latch is redrawn in Figure 8-2 with the negative-OR equivalents used for

the NAND gates. This is done because LOWs on the S and R lines are the activating inputs.

The latch in Figure 8-2 has two inputs, S and R , and two outputs, Q and Q . Let's
start by assuming that both inputs and the Q output are HIGH. Since the Q output is

connected back to an input of gate G2, and the R input is HIGH, the output of G2 must be
LOW. This LOW output is coupled back to an input of gate G1, ensuring that its output is
HIGH.
 56

FIGURE 8-2 Negative-OR equivalent of the NAND gate S − R latch in Figure 8-1(b).

When the Q output is HIGH, the latch is in the SET state. It will remain in this state

indefinitely until a LOW is temporarily applied to the R input. With a LOW on the R input

and a HIGH on S , the output of gate G2 is forced HIGH. This HIGH on the Q output is

coupled back to an input of G1, and since the S input is HIGH, the output of G, goes LOW.

This LOW on the Q output is then coupled back to an input of G2, ensuring that the Q output

remains HIGH even when the LOW on the R input is removed. When the Q output is LOW,
the latch is in the RESET state. Now the latch remains indefinitely in the RESET state until a

LOW is applied to the S input.

The outputs of a latch are always complements of each other: When Q is HIGH, Q is

LOW, and when Q is LOW, Q is HIGH.

An invalid condition in the operation of an active-LOW input S − R latch occurs

when LOWs are applied to both S and R at the same time. As long as the LOW levels are

simultaneously held on the inputs, both the Q and Q outputs are forced HIGH, thus violating
the basic complementary operation of the outputs. Also, if the LOWs are released
simultaneously, both outputs will attempt to go LOW. Since there is always some small
difference in the propagation delay time of the gates, one of the gates will dominate in its
transition to the LOW output state. This, in turn, forces the output of the slower gate to
remain HIGH. In this situation, you cannot reliably predict the next state of the latch.

Figure 8-3 illustrates the active-LOW input S − R latch operation for each of the four
possible combinations of levels on the inputs. (The first three combinations are valid, but the
last is not.) Table 8-1 summarizes the logical operation in truth table form. Operation of the
active-HIGH input NOR gate latch in Figure 8-1(a) is similar but requires the use of opposite
logic levels.
 57

FIGURE 8-3 The three modes of basic S -R latch operation (SET, RESET, No-Change)
and the invalid condition.

TABLE 8-1 Truth table for an active-LOW input S − R latch

Input Output Comment

S R Q Q
1 1 NC NC No change. Latch remains in present state.
0 1 1 0 Latch SET.
1 0 0 1 Latch RESET
0 0 1 1 Invalid condition
 58

FIGURE 8-4 Logic symbols for the S-R latch.

EXAMPLE 8-1

If the S and R waveforms in Figure 8-5(a) are applied to the inputs of the latch in
Figure 8-4(b), determine the waveform that will be observed on the Q output. Assume that Q
is initially LOW.

FIGURE 8-5

Solution See Figure 8-5(b).

Related Exercise Determine the Q output of an active-HIGH' input S-R latch if the
waveforms in Figure 8-5(a) are inverted and applied to the inputs.

The Latch as a Contact-Bounce Eliminator

A good wxample of an application of an S-R Latch is in the elimination of mechanical

switch contact "bounce". When the pole of a switch strikes the contact upon switch closure it
physically vibrates or bounces several time before finally making a solid contact. Although
these bounces are minute, they produce voltage solid that are often not acceptable in a digital
system. This situation is illustrated in Figure 8-6 (a).

FIGURE 8-6 The S − R latch used to eliminate switch contact bounce.

 59

An S − R latch can be used to-eliminate the effects of switch bounce as shown in

Figure 8-6(b). The switch is normally in position 1, keeping the R input LOW and the latch

RESET. When the switch is thrown to position 2, R goes HIGH because of the pull-up

resistor to Vcc, and S goes LOW on the first contact. Although S remains LOW for only a
very short time before the switch bounces, this is sufficient to SET the latch. Any further

voltage spikes on the S input due to switch bounce do not affect the latch, and it remains
SET. Notice that the Q output of the latch provides a clean transition from LOW to HIGH,
thus eliminating the voltage spikes caused by contact bounce. Similarly, a clean transition
from HIGH to LOW is made when the switch is thrown back to position 1.

The 74LS279 Quad S − R Latch

The 74LS279 is an example of a quad S − R latch represented by the diagram of

Figure 8-7. Notice that two of the latches each have two S inputs.

FIGURE 8-7
The Gated S-R Latch
A gated latch requires an enable input, EN. The logic diagram and logic symbol for a
gated S-R latch are shown in Figure 8-8. The S and R inputs control the state to which the
latch will go when a HIGH level is applied to the EN input. The latch will not change until
EN is HIGH, but as long as it remains HIGH, the output is controlled by the state of the S and
R inputs. In this circuit the invalid state occurs when both S and R are simultaneously HIGH.

FIGURE 8-8 A gated S-R Latch

EXAMPLE 8-2
Determine the Q output waveform if the inputs shown in Figure 8-9(a) are applied to a gated
S-R latch that is initially RESET.
 60

FIGURE 8-9

Solution
The Q waveform is shown in Figure 8-9(b). Anytime S is HIGH and R is LOW, a HIGH on
the EN input SETS the latch. Anytime S is LOW and R is HIGH, a HIGH on the EN input
RESETS the latch.
Related Exercise
Determine the Q output of a gated S-R latch if the S and R inputs in Figure 8-9(a) are
inverted.

The Gated D Latch

FIGURE 8-10 A gated D latch.

It differs from the S-R latch because it has only one input in addition to EN. This
input is called the D (data) input. Figure 8-10 contains a logic diagram and logic symbol of a
D latch. When the D input is HIGH and the EN input is HIGH; the latch will SET. When the
D input is LOW, and EN is HIGH, the latch will RESET. Stated another way, the output Q
follows the input D when EN is HIGH.

EXAMPLE 8-3
Determine the Q output waveform if the inputs shown in Figure 8-11(a) are applied to
a gated D latch, which is initially RESET.

FIGURE 8-11
 61

Solution
The Q waveform is shown in Figure 8-11(b). Whenever D is HIGH and EN is HIGH,
Q goes HIGH. Whenever D is LOW and EN is HIGH, Q goes LOW. When EN is LOW, the
state of the latch is not affected by the D input.

Related Exercise
Determine the Q output of the gated D latch if the D input in Figure 8-11(a) is inverted.

The 74LS75 Quad Latches

An example of an IC gated D latch is the 74LS75 represented by the logic symbol in
Figure 8-12(a). This device has four latches. Notice that each active-HIGH EN input is
shared by two latches and is designated as a control input (C). The truth table for each latch is
shown in Figure 8-12(b). The X in the truth table represents a "don't care" condition. In this
case, when the EN input is LOW, it does not matter what the D input is because the outputs
are unaffected and remain in their prior states.

FIGURE 8-12 The 74LS75 quad gated D latches.

8-2 EDGE-TRIGGERED FLIP-FLOPS

Flip-flops are synchronous bistable devices. In this case the term synchronous means
that the output changes state only at a specified point on a triggering input called the clock
(CLK) which is designated as a control input, C; that is, changes in the output occur in
synchronization with the clock.
 62

Three types of edgetriggered flip-flops are covered in this section: S-R, D, and J-K.

FIGURE 8-13 Edge triggered flip-flop logic symbols (top-positive edge-triggered,

bottom-negative edge-triggered).

The Edge Triggered S-R Flip-Flop

The S and R inputs of the S-R flip-flop are called synchronous inputs because data on
these inputs are transferred to the flip-flop's output only on the triggering edge of the clock
pulse. When S is HIGH and R is LOW, the Q output goes HIGH on the triggering edge of the
clock pulse, and the flip-flop is SET. When S is LOW and R is HIGH, the Q output goes
LOW on the triggering edge of the clock pulse, and the flip-flop is RESET. When both S and
R are LOW, the output does not change from its prior state. An invalid condition exists when
both S and R are HIGH.

The basic operation of a positive edge-triggered flip flop is illustrated in Figure 8-14,
and Table 8-3 is the truth table for this type of flip flop. Remember, the flip flop cannot
change state except on the triggering edge of a clock pulse. The S and R inputs can be
changed at any time when the clock input is low or high (except for a very short interval
around the btriggering transition of the clock ) without affecting the output.
 63

The operation and truth table for a negative edge-triggered S-R flip flop are the same
as those for a positive edge triggered device except that the falling edge of the clock pulse is
the triggering edge.

FIGURE 8-14 Operation of a positive edge-triggered S-R flip-flop.

EXAMPLE 8-4
Determine the Q and Q output waveforms of the flip-flop in Figure 8-15 for the S, R,
and CLK inputs in Figure 8-16(a). Assume that the positive edge-triggered flip-flop is
initially RESET.

FIGURE 8-15

Figure 8-16
 64

Solution
1. At clock pulse 1, S is LOW and R is LOW, so Q does not change.
2. At clock pulse 2, S is LOW and R is HIGH, so Q remains LOW (RESET).
3. At clock pulse 3, S is HIGH and R is LOW, so Q goes HIGH (SET).
4. At clock pulse 4, S is LOW and R is HIGH, so Q goes LOW (RESET).
5. At clock pulse 5, S is HIGH and R is LOW, so Q goes HIGH (SET).
6. At clock pulse 6, S is HIGH and R is LOW, so Q stays HIGH.
Once Q is determined, Q is easily found since it is simply the complement of Q. The
resulting waveforms for Q and Q are shown in Figure 8-16(b) for the input waveforms in part
(a).

Related Exercise
Determine Q and Q for the S and R inputs in Figure 8-16(a) if the flip-flop is a
negative edge-triggered device.

A Method of Edge Triggering

A simplified implementation of an edge triggered S-R flip flop is illustrated in Figure
8-17 (a) and is used to demonstrate the concept of edge-triggering. This converge of the S-R
flip flop does not imply that it is the most important type. Actually the D flip flop and the
J-K flip flop are more widely used and more available in IC form than is the S-R type.
However, understanding the S-R is important because both the D and J-K flip flop
are derived from the S-R flip flop. Noticed that the S-R flip flop differs from the gated S-R

latch only in that it has a pulse transition detector. This circuit produces a very short
duration spike on the positive-going transition of the clock pulse.
One basic type of pulse transition detector is shown in Figure 8-17(b). As you
can see ,there is a small delay on one input to the NAND gate so that the inverted clock pulse
arrives at the gate input a few nanoseconds after the true clock pulse. This produce an output
spike with a duration of only a few nanoseconds. In a negative edge-triggered flip flop the
clock pulse is inverted first, thus producing a narrow spike on the negative -going edge.
Notice that the circuit in Figure 8-17 is partitioned into two sections, one labeled
Steering gates, and the other Latch. The steering gates direct, or steer, the clock spike either
 65

to the input to gate G3 or to the input to gate G4, depending on the state of the S and R inputs.
To understand the operation of this flip-flop, begin with the assumptions that it is in the
RESET state (Q = 0) and that the S, R, and CLK inputs are all LOW. For this condition, the
outputs of gate G, and gate G2 are both HIGH. The LOW on the Q output is coupled back

into one input of gate G4, making the Q output HIGH. Because Q is HIGH, both inputs to
gate G3 are HIGH (remember, the output of gate G1 is HIGH), holding the Q output LOW. If
a pulse is applied to the CLK input, the outputs of gates G, and G2 remain HIGH because
they are disabled by the LOWs on the S input and the R input; therefore, there is no change in
the state of the flip-flop-it remains RESET.

FIGURE 8-17 Edge triggering.

Let's now make S HIGH, leave R LOW and apply a clock pulse. Because the S input
to gate G1 is now HIGH, the output of gate G1 goes LOW for a very short time (spike) when
CLK goes HIGH, causing the Q output to go HIGH. Both inputs to gate G4 are now HIGH

(remember, gate G2 output is HIGH because R is LOW), forcing the Q output LOW. This

LOW on Q is coupled back into one input of gate G3, ensuring that the Q output will remain
HIGH. The flip-flop is now in the SET state. Figure 8-18 illustrates the logic level transitions
that take place within the flip-flop for this condition.
 66

FIGURE 8-18 Flip-flop making a transition from the RESET state to the SET state on the
pasitive-going edge of the clock pulse.

Next, let's make S LOW and R HIGH and apply a clock pulse. Because the R input is
now HIGH, the positive-going edge of the clock produces a negative-going spike on the

output of gate G2 causing the Q output to go HIGH. Because of this HIGH on Q , both inputs
to gate G3 are now HIGH (remember, the output of gate G1 is HIGH because of the LOW on
S), forcing the Q output to go LOW. This LOW on Q is coupled back into one input of gate
G4, ensuring that Q will remain HIGH. The flip-flop is now in the RESET state. Figure 8-19
illustrates the logic level transitions that occur within the flip-flop for this condition. As with
the gated latch, an invalid condition exists when both S and R are HIGH at the same time.
This is the major drawback of the S-R flip-flop.

FIGURE 8-19 Flip-flop making a transition from the SET state to the RESET state on the
positive-going edge of the clock pulse.

The Edge Triggered D Flip-Flop

The D flip-flop is useful when a single data hit (1 or 0) is to be stored. The addition of
an inverter to an S-R flip-flop creates a basic D flip-flop, as in Figure 8-20, where a positive
edge-triggered type is shown.
Notice that the flip-flop in Figure 8-20 has only one input, the D input, in addition to
the clock. If there is a HIGH on the D input when a clock pulse is applied, the flip-flop will
SET, and the HIGH on the D input is stored by the flip-flop on the positive-going edge of the
clock pulse. If there is a LOW on the D input when the clock pulse is applied, the flip-flop
will RESET, and the LOW on the D input is stored by the flip-flop on the leading edge of the
 67

clock pulse. In the SET state the flip-flop is storing a 1, and in the RESET state it is storing a
0.
The operation of the positive edge-triggered D flip-flop is summarized in Table 8-3.
The operation of a negative edge-triggered device is, of course, the same, except that
triggering occurs on the falling edge of the clock pulse. Remember, Q follows D at the clock
edge.

FIGURE 8-20 A positive edge-triggered D flip-flop formed with an S-R flip-flop and an
inverter.

TABLE 8-3
Truth table for a positive edge-triggered D flip-flop
Inputs Outputs
D CLK Q Q Comments

1 ↑ 1 0 SET (stores a 1)
0 ↑ 0 1 RESET (stores a 0)

↑ - clock transition LOW to HIGH

EXAMPLE 8-5
Given the waveforms in Figure 8-21(a) for the D input and the clock, determine the Q
output waveform if the flip-flop starts out RESET.

FIGURE 8-21

Solution
The Q output goes to the state of the D input at the time of the positivegoing clock
edge. The resultant output is shown in Figure 8-21(b).
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Related Exercise
Determine the Q output for the D flip-flop if the D input in Figure 8-21(a) is inverted.

The Edge-Triggered )-K Flip-Flop

The J-K flip-flop is versatile and is perhaps the most widely used type of flip-flop.
The J and K designations for the inputs have no known significance except that they are
adjacent letters in the alphabet.
The functioning of the J-K flip-flop is identical to that of the S-R flip-flop in the SET,
RESET, and no-change conditions of operation. The difference is that the J-K flip-flop has no
invalid state as does the S-R flip-flop.

Figure 8-22 shows the basic internal logic for a positive edge-triggered J-K flip-flop.
Notice that it differs from the S-R edge-triggered flip-flop in that the Q output is connected

back to the input of gate G2, and the Q output is connected back to the input of gate G1. The
two inputs are labeled J and K. A J-K flip-flop can also be of the negative edge-triggered
type, in which case the clock input is inverted.

FIGURE 8-22 A simplified logic diagram for a positive edge-triggered J-K Flip-flop.

Let's assume that the flip-flop in Figure 8-23 is RESET and that the J input is HIGH
and the K input is LOW rather than as shown. When a clock pulse occurs, a leading-edge

spike indicated by (1) is passed through gate G1 because Q is HIGH and J is HIGH. This will
cause the latch portion of the flip-flop to change to the SET state.
The flip-flop is now SET. If we now make J LOW and K HIGH, the next clock spike
indicated by (2) will pass through gate G2 because Q is HIGH and K is HIGH. This will
cause the latch portion of the flip-flop to change to the RESET state.
Now if a LAW is applied to both the J and K inputs, the flip-flop will stay in its
present state when a clock pulse occurs. So, a LOW on both J and K results in a no-change
condition.
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FIGURE 6-23 Transitions illustrating the toggle operation when j = 1 and K = 1.

So far, the logical operation of the J-K flip-flop is the same as that of the S-R type in
the SET, RESET, and no-change modes. The difference in operation occurs when both the J

and K inputs are HIGH. To see this, assume that the flip-flop is RESET The HIGH on the Q
enables gate G1 so the clock spike indicated by (3) passes through to SET the flip-flop. Now,

there is a HIGH on Q, which allows the next clock spike to pass through gate G2 and
RESET the flip-flop.

TABLE8-4
Truth table for a positive edge-
triggered J-K flip-flop

EXAMPLE8-6

The waveforms in Figure 8-24(a) are applied to the J, K, and clock inputs as
indicated. Determine the Q output, assuming that the flip-flop is initially RESET.

FIGURE 8-24
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Solution

1. First, since this is a negative edge-triggered flip-flop, as indicated by the

"bubble" at the clock input, the Q output will change only on the negative-going
edge of the clock pulse.

2. At the first clock pulse, both J and K are HIGH: and because this is a toggle
condition, Q goes HIGH.
3. At clock pulse 2, a no-change condition exists on the inputs, keeping Q at a
HIGH level.
4. When clock pulse 3 occurs, J is LOW and K is HIGH, resulting in a RESET
condition; Q goes LOW.
5. At clock pulse 4, J is HIGH and K is LOW, resulting in a SET condition; Q
goes HIGH.
6. A SET condition still exists on J and K when clock pulse 5 occurs, so Q will
remain HIGH.

The resulting Q waveform is indicated in Figure 8-24(b).

Related Exercise
Determine the Q output of the J-K flip-flop if the J and K inputs in Figure 8-24(a) are
inverted.

Asynchronous Inputs
For the flip-flops just discussed, the S-R, D, and J -K inputs are called synchronous
inputs because data on these inputs are transferred to the flip-flop's output only on the
triggering edge of the clock pulse; that is, the data are transferred synchronously with the
clock.
Most integrated circuit flip-flops also have asynchronous inputs. These are inputs that
affect the state of the flip-flop independent of the clock. They are normally labeled preset
(PRE) and clear (CLR), or direct set (SD) and direct reset (RD) by some manufacturers. An
active level on the preset input will SET the flip-flop, and an active level on the clear input
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will RESET it. A logic symbol for a J-K flip-flop with preset and clear inputs is shown in
Figure 8-25. These inputs are active-LOW, as indicated by the bubbles. These preset and
clear inputs must both be kept HIGH for synchronous operation.
Figure 8-26 shows the logic diagram for an edge-triggered J-K flip-flop with active
LOW preset (PRE) and clear (CLR) inputs. This figure illustrates basically how these inputs
work. As you can see, they are connected so that they override the effect of the synchronous
inputs, J, K and the clock.

FIGURE 8-25
Logic symbol for a J-K flip-flop with
active-LOW preset and clear inputs.

FIGURE 8-26
Logic diagram for a basic) J-K Flip-flop
with active-LOW preset and clear.

EXAMPLE 8-7
For the positive edge-triggered J-K flip-flop with preset and clear inputs in Figure 8-
27(a), determine the Q output for the inputs shown in the timing diagram if Q is initially
LOW.

FIGURE 8-.27
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Solution

1. During clock pulses 1, 2, and 3, the preset ( PRE ) is LOW, keeping the Sip-flop SET
regardless of the synchronous J and K inputs.
2. For clock pulses 4, 5, 6, and 7, toggle operation occurs because J is HIGH, K is

HIGH, and both PRE and CLR are HIGH.

3. For clock pulses 8 and 9, the clear ( CLR ) input is LOW, keeping the flip-flop RESET
regardless of the synchronous inputs. The resulting Q output is shown in Figure 8-27(b).

Related Exercise If you interchange the PRE and CLR waveforms in Figure 8-27(a), what
will the Q output look like?

8-3 MASTER-SLAVE FLIP-FLOPS

Another class of f lip flop is the master-slave. Although this type of flip-flop has
largely been replaced. by the edge-triggered devices, a limited selection is still available from
IC manufacturers and you may encounter this type of flip-flop in some existing equipment.
Two basic types of master-slave flip-flops are the pulse-triggered and the data lock-out
versions. In both types, data are entered_ into the flip-fop on the leading edge of the clock
pulse, but the output does not reflect the input state until the trailing edge. The pulse-tiggered
version does not allow data to change while the clock pulse is active, whereas the data lock-
out version does not have this restriction.

The Pulse-Triggered Master-Slave J-K Flip-Flop

This type of flip-flop is composed of two sections, the master section and the slave
section. The master section is basically a gated latch, and the slave section is the same except
that it is clocked on the inverted clock pulse and is controlled by the outputs of the master
section rather than by the external J-K inputs.

FIGURE 8-31 Logic diagram for a master-slave J-K Flip-flop.

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The master section will assume the state determined by the J and K inputs at the
leading (positive-going) edge of the clock pulse. The state of the master section is then
transferred to the slave section on the trailing (negative-going) edge of the clock pulse,
because the outputs of the master are applied to the inputs of the slave and the clock pulse to

the slave is inverted. The state of the slave then immediately appears on the Q and Q outputs.

The Q output is connected back to an input of gate G2 and the Q output is connected back to
an input of gate G, to produce the characteristic toggle operation when J = I and K = 1. The
logical operation is summarized in Table 8-5.
TABLE 8-5 Truth table for tits master-slave J-K flip-flop

FIGURE 8-32 Pulse-triggered (master-slave) J-K flip-flop logic symbols .

EXAMPLE 8-9 Determine the Q output of the master-slave J-K flip-flop for the input
waveforms shown in Figure 8-33(a). The flip-flop starts out RESET.