BASIC ELECTRONICS NOTES

B.Tech, SEMESTER-I, August 2020

Definition: A p-n junction is an interface or a boundary between two semiconductor material

types, namely the p-type and the n-type, inside a semiconductor.

The p-side or the positive side of the semiconductor has an excess of holes and the n-side or
the negative side has an excess of electrons. In a semiconductor, the p-n junction is created by
the method of doping. The process of doping is explained in further detail in the next section.

Formation of P-N Junction

As we know if we use different semiconductor materials to make a p-n junction, there will be
a grain boundary that would inhibit the movement of electrons from one side to the other by
scattering the electrons and holes and thus we use the process of doping. We will understand
the process of doping with the help of this example. Let us consider a thin p-type silicon
semiconductor sheet. If we add a small amount of pentavalent impurity to this, a part of the p-
type Si will get converted to n-type silicon. This sheet will now contain both p-type region and
n-type region and a junction between these two regions. The processes that follow after the
formation of a p-n junction are of two types – diffusion and drift. As we know, there is a
difference in the concentration of holes and electrons at the two sides of a junction, the holes
from the p-side diffuse to the n-side and the electrons from the n-side diffuse to the p-side.
These give rise to a diffusion current across the junction.

Figure 1 Unbiased pn junction diode

Also, when an electron diffuses from the n-side to the p-side, an ionized donor is left behind
on the n-side, which is immobile. As the process goes on, a layer of positive charge is developed
on the n-side of the junction. Similarly, when a hole goes from the p-side to the n-side, and
ionized acceptor is left behind in the p-side, resulting in the formation of a layer of negative
charges in the p-side of the junction. This region of positive charge and negative charge on
either side of the junction is termed as the depletion region. Due to this positive space charge
region on either side of the junction, an electric field direction from a positive charge towards
the negative charge is developed. Due to this electric field, an electron on the p-side of the
junction moves to the n-side of the junction. This motion is termed as the drift. Here, we see
that the direction of drift current is
opposite to that of the diffusion current.

Biasing conditions for the p-n Junction Diode

There are two operating regions in the p-n junction diode:

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• P-type
• N-type

There are three biasing conditions for p-n junction diode and this is based on the voltage
applied:

• Zero bias: There is no external voltage applied to the p-n junction diode.
• Forward bias: The positive terminal of the voltage potential is connected to the p-type
while the negative terminal is connected to the n-type.
• Reverse bias: The negative terminal of the voltage potential is connected to the p-type
and the positive is connected to the n-type.

Forward Bias

When the p-type is connected to the positive terminal of the battery and the n-type to the
negative terminal then the p-n junction is said to be forward-biased. When the p-n junction is
forward biased, the built-in electric field at the p-n junction and the applied electric field are in
opposite directions. When both the electric fields add up the resultant electric field has a
magnitude lesser than the built-in electric field. This results in a less resistive and thinner
depletion region. The depletion region’s resistance becomes negligible when the applied
voltage is large. In silicon, at the voltage of 0.6 V, the resistance of the depletion region
becomes completely negligible and the current flows across it unimpeded.

Reverse Bias

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When the p-type is connected to the negative terminal of the battery and the n-type is connected
to the positive side then the p-n junction is said to be reverse biased. In this case, the built-in
electric field and the applied electric field are in the same direction. When the two fields are
added, the resultant electric field is in the same direction as the built-in electric field creating a
more resistive, thicker depletion region. The depletion region becomes more resistive and
thicker if the applied voltage becomes larger.
The formula used in the p-n junction depends upon the built-in potential difference created by
the electric field is given as:

Where,
E0 is the zero bias junction voltage
VT is the thermal voltage of 26mV at room temperature
ND and NA are the impurity concentrations
ni is the intrinsic concentration.
The flow of electrons from the n-side towards the p-side of the junction takes place when there
is an increase in the voltage. Similarly, the flow of holes from the p-side towards the n-side of
the junction takes place along with the increase in the voltage. This results in the concentration
gradient between both sides of the terminals. Because of the formation of the concentration
gradient, there will be a flow of charge carriers from higher concentration regions to lower
concentration regions. The movement of charge carriers inside the pn junction is the reason
behind the current flow in the circuit.

V-I Characteristics of PN Junction Diode

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VI characteristics of PN junction diode is a curve between the voltage and current through the
circuit. Voltage is taken along the x-axis while the current is taken along the y-axis. The above
graph is the VI characteristics curve of the PN junction diode. With the help of the curve we
can understand that there are three regions in which the diode works, and they are:

• Zero bias
• Forward bias
• Reverse bias

When the PN junction diode is under zero bias condition, there is no external voltage applied
and this means that the potential barrier at the junction does not allow the flow of current.

When the PN junction diode is under forward bias condition, the p-type is connected to the
positive terminal while the n-type is connected to the negative terminal of the external voltage.
When the diode is arranged in this manner, there is a reduction in the potential barrier. For
silicone diodes, when the voltage is 0.7 V and for germanium diodes, when the voltage is 0.3
V, the potential barriers decreases and there is a flow of current.

When the diode is in forward bias, the current increases slowly and the curve obtained is non-
linear as the voltage applied to the diode is overcoming the potential barrier. Once the potential
barrier is overcome by the diode, the diode behaves normal and the curve rises sharply as the
external voltage increases and the curve so obtained is linear.

When the PN junction diode is under negative bias condition, the p-type is connected to the
negative terminal while the n-type is connected to the positive terminal of the external voltage.
This results in an increase in the potential barrier. Reverse saturation current flows in the
beginning as minority carriers are present in the junction.

When the applied voltage is increased, the minority charges will have increased kinetic energy
which affects the majority charges. This is the stage when the diode breaks down. This may
also destroy the diode.

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Applications of PN Junction Diode

• p-n junction diode can be used as a photodiode as the diode is sensitive to the light
when the configuration of the diode is reverse-biased.
• It can be used as a solar cell.
• When the diode is forward-biased, it can be used in LED lighting applications.
• It is used as rectifiers in many electric circuits and as a voltage-controlled oscillator in
varactors.

DIODE EQUIVALENT CIRCUITS

An equivalent circuit is a combination of elements properly chosen to best

represent the actual terminal characteristics of a device, system, or such in a
particular operating region.

Ideal Diode Model

Figure indicates that the voltage drop across the diode is zero for any value of diode current.
The ideal diode does not allow any current to flow in reverse biased condition. The current
flowing through the diode is zero for any value of reverse biased voltage. Taking this into
consideration, the ideal diode can be modeled as open or closed switch depending on the bias
voltage.1.Ideal diode allows the flow of forward current for any value of forward bias voltage.
Hence, Ideal diode can be modeled as closed switch under forward bias condition. This is
shown in the figure.2. Ideal diode allows zero current to flow under reverse biased condition.
Hence it can be modeled as open switch. This is indicated in the figure.

Simplified Model

The equivalent model in this case consists of a battery and an ideal diode. Consider the
horizontal line from (0 to 0.7 V) in the curve. The horizontal line indicates that the current
flowing through diode is zero for voltages between 0 and 0.7 V. To model this behaviour, we
put a battery of 0.7 V in the equivalent diode model. This does not mean that diodes are a
source of voltage. When you measure the voltage across an isolated diode, the instrument will
show zero value. The battery simply indicates that it opposes the flow of current in forward

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direction until 0.7 V. As the voltage becomes larger than 0.7 V, the current starts flowing in
forward direction.

Piece-Wise Linear Model

The piece-wise linear model, as the name suggests, is a model in which the characteristics of
diode is approximated by “piece-wise linear” line segments. Now consider the straight line in
the piece-wise linear characteristics. This straight line indicates constant slope. Slope in the V-
I graph indicates resistance. So we add a resistor in the diode model. The value of resistance
can be found from thegraph. We can see from the graph that the diode current changes from 0
to 15 mA for a voltage change from 0.7 to 0.8 V. Thus the average value of resistance is (0.8
V-0.7 V)/(15 mA-0 mA) = 6.67 Ω. Thus the value of resistance in the equivalent model is
approximately 6.67Ω. The figure given below shows piece-wise linear characteristics of diode
along with the its model.

In the graph shown on left, the actual characteristics of diode is superimposed by piece-wise
linear characteristics. It is clear that the piece-wise linear characteristics do not exactly
represent the characteristics of diode, especially near the knee of the curve. However it provides
a good first approximation to the actual characteristics of the diode. Piece-wise linear
characteristics can be obtained by replacing the diode in the circuit with a resistor, a battery
and an ideal diode. This is shown in the right side of the above figure.

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Zener Diodes

A diode is a fundamental electronic component that allows the flow of electricity in one
direction only. There are many types of diodes and Zener diode is one of the commonly used
diodes. Zener diodes not only allow current to flow from anode to cathode but also, in the
reverse direction on reaching the Zener voltage. Due to this functionality, Zener diodes are the
most commonly used semiconductor diodes.

Zener diodes, also known as breakdown diodes are heavily doped semiconductor devices that
are designed to operate in the reverse direction. When the voltage across its terminals is
reversed and the potential reaches the Zener Voltage (knee voltage), the junction will break
down and the current flows in the reverse direction. This effect is known as the Zener Effect.
Zener diodes are manufactured with a great variety of Zener voltages (Vz) and some are even
made variable.

Zener Diode Circuit Symbol

Zener Diode Specifications

Some commonly used specifications for Zener diodes are as follows:

• Zener/Breakdown Voltage – The Zener or the reverse breakdown voltage ranges from
2.4 V to 200 V, sometimes it can go up to 1 kV while the maximum for the surface-
mounted device is 47 V.
• Current Iz (max) – It is the maximum current at the rated Zener Voltage (Vz – 200μA
to 200 A)
• Current Iz (min) – It is the minimum value of current required for the diode to
breakdown.
• Power Rating – It denotes the maximum power the Zener diode can dissipate. It is given
by the product of voltage of the diode and the current flowing through it.
• Temperature Stability – Diodes around 5 V have the best stability
• Voltage Tolerance – It is typically ±5%
• Zener Resistance (Rz) – It is the resistance the Zener diode exhibits.

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Working of Zener Diode

The Zener diode operates just like a normal diode when it is forward-biased. However, when
connected in reverse biased mode, a small leakage current flows through the diode. As the
reverse voltage increases to the predetermined breakdown voltage (Vz), a current start flowing
through the diode. The current increases to a maximum, which is determined by the series
resistor, after which it stabilizes and remains constant over a wide range of applied voltage.

For a Zener diode there are two types of breakdown:

• Zener breakdown
• Avalanche breakdown

A conventional reverse-biased diode, when subjected to its breakdown voltage allows a

significant amount of current. But when this reverse breakdown voltage is exceeded, the diode
experiences an avalanche breakdown. An Avalanche breakdown is a form of electric current
conduction that allows a very large current to pass through good insulators. This may
permanently damage a conventional diode. A Zener diode exhibits the same properties except
it is designed to have a reduced breakdown voltage. In contrast to the conventional diode, it
exhibits a controlled breakdown. When we increase the voltage through Zener diode in reverse
bias mode, first current increases uniformly with it but after it reaches the breakdown state, the
current increases massively for a very small or negligible change in voltage. The change is
sharper in the Zener diode than the normal diode.

Zener Breakdown vs Avalanche Breakdown

• The Zener effect is dominant in voltages up to 5.6 volts and the avalanche effect takes
over above that.
• They are both similar effects, the difference being that the Zener effect is a quantum
phenomenon and the avalanche effect is the movement of electrons in the valence
band like in any electric current.
• Avalanche effect also allows a larger current through the diode than the Zener effect

Zener Breakdown Avalanche Breakdown

The process in which the electrons move The process of applying high voltage and
across the barrier from the valence band of p- increasing the free electrons or electric
type material to the conduction band of n- current in semiconductors and insulating
type material is known as Zener breakdown. materials is called an avalanche breakdown.
This is observed in Zener diodes having a This is observed in Zener diode having a
Zener breakdown voltage Zener breakdown voltage Vz greater than 8
Vz of 5 to 8 volts. volts.
The valence electrons are pushed to
The valence electrons are pulled into conduction due to the energy imparted by
conduction due to the high electric field in accelerated electrons, which gain their
the narrow depletion region. velocity due to their collision with other
atoms.

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The increase in temperature decreases the The increase in temperature increases the
breakdown voltage. breakdown voltage.
The VI characteristic curve of the avalanche
The VI characteristics of a Zener breakdown
breakdown is not as sharp as the Zener
has a sharp curve.
breakdown.
It occurs in diodes that are highly doped. It occurs in diodes that are lightly doped.

V-I Characteristics of Zener Diode

The diagram given below shows the V-I characteristics of the Zener diode.

The V-I characteristics of a Zener diode can be divided into two parts as follows:
(i) Forward Characteristics
(ii) Reverse Characteristics

Forward Characteristics

The first quadrant in the graph represents the forward characteristics of a Zener diode. From
the graph we understand that it is almost identical to the forward characteristics of any other P-
N junction diode.

Reverse Characteristics

When a reverse voltage is applied to a Zener voltage, initially a small reverse saturation current
Io flows across the diode. This current is due to thermally generated minority carriers. As the
reverse voltage is increased, at a certain value of reverse voltage, the reverse current increases
drastically and sharply. This is an indication that the breakdown has occurred. We call this
voltage breakdown voltage or Zener voltage and it is denoted by Vz.

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Application of Zener Diode

Zener diode as a voltage regulator:

Zener diode is used as a Shunt voltage regulator for regulating voltage across small loads. The
breakdown voltage of Zener diodes will be constant for a wide range of current. Zener diode is
connected parallel to the load to make it reverse bias and once the Zener diode exceeds knee
voltage, the voltage across the load will become constant.

Zener diode in over-voltage protection:

When the input voltage is higher than the Zener breakage voltage, the voltage across the resistor
drops resulting in a short circuit. This can be avoided by using the Zener diode.

Zener diode in clipping circuits:

Zener diode is used for modifying AC waveform clipping circuits by limiting the parts of either
one or both the half cycles of an AC waveform.

Zener diode as a voltage regulator

Zener diode is a silicon semiconductor with a p-n junction that is specifically designed to work
in the reverse biased condition. When forward biased, it behaves like a normal signal diode,
but when the reverse voltage is applied to it, the voltage remains constant for a wide range of
currents. Due to this feature, it is used as a voltage regulator in d.c. circuit. The primary
objective of the Zener diode as a voltage regulator is to maintain a constant voltage. Let us say
if Zener voltage of 5 V is used then, the voltage becomes constant at 5 V, and it does not
change.

A voltage regulator is a device that regulates the voltage level. It essentially steps down the
input voltage to the desired level and keeps it in that same level during the supply. This ensures
that even when a load is applied the voltage doesn’t drop. The voltage regulator is used for two
main reasons and they are:

• To vary or regulate the output voltage

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• To keep the output voltage constant at the desired value in spite of variations in the
supply voltage.

Voltage regulators are used in computers, power generators, alternators to control the output
of the plant.

Zener Diode as a Voltage Regulator

There is a series resistor connected to the circuit in order to limit the current into the diode. It
is connected to the positive terminal of the d.c. It works in such a way the reverse-biased can
also work in breakdown condition. We do not use ordinary junction diode because the low
power rating diode can get damaged when we apply reverse bias above its breakdown voltage.
When the minimum input voltage and the maximum load current is applied, the Zener diode
current should always be minimum.

Since the input voltage and the required output voltage is known, it is easier to choose a Zener
diode with a voltage approximately equal to the load voltage, i.e. VZ = VL.

The value of the series resistor is written as RS = (VL − VZ)IL

Current through the diode increases when the voltage across the diode tends to increase which
results in the voltage drop across the resistor. Similarly, the current through the diode decreases
when the voltage across the diode tends to decrease. Here, the voltage drop across the resistor
is very less, and the output voltage results normally.

Rectification
The main application of p-n junction diode is in rectification circuits. These circuits are used
to describe the conversion of a.c signals to d.c in power supplies. Diode rectifier gives an
alternating voltage which pulsates in accordance with time. The filter smoothes the pulsation
in the voltage and to produce d.c voltage, a regulator is used which removes the ripples.

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There are two primary methods of diode rectification:

• Half Wave Rectifier

• Full Wave Rectifier

Half Wave Rectifier

In a half-wave rectifier, one half of each a.c input cycle is rectified. When the p-n junction
diode is forward biased, it gives little resistance and when it is reversing biased it provides high
resistance. During one-half cycles, the diode is forward biased when the input voltage is applied
and in the opposite half cycle, it is reverse biased. During alternate half cycles, the optimum
result can be obtained.

Working

The half wave rectifier has both positive and negative cycles. During the positive
half of the input, the current will flow from positive to negative which will
generate only positive half cycle of the a.c supply. When a.c supply is applied to
the transformer, the voltage will be decreasing at the secondary winding of the
diode. All the variations in the a.c supply will reduce and we will get the pulsating
d.c voltage to the load resistor.

In the second half cycle, current will flow from negative to positive and the diode
will be reverse biased. Thus, at the output side, there will be no current generated
and we cannot get power at the load resistance. A small amount of reverse current
will flow during reverse bias due to minority carriers.

Full Wave Rectifier

In a Full Wave Rectifier circuit two diodes are now used, one for each half of the
cycle. A multiple winding transformer is used whose secondary winding is split
equally into two halves with a common centre tapped connection, (C). This
configuration results in each diode conducting in turn when its anode terminal is
positive with respect to the transformer centre point C producing an output during
both half-cycles, twice that for the half wave rectifier so it is 100% efficient as
shown below.

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Working

The full wave rectifier circuit consists of two diodes connected to a single load
resistance (RL) with each diode taking it in turn to supply current to the load.
When point A of the transformer is positive with respect to point C, diode D1
conducts in the forward direction as indicated by the arrows.

When point B is positive (in the negative half of the cycle) with respect to point
C, diode D2 conducts in the forward direction and the current flowing through
resistor R is in the same direction for both half-cycles. As the output voltage
across the resistor R is the phasor sum of the two waveforms combined, this type
of full wave rectifier circuit is also known as a “bi-phase” circuit.

The main disadvantage of this type of full wave rectifier circuit is that a larger
transformer for a given power output is required with two separate but identical
secondary windings making this type of full wave rectifying circuit costly
compared to the “Full Wave Bridge Rectifier” circuit equivalent.

Full Wave Bridge Rectifier

Another type of circuit that produces the same output waveform as the full wave
rectifier circuit above, is that of the Full Wave Bridge Rectifier. This type of
single-phase rectifier uses four individual rectifying diodes connected in a closed
loop “bridge” configuration to produce the desired output.

The main advantage of this bridge circuit is that it does not require a special centre
tapped transformer, thereby reducing its size and cost. The single secondary

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winding is connected to one side of the diode bridge network and the load to the
other side as shown below.

Working

The four diodes labelled D1 to D4 are arranged in “series pairs” with only two
diodes conducting current during each half cycle. During the positive half cycle
of the supply, diodes D1 and D2 conduct in series while diodes D3 and D4 are
reverse biased and the current flows through the load as shown below.

The Positive Half-cycle

During the negative half cycle of the supply, diodes D 3 and D4 conduct in series,
but diodes D1 and D2 switch “OFF” as they are now reverse biased. The current
flowing through the load is the same direction as before.

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The Negative Half-cycle

As the current flowing through the load is unidirectional, so the voltage developed
across the load is also unidirectional the same as for the previous two diode full-
wave rectifier.

Full-wave Rectifier with Capacitor filter

The capacitor filter converts the full-wave rippled output of the rectifier into a
smoother DC output voltage. Previously the load voltage followed the rectified
output waveform down to zero volts. Here the capacitor is charged to the peak
voltage of the output DC pulse, but when it drops from its peak voltage back
down to zero volts, the capacitor cannot discharge as quickly due to the RC time
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constant of the circuit. In other words, the capacitor only has time to discharge
briefly before the next DC pulse recharges it back up to the peak value. Thus, the
DC voltage applied to the load resistor drops only by a small amount.

However, there are two important parameters to consider when choosing a

suitable smoothing capacitor and these are its Working Voltage, which must be
higher than the no-load output value of the rectifier and its Capacitance Value,
which determines the amount of ripple that will appear superimposed on top of
the DC voltage.

Too low a capacitance value and the capacitor have little effect on the output
waveform. But if the smoothing capacitor is sufficiently large enough (parallel
capacitors can be used) and the load current is not too large, the output voltage
will be almost as smooth as pure DC.

Photodiode
It is a form of light-weight sensor that converts light energy into electrical voltage
or current. Photodiode is a type of semi conducting device with PN junction.
Between the p (positive) and n (negative) layers, an intrinsic layer is present. The
photo diode accepts light energy as input to generate electric current.

It is also called as Photodetector, photo sensor or light detector. Photo diode

operates in reverse bias condition i.e. the p – side of the photodiode is connected
with negative terminal of battery (or the power supply) and n – side to the positive
terminal of battery.

Typical photodiode materials are Silicon, Germanium, Indium Gallium Arsenide

Phosphide and Indium gallium arsenide.

Internally, a photodiode has optical filters, built in lens and a surface area. When
surface area of photodiode increases, it results in more response time. Few photo
diodes will look like Light Emitting Diode (LED). It has two terminals as shown
below. The smaller terminal acts as cathode and longer terminal acts as anode.

The symbol of the photodiode is similar to that of an LED but the arrows point
inwards as opposed to outwards in the LED. The following image shows the
symbol of a photodiode.

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Working
Generally, when a light is made to illuminate the PN junction, covalent bonds are
ionized. This generates hole and electron pairs. Photocurrents are produced due
to generation of electron-hole pairs. Electron hole pairs are formed when photons
of energy more than 1.1eV hits the diode. When the photon enters the depletion
region of diode, it hits the atom with high energy. This results in release of
electron from atom structure. After the electron release, free electrons and hole
are produced.

In general, an electron will have negative charge and holes will have a positive
charge. The depletion energy will have built in electric filed. Due to that electric
filed, electron hole pairs moves away from the junction. Hence, holes move to
anode and electrons move to cathode to produce photo current. The photon
absorption intensity and photon energy are directly proportional to each other.

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When energy of photos is less, the absorption will be more. This entire process is
known as Inner Photoelectric Effect.

Intrinsic Excitations and Extrinsic Excitations are the two methods via which the
photon excitation happens. The process of intrinsic excitation happens, when an
electron in the valence band is excited by photon to conduction band.

Modes of operation of a Photo Diode

Photodiode operates in three different modes namely Photovoltaic mode,
Photoconductive mode and Avalanche diode mode.

Photovoltaic Mode
This is otherwise called as Zero Bias mode. When a photodiode operates low
frequency applications and ultra-level light applications, this mode is preferred.
When photodiode is irradiated by flash of light, voltage is produced. The voltage
produced will be in very small dynamic range and it has a non-linear
characteristic.

Photoconductive Mode
In this mode, photodiode will act in reverse biased condition. Cathode will be
positive and anode will be negative. When the reverse voltage increases, the
width of the depletion layer also increases. Due to this the response time and
junction capacitance will be reduced. Comparatively this mode of operation is
fast and produces electronic noise.

Avalanche Diode Mode

In this mode, avalanche diode operates at a high reverse bias condition. It allows
multiplication of an avalanche breakdown to each photo-produced electron-hole
pair. Hence, this produces internal gain within photodiode. The internal gain
increases the device response.

Applications of Photodiode
• In a simple day to day applications, photodiodes are used. The reason for
their use is their linear response of photodiode to a light illumination. When
more amount of light falls on the sensor, it produces high amount of
current. The increase in current will be displayed on a galvanometer
connected to the circuit.

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• Photodiodes helps to provide an electric isolation with help of

optocouplers. When two isolated circuits are illuminated by light,
optocouplers is used to couple the circuit optically. But the circuits will be
isolated electrically. Compared to conventional devices, optocouplers are
fast.
• Photodiodes are applied in safety electronics like fire and smoke detectors.
It is also used in TV units.
• When utilized in cameras, they act as photo sensors. It is used in
scintillators charge-coupled devices, photoconductors, and photomultiplier
tubes.
• Photodiodes are also widely used in numerous medical applications like
instruments to analyse samples, detectors for computed tomography and
also used in blood gas monitors.

Light Emitting Diode (LED)

A light releasing diode is an electric component that emits light when the electric
current flows through it. It is a light source based on semiconductors. When
current passes through the LED, the electrons recombine with holes emitting light
in the process. It is a specific type of diode having similar characteristics as the
p-n junction diode. Which means that an LED allows the flow of current in its
forward direction while it blocks the flow in the reverse direction. Light-emitting
diodes are built using a weak layer of heavily doped semiconductor material.
Based on the semiconductor material used and the amount of doping, an LED
will emit a coloured light at a particular spectral wavelength when forward biased.

The symbol is similar to that of the p-n junction diode. The difference between
these two symbols is that the two arrows indicate that the diode is emitting the
light.

Working Principle of LED

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The holes lie in the valence band, while the free electrons are in the conduction
band. When there is a forward bias in the p-n junction, the electron which is a
part of the n-type semiconductor material would overrun the p-n junction and join
with the holes in the p-type semiconductor material. Therefore, regarding
the holes, the free electrons would be at the higher energy bands.

When this movement of free electron and hole takes place, there is a change in
the energy level as the voltage drops from the conduction band to the valance
band. There is a release of energy due to the motion of the electron. In standard
diodes, the release of energy in the manner of heat. But in LED the release of
energy in the form of photons that would emit the light energy. The entire process
is known as electroluminescence, and the diodes are known as a light-emitting
diode.

In LED, energy discharged in light form hinges on the forbidden energy gap. One
could manipulate the wavelength of the light produced. Therefore, from its
wavelength, the light colour and its visibility or cannot be controlled. The colour
and wavelength of the light emitted can be determined by doping it with several
impurities.

Uses of LED
LEDs find application in various fields, including optical communication, alarm
and security systems, remote-controlled operations, robotics etc. It finds usage in
many such areas because of its long-lasting capability, low power requirements,
swift response time and fast switching capabilities. Below are a few standards
LED uses:

o Used for TV back-lighting

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o Uses in displays
o Used in automotive
o LEDs used in the dimming of lights

There are different types of light emitting diodes present and some of them are
mentioned below.

• Gallium Arsenide (GaAs) – infra-red

• Gallium Arsenide Phosphide (GaAsP) – red to infra-red, orange
• Aluminium Gallium Arsenide Phosphide (AlGaAsP) – high-brightness
red, orange-red, orange, and yellow
• Gallium Phosphide (GaP) – red, yellow and green
• Aluminium Gallium Phosphide (AlGaP) – green
• Gallium Nitride (GaN) – green, emerald green
• Gallium Indium Nitride (GaInN) – near ultraviolet, bluish-green and blue
• Silicon Carbide (SiC) – blue as a substrate
• Zinc Selenide (ZnSe) – blue
• Aluminium Gallium Nitride (AlGaN) – ultraviolet

Photocoupler/Optocoupler/Optoisolator
Optocoupler or photocoupler is a semiconductor device that uses a short optical
path or link to couple a signal from one electrical circuit to another whilst
providing electrical isolation. Photocouplers or optocouplers are used to provide
many functions: they can be used to link data across two circuits, they can be used
within optical encoders, where the optocoupler provides a means of detecting
visible edge transitions on an encoder wheel to detect position, etc., and they can
be used in many other circuits where optical links and transitions are needed.

The opto-coupler is a component that contains the two elements required for an
opto-isolator:

Light emitter: The light emitter is on the input side and takes the incoming
signal and converts it into a light signal. Typically, the light emitter is a light
emitting diode.

Light detector: The light detector within the opto-coupler or opto-isolator

detects the light from the emitter and converts it back into an electrical signal.
The light detector can be any one of a number of different types of device from a
photodiode to a phototransistor, photodarlington, etc.

The light emitter and detector are tailored to match one another, having matching
wavelengths so that the maximum coupling is achieved.

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Fixed Voltage Regulators

These regulators provide a constant output voltage. A popular example is the
7805 IC which provides a constant 5 volts output. A fixed voltage regulator can
be a positive voltage regulator or a negative voltage regulator. A positive voltage
regulator provides with constant positive output voltage. All those IC’s in the
78XX series are fixed positive voltage regulators. In the IC nomenclature – 78XX
; the part XX denotes the regulated output voltage the IC is designed for.
Examples:- 7805, 7806, 7809 etc.

A negative fixed voltage regulator is same as the positive fixed voltage regulator
in design, construction & operation. The only difference is in the polarity of
output voltages. These IC’s are designed to provide a negative output voltage.
Example:- 7905, 7906 and all those IC’s in the 79XX series.

7805 IC Rating
• Input voltage range 7V- 35V
• Current rating Ic = 1A
• Output voltage range VMax=5.2V ,VMin=4.8V

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Pin Details of 7805 IC

Pin No. Pin Function Description

In this pin of the IC positive unregulated

1 INPUT Input voltage (7V-35V)
voltage is given in regulation.

In this pin where the ground is given. This pin

2 GROUND Ground (0V)
is neutral for equally the input and output.

Regulated output; 5V The output of the regulated 5V volt is taken

3 OUTPUT
(4.8V-5.2V) out at this pin of the IC regulator.

Field Effect Transistors (FET)

1. The Field effect transistor is abbreviated as FET, is another semiconductor
device like a BJT which can be used as an amplifier or switch.
2. The Field effect transistor is a voltage operated device. Whereas Bipolar
junction transistor is a current controlled device. Unlike BJT a FET requires
virtually no input current.
3. This gives it an extremely high input resistance, which is its most important
advantage over a bipolar transistor.
4. FET is also a three-terminal device, labelled as source, drain and gate.
5. The source can be viewed as BJT’s emitter, the drain as collector, and the gate
as the counterpart of the base.

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6. The material that connects the source to drain is referred to as the channel.
7. FET operation depends only on the flow of majority carriers; therefore, they
are called unipolar devices. BJT operation depends on both minority and majority
carriers.
8. As FET has conduction through only majority carriers it is less noisy than BJT.
9. FETs are much easier to fabricate and are particularly suitable for ICs because
they occupy less space than BJTs.
10. FET amplifiers have low gain bandwidth product due to the junction
capacitive effects and produce more signal distortion except for small signal
operation.
11. The performance of FET is relatively unaffected by ambient temperature
changes. As it has a negative temperature coefficient at high current levels, it
prevents the FET from thermal breakdown. The BJT has a positive temperature
coefficient at high current levels which leads to thermal breakdown.

CLASSIFICATION OF FET
There are two major categories of field effect transistors:
1. Junction Field Effect Transistors
2. MOSFETs
These are further sub divided in to P- channel and N-channel devices.
MOSFETs are further classified in to two types Depletion MOSFETs and
Enhancement. MOSFETs When the channel is of N-type the JFET is referred to
as an N-channel JFET ,when the channel is of P-type the JFET is referred to as
P-channel JFET. The schematic symbols for the P-channel and N-channel JFETs
are shown in the figure.

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CONSTRUCTION AND OPERATION OF N- CHANNEL

FET

A piece of N- type material, referred to as channel has two smaller pieces of P-

type material attached to its sides, forming PN junctions. The channel ends are
designated as the drain and source. And the two pieces of P-type material are
connected together and their terminal is called the gate. Since this channel is in
the N-type bar, the FET is known as N-channel JFET.

OPERATION OF N-CHANNEL JFET

The overall operation of the JFET is based on varying the width of the channel to
control the drain current. A piece of N type material referred to as the channel,
has two smaller pieces of P type material attached to its sites, farming PN –
Junctions. The channel’s ends are designated the drain and the source. And the
two pieces of P type material are connected together and their terminal is called
the gate. With the gate terminal not connected and the potential applied positive
at the drain negative at the source a drain current Id flows. When the gate is biased
negative with respective to the source the PN junctions are reverse biased and
depletion regions are formed. The channel is more lightly doped than the P type
gate blocks, so the depletion regions penetrate deeply into the channel. Since
depletion region is a region depleted of charge carriers it behaves as an Insulator.
The result is that the channel is narrowed. Its resistance is increased and Id is
reduced. When the negative gate bias voltage is further increased, the depletion
regions meet at the center and Id is cut off completely.
There are two ways to control the channel width
1. By varying the value of Vgs
2. And by Varying the value of Vds holding Vgs constant

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By varying the value of Vgs:-

We can vary the width of the channel and in turn vary the amount of drain current.
This can be done by varying the value of Vgs. This point is illustrated in the fig
below. Here we are dealing with N channel FET. So, channel is of N type and
gate is of P type that constitutes a PN junction. This PN junction is always reverse
biased in JFET operation. The reverse bias is applied by a battery voltage Vgs
connected between the gate and the source terminal i.e. positive terminal of the
battery is connected to the source and negative terminal to gate.

1) When a PN junction is reverse biased the electrons and holes diffuse across
junction by leaving immobile ions on the N and P sides, the region containing
these immobile ions is known as depletion regions.
2) If both P and N regions are heavily doped then the depletion region extends
symmetrically on both sides.
3) But in N channel FET P region is heavily doped than N type thus depletion
region extends more in N region than P region.
4) So, when no Vds is applied the depletion region is symmetrical and the
conductivity becomes Zero. Since there are no mobile carriers in the junction.
5) As the reverse bias voltage is increases the thickness of the depletion region
also increases. i.e. the effective channel width decreases.
6) By varying the value of Vgs we can vary the width of the channel.

Varying the value of Vds holding Vgs constant :-

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1.When no voltage is applied to the gate i.e. Vgs=0, Vds is applied between
source and drain the electrons will flow from source to drain through the channel
constituting drain current Id.
2) With Vgs= 0 for Id= 0 the channel between the gate junctions is entirely open.
In response to a small applied voltage Vds, the entire bar acts as a simple
semiconductor resistor and the current Id increases linearly with Vds .
3) The channel resistances are represented as rd and rs as shown in the fig.

4. This increasing drain current Id produces a voltage drop across rd which

reverse biases the gateto source junction, (rd> rs). Thus the depletion region is
formed which is not symmetrical.
5) The depletion region i.e. developed penetrates deeper in to the channel near
drain and less towards source because Vrd >> Vrs. So reverse bias is higher near
drain than at source.
6) As a result, growing depletion region reduces the effective width of the
channel. Eventually a voltage Vds is reached at which the channel is pinched off.
This is the voltage where the current Id begins to level off and approach a constant
value.
7) So, by varying the value of Vds we can vary the width of the channel holding
Vgs constant.
When both Vgs and Vds is applied:

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It is of course in principle not possible for the channel to close Completely and
there by reduce the current Id to Zero for, if such indeed, could be the case the
gate voltage Vgs is applied in the direction to provide additional reverse bias
1) When voltage is applied between the drain and source with a battery Vdd, the
electrons flow from source to drain through the narrow channel existing between
the depletion regions. This constitutes the drain current Id, its conventional
direction is from drain to source.
2) The value of drain current is maximum when no external voltage is applied
between gate and source and is designated by Idss.

3) When Vgs is increased beyond Zero the depletion regions are widened. This
reduces the effective width of the channel and therefore controls the flow of drain
current through the channel.
4) When Vgs is further increased a stage is reached at which to depletion regions
touch each other that means the entire channel is closed with depletion region.
This reduces the drain current to Zero.

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CHARACTERISTICS OF N-CHANNEL JFET

The family of curves that shows the relation between current and voltage are
known as characteristic curves.
There are two important characteristics of a JFET.
1) Drain or VI Characteristics
2) Transfer characteristics
Drain Characteristics
Drain characteristics shows the relation between the drain to source voltage Vds
and drain current Id. In order to explain typical drain characteristics, let us
consider the curve with Vgs= 0.V.

1) When Vds is applied and it is increasing the drain current ID also increases
linearly up to knee point.
2) This shows that FET behaves like an ordinary resistor. This region is called
as ohmic region.
3) ID increases with increase in drain to source voltage. Here the drain current is
increased slowly as compared to ohmic region.

4) It is because of the fact that there is an increase in VDS .This in turn increases
the reverse bias voltage across the gate source junction .As a result of this
depletion region grows in size thereby reducing the effective width of the channel.
5) All the drain to source voltage corresponding to point the channel width is
reduced to a minimum value and is known as pinch off.
6) The drain to source voltage at which channel pinch off occurs is called pinch
off voltage(Vp).
PINCH OFF Region:-

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1) This is the region shown by the curve as saturation region.

2) It is also called as saturation region or constant current region. Because of the
channel is occupied with depletion region, the depletion region is more towards
the drain and less towards the source, so the channel is limited, with this only
limited number of carriers are only allowed to cross this channel from source
drain causing a current that is constant in this region. To use FET as an amplifier
it is operated in this saturation region.
3) In this drain current remains constant at its maximum value IDSS.
4) The drain current in the pinch off region depends upon the gate to source
voltage and is given by the relation

This is known as shokley’s relation.

BREAKDOWN REGION:-

1) The region is shown by the curve .In this region, the drain current increases
rapidly as the drain to source voltage is increased.
2) It is because of the gate to source junction due to avalanche effect.
3) The avalanche break down occurs at progressively lower value of VDS because
the reverse bias gate voltage adds to the drain voltage thereby increasing effective
voltage across the gate junction.
This causes
1.The maximum saturation drain current is smaller
2.The ohmic region portion decreased.

4) It is important to note that the maximum voltage VDS which can be applied to
FET is the lowest voltage which causes available break down.
TRANSFER CHARACTERISTICS
These curves shows the relationship between drain current ID and gate to source
voltage VGS for different values of VDS.
1) First adjust the drain to source voltage to some suitable value, then increase
the gate to source voltage in small suitable value.
2) Plot the graph between gate to source voltage along the horizontal axis and
current ID on the vertical axis. We shall obtain a curve like this.

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3) As we know that if Vgs is more negative curves drain current to reduce. where
Vgs is made sufficiently negative, Id is reduced to zero. This is caused by the
widening of the depletion region to a point where it is completely closes the
channel. The value of Vgs at the cut-off point is designed as Vgsoff
4) The upper end of the curve as shown by the drain current value is equal to I
dss that is when Vgs = 0 the drain current is maximum.
5) While the lower end is indicated by a voltage equal to Vgsoff
6) If Vgs continuously increasing, the channel width is reduced, then Id =0
7) It may be noted that curve is part of the parabola; it may be expressed as

DIFFERENCE BETWEEN Vp AND Vgsoff –

Vp is the value of Vgs that causes the JFET to become constant current
component, it is measured at Vgs =0V and has a constant drain current of Id =Idss.
Where Vgsoff is the value of Vgs that reduces Id to approximately zero.
Why the gate to source junction of a JFET be always reverse biased?
The gate to source junction of a JFET is never allowed to become forward biased
because the gate material is not designed to handle any significant amount of

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current. If the junction is allowed to become forward biased, current is generated

through the gate material. This current may destroy the component.
There is one more important characteristic of JFET reverse biasing i.e. J FET ‘s
has extremely high characteristic gate input impedance. This impedance is
typically in the high mega ohm range. With the advantage of extremely high input
impedance it draws no current from the source. The high input impedance of the
JFET has led to its extensive use in integrated circuits. The low current
requirements of the component make it perfect for use in ICs. Where thousands
of transistors must be etched on to a single piece of silicon. The low current draw
helps the IC to remain relatively cool, thus allowing more components to be
placed in a smaller physical area.
JFET PARAMETERS
The electrical behavior of JFET may be described in terms of certain parameters.
Such parameters are obtained from the characteristic curves.
A C Drain resistance(rd):
It is also called dynamic drain resistance and is the a.c.resistance between the
drain and source terminal, when the JFET is operating in the pinch off or
saturation region. It is given by the ratio of small
change in drain to source voltage ∆Vds to the corresponding change in drain
current ∆Id for a constant gate to source voltage Vgs.
Mathematically it is expressed as rd=∆Vds/ ∆Id where Vgs is held constant.
TRANSCONDUCTANCE (gm):
It is also called forward transconductance. It is given by the ratio of small change
in drain current (∆Id) to the corresponding change in gate to source voltage (∆Vds)
Mathematically the transconductance can be written as
gm=∆Id/∆Vds
AMPLIFICATION FACTOR (µ)
It is given by the ratio of small change in drain to source voltage (∆V ds) to the
corresponding change in gate to source voltage (∆Vgs) for a constant drain
current (Id).
Thus µ=∆Vds/∆Vgs when Id held constant.
The amplification factor µ may be expressed as a product of transconductance
(gm)and ac drain resistance (rd)

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µ=∆Vds/∆Vgs=gm rd

METAL OXIDE SEMICONDUCTOR FIELD EFFECT TRANSISTOR

(MOSFET)
We now turn our attention to the insulated gate FET or metal oxide semi
conductor FET which is having the greater commercial importance than the
junction FET.
Most MOSFETS however are triodes, with the substrate internally connected to
the source. The circuit symbols used by several manufacturers are indicated in
the Fig below.

Both of them are P- channel

Here are two basic types of MOSFETS
(1) Depletion type (2) Enhancement type MOSFET.
D-MOSFETS can be operated in both the depletion mode and the enhancement
mode. E MOSFETS are restricted to operate in enhancement mode. The primary
difference between them is their physical construction. The construction
difference between the two is shown in the fig given below.

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As we can see the D MOSFET have physical channel between the source and
drain terminals (Shaded area).

The E MOSFET on the other hand has no such channel physically. It depends on
the gate voltage to form a channel between the source and the drain terminals.
Both MOSFETS have an insulating layer between the gate and the rest of the
component. This insulating layer is made up of SiO2 a glass like insulating
material. The gate material is made up of metal conductor. Thus, going from gate
to substrate, we can have metal oxide semiconductor which is where the term
MOSFET comes from.
Since the gate is insulated from the rest of the component, the MOSFET is
sometimes referred to as an insulated gate FET or IGFET.

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The foundation of the MOSFET is called the substrate. This material is

represented in the schematic symbol by the centre line that is connected to the
source.
In the symbol for the MOSFET, the arrow is placed on the substrate. As with
JFET an arrow pointing in represents an N-channel device, while an arrow
pointing out represents p-channel device.
CONSTRUCTION OF AN N-CHANNEL MOSFET: -
The N- channel MOSFET consists of a lightly doped p type substance into which
two heavily doped n+ regions are diffused as shown in the Fig. These n+ sections,
which will act as source and drain. A thin layer of insulation silicon dioxide
(SiO2) is grown over the surface of the structure, and holes are cut into oxide
layer, allowing contact with the source and drain. Then the gate metal area is
overlaid on the oxide, covering the entire channel region. Metal contacts are made
to drain and source and the contact to the metal over the channel area is the gate
terminal. The metal area of the gate, in conjunction with the insulating dielectric
oxide layer and the semiconductor channel, forms a parallel plate capacitor. The
insulating layer of SiO2 is the reason why this device is called the insulated gate
field effect transistor. This layer results in an extremely high input for MOSFET.
DEPLETION MOSFET
The basic structure of D –MOSFET is shown in the fig. An N-channel is diffused
between source and drain with the device an appreciable drain current IDSS flows
foe zero gate to source voltage, Vgs=0.

Depletion mode operation: -

1) The above fig shows the D-MOSFET operating conditions with gate and
source terminals shorted together (VGS=0V)
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2) At this stage ID= IDSS where VGS=0V, with this voltage VDS, an appreciable
drain current IDSS flow.
3) If the gate to source voltage is made negative i.e. VGS is negative. Positive
charges are induced in the channel through the SiO2 of the gate capacitor.
4) Since the current in a FET is due to majority carriers (electrons for an N-type
material), the induced positive charges make the channel less conductive and the
drain current drops as Vgs is made more negative.
5) The re distribution of charge in the channel causes an effective depletion of
majority carriers, which accounts for the designation depletion MOSFET.
6) That means biasing voltage Vgs depletes the channel of free carriers. This
effectively reduces the width of the channel, increasing its resistance.
7) Note that negative Vgs has the same effect on the MOSFET as it has on the
JFET.

8) As shown in the fig above, the depletion layer generated by Vgs (represented
by the white space between the insulating material and the channel) cuts into the
channel, reducing its width. As a result, Id<Idss. The actual value of ID depends
on the value of Idss, Vgs(off) and Vgs.
Enhancement mode operation of the D-MOSFET: -
1) This operating mode is a result of applying a positive gate to source voltage
Vgs to the device.
2) When Vgs is positive the channel is effectively widened. This reduces the
resistance of the channel allowing ID to exceed the value of IDSS

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3) When Vgs is given positive the majority carriers in the p-type are holes. The
holes in the p type substrate are repelled by the +ve gate voltage.
4) At the same time, the conduction band electrons (minority carriers) in the p
type material are attracted towards the channel by the +gate voltage.
5) With the build-up of electrons near the channel, the area to the right of the
physical channel effectively becomes an N type material.
6) The extended n type channel now allows more current, Id> Idss.

Characteristics of Depletion MOSFET: -

The fig. shows the drain characteristics for the N channel depletion type
MOSFET
1) The curves are plotted for both Vgs positive and Vgs negative voltages.
2) When Vgs=0 and negative the MOSFET operates in depletion mode when Vgs
is positive, the MOSFET operates in the enhancement mode.
3) The difference between JFET and D MOSFET is that JFET does not operate
for positive values of Vgs.
4) When Vds=0, there is no conduction takes place between source to drain, if
Vgs<0 and Vds>0 then Id increases linearly.
5) But as Vgs,0 induces positive charges holes in the channel, and controls the
channel width. Thus, the conduction between source to drain is maintained as
constant, i.e. Id is constant.
6) If Vgs>0 the gate induces more electrons in channel side, it is added with the
free electrons generated by source. again the potential applied to gate determines
the channel width and maintains constant current flow through it as shown in Fig.

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TRANSFER CHARACTERISTICS: -
The combination of 3 operating states i.e. Vgs=0V, VGs<0V, Vgs>0V is
represented by the DMOSFET transconductance curve shown in Fig.

1. Here in this curve it may be noted that the region AB of the

characteristics similar to that of JFET.
2. This curve extends for the positive values of Vgs.
3. Note that Id=Idss for Vgs=0V when Vgs is negative, Id< Idss when
Vgs= Vgs(off) ,Id is reduced to approximately 0 mA. Where Vgs is

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positive Id>Idss. So obviously Idss is not the maximum possible

value of Id for a MOSFET.
4. The curves are similar to JFET so that the D MOSFET have the same
transconductance equation.
E-MOSFETS
The E MOSFET is capable of operating only in the enhancement mode. The gate
potential must be positive w.r.t to source.

1) when the value of Vgs=0V, there is no channel connecting the source and drain
materials.
2) As a result, there can be no significant amount of drain current.
3) When Vgs=0, the Vdd supply tries to force free electrons from source to drain
but the presence of p-region does not permit the electrons to pass through it. Thus,
there is no drain current at Vgs=0,
4) If Vgs is positive, it induces a negative charge in the p type substrate just
adjacent to the SiO2 layer.
5) As the holes are repelled by the positive gate voltage, the minority carrier
electrons attracted toward this voltage. This forms an effective N type bridge
between source and drain providing a path for drain current.
6) This +ve gate voltage forma a channel between the source and drain.
7) This produces a thin layer of N type channel in the P type substrate. This layer
of free electrons is called N type inversion layer.

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8) The minimum Vgs which produces this inversion layer is called threshold
voltage and is designated by Vgs(th).This is the point at which the device turns
on is called the threshold voltage Vgs(th)
9) When the voltage Vgs is <Vgs (th) no current flows from drain to source.
10) However, when the voltage Vgs > Vgs (th) the inversion layer connects the
drain to source and we get significant values of current.
CHARACTERISTICS OF E MOSFET: -
1. DRAIN CHARACTERISTICS
The volt ampere drain characteristics of an N-channel enhancement mode
MOSFET are given in the

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2. TRANSFER CHARACTERISTICS: -
1) The current Idss at Vgs≤ 0 is very small being of the order of a few nano amps.
2) As Vgs is made +ve, the current Id increases slowly at forst, and then much
more rapidly with an increase in Vgs.
3) The standard transconductance formula will not work for the E MOSFET.
4) To determine the value of ID at a given value of VGs we must use the following
relation Id =K[Vgs-Vgs(Th)]2
Where K is constant for the MOSFET found as

Operational Amplifiers:

The operational amplifier is a direct-coupled high gain amplifier usable from 0 to

over 1MHz to which feedback is added to control its overall response
characteristic i.e. gain and bandwidth. The op-amp exhibits the gain down to zero
frequency.

Such direct coupled (dc) amplifiers do not use blocking (coupling and by pass)
capacitors since these would reduce the amplification to zero at zero frequency.

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Large by pass capacitors may be used but it is not possible to fabricate large
capacitors on a IC chip. The capacitors fabricated are usually less than 20 pf.
Transistor, diodes and resistors are also fabricated on the same chip.

Differential Amplifiers:

Differential amplifier is a basic building block of an op-amp. The function of a

differential amplifier is to amplify the difference between two input signals.

How the differential amplifier is developed? Let us consider two emitter-biased

circuits as shown in fig. 1.

Fig. 1

The two transistors Q1 and Q2 have identical characteristics. The resistances of

the circuits are equal, i.e. RE1 = R E2, RC1 = R C2 and the magnitude of +VCC is
equal to the magnitude of –VEE. These voltages are measured with respect to
ground.

To make a differential amplifier, the two circuits are connected as shown in fig.
1. The two +VCC and –VEE supply terminals are made common because they are
same. The two emitters are also connected and the parallel combination of RE1
and RE2 is replaced by a resistance RE. The two input signals v1 & v2 are applied
at the base of Q1 and at the base of Q2. The output voltage is taken between two
collectors. The collector resistances are equal and therefore denoted by RC = RC1
= RC2.

Ideally, the output voltage is zero when the two inputs are equal. When v 1 is
greater then v2 the output voltage with the polarity shown appears. When v 1 is
less than v2, the output voltage has the opposite polarity.

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The differential amplifiers are of different configurations.

The four differential amplifier configurations are following:

1. Dual input, balanced output differential amplifier.

2. Dual input, unbalanced output differential amplifier.
3. Single input balanced output differential amplifier.
4. Single input unbalanced output differential amplifier.

Fig. 2

These configurations are shown in fig. 2, and are defined by number of input
signals used and the way an output voltage is measured. If use two input signals,
the configuration is said to be dual input, otherwise it is a single input
configuration. On the other hand, if the output voltage is measured between two

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collectors, it is referred to as a balanced output because both the collectors are at

the same dc potential w.r.t. ground. If the output is measured at one of the
collectors w.r.t. ground, the configuration is called an unbalanced output.

A multistage amplifier with a desired gain can be obtained using direct

connection between successive stages of differential amplifiers. The advantage
of direct coupling is that it removes the lower cut off frequency imposed by the
coupling capacitors, and they are therefore, capable of amplifying dc as well as
ac input signals.

Dual Input, Balanced Output Differential Amplifier:

The circuit is shown in fig. 1, v1 and v2 are the two inputs, applied to the bases of
Q1 and Q2 transistors. The output voltage is measured between the two collectors
C1 and C2 , which are at same dc potentials.

D.C. Analysis:

To obtain the operating point (ICC and VCEQ) for differential amplifier dc
equivalent circuit is drawn by reducing the input voltages v 1 and v2 to zero as
shown in fig. 3.

Fig. 3

The internal resistances of the input signals are denoted by RS because RS1= RS2.
Since both emitter biased sections of the different amplifier are symmetrical in
all respects, therefore, the operating point for only one section need to be
determined. The same values of ICQ and VCEQ can be used for second transistor
Q2.

Applying KVL to the base emitter loop of the transistor Q1.

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The value of RE sets up the emitter current in transistors Q 1 and Q2 for a given
value of VEE. The emitter current in Q1 and Q2 are independent of collector
resistance RC.

The voltage at the emitter of Q1 is approximately equal to -VBE if the voltage drop
across R is negligible. Knowing the value of IC the voltage at the collector VCis
given by

VC =VCC – IC RC

and VCE = VC – VE

= VCC – IC RC + VBE

VCE = VCC + VBE – ICRC (E-2)

From the two equations VCEQ and ICQ can be determined. This dc analysis
applicable for all types of differential amplifier.

Example - 1

The following specifications are given for the dual input, balanced-output
differential amplifier of fig.1:
RC = 2.2 kΩ, RB = 4.7 kΩ, Rin 1 = Rin 2 = 50 Ω , +VCC = 10V, -VEE = -10 V, βdc
=100 and VBE = 0.715V.
Determine the operating points (ICQ and VCEQ) of the two transistors.

Solution:

The value of ICQ can be obtained from equation (E-1).

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The voltage VCEQ can be obtained from equation (E-2).

The values of ICQ and VCEQ are same for both the transistors.

Dual Input, Balanced Output Difference Amplifier:

The circuit is shown in fig. 1 v1 and v2 are the two inputs, applied to the bases of
Q1 and Q2 transistors. The output voltage is measured between the two collectors
C1 and C2, which are at same dc potentials.

Fig. 1

A.C. Analysis :

To find the voltage gain Ad and the input resistance Ri of the differential amplifier,
the ac equivalent circuit is drawn using r-parameters as shown in fig. 2. The dc
voltages are reduced to zero and the ac equivalent of CE configuration is used.

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Fig. 2

Since the two dc emitter currents are equal. Therefore, resistance r'e1 and r'e2 are
also equal and designated by r'e . This voltage across each collector resistance is
shown 180° out of phase with respect to the input voltages v1 and v2. This is same
as in CE configuration. The polarity of the output voltage is shown in Figure. The
collector C2 is assumed to be more positive with respect to collector C1 even
though both are negative with respect to to ground.

Applying KVL in two loops 1 & 2.

Substituting current relations,

Again, assuming RS1 / b and RS2 / b are very small in comparison with RE and re'
and therefore neglecting these terms,

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Solving these two equations, ie1 and ie2 can be calculated.

The output voltage VO is given by

VO = VC2 - VC1

= -RC iC2 - (-RC iC1)

= RC (iC1 - iC2)

= RC (ie1 - ie2)

Substituting ie1, & ie2 in the above expression

Thus a differential amplifier amplifies the difference between two input signals.
Defining the difference of input signals as vd = v1 – v2 the voltage gain of the dual
input balanced output differential amplifier can be given by

(E-2)

Differential Input Resistance:

Differential input resistance is defined as the equivalent resistance that would be

measured at either input terminal with the other terminal grounded. This means
that the input resistance Ri1 seen from the input signal source v1 is determined
with the signal source v2 set at zero. Similarly, the input signal v1 is set at zero to
determine the input resistance Ri2 seen from the input signal source v2. Resistance
RS1 and RS2 are ignored because they are very small.

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Substituting ie1,

Similarly,

The factor of 2 arises because the re' of each transistor is in series.

To get very high input impedance with differential amplifier is to use Darlington
transistors. Another ways is to use FET.

Output Resistance:

Output resistance is defined as the equivalent resistance that would be measured

at output terminal with respect to ground. Therefore, the output resistance R O1
measured between collector C1 and ground is equal to that of the collector
resistance RC. Similarly the output resistance RO2 measured at C2 with respect to
ground is equal to that of the collector resistor RC.

RO1 = RO2 = RC (E-5)

The current gain of the differential amplifier is undefined. Like CE amplifier the
differential amplifier is a small signal amplifier. It is generally used as a voltage
amplifier and not as current or power amplifier.

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Example - 1

The following specifications are given for the dual input, balanced-output
differential amplifier: RC = 2.2 kΩ, RB = 4.7 kΩ, Rin 1 = Rin 2 = 50Ω, +VCC= 10V,
-VEE = -10 V, βdc =100 and VBE = 0.715V.

a. Determine the voltage gain.

b. Determine the input resistance
c. Determine the output resistance.

Solution:

(a). The parameters of the amplifiers are same as discussed in example-1 of

lecture-1. The operating point of the two transistors obtained in lecture-1 are
given below

ICQ = 0.988 mA
VCEQ=8.54V

The ac emitter resistance

Therefore, substituting the known values in voltage gain equation (E-2), we

obtain

b). The input resistance seen from each input source is given by (E-3) and (E-4):

(c) The output resistance seen looking back into the circuit from each of the two
output terminals is given by (E-5)

Ro1 = Ro2 = 2.2 k Ω

Example - 2

For the dual input, balanced output differential amplifier of Example-1:

a. Determine the output voltage (vo) if vin 1 = 50mV peak to peak (pp)
at 1 kHz and vin 2 = 20 mV pp at 1 kHz.

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b. What is the maximum peal to peak output voltage without clipping?

Solution:

(a) In Example-1 we have determined the voltage gain of the dual input,
balanced output differential amplifier. Substituting this voltage gain (Ad = 86.96)
and given values of input voltages in (E-1), we get

(b) Note that in case of dual input, balanced output difference amplifier, the
output voltage vo is measured across the collector. Therefore, to calculate the
maximum peak to peak output voltage, we need to determine the voltage drop
across each collector resistor:

Substituting IC = ICQ = 0.988 mA, we get

This means that the maximum change in voltage across each collector resistor is
± 2.17 (ideally) or 4.34 VPP. In other words, the maximum peak to peak output
voltage without clipping is (2) (4.34) = 8.68 VPP.

A dual input, balanced output difference amplifier circuit is shown in fig. 1.

Fig. 1

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Inverting & Non – inverting Inputs:

In differential amplifier the output voltage vO is given by

VO = Ad (v1 – v2)
When v2 = 0, vO = Ad v1
& when v1 = 0, vO = - Ad v2

Therefore, the input voltage v1 is called the non inventing input because a positive
voltage v1 acting alone produces a positive output voltage vO. Similarly, the
positive voltage v2 acting alone produces a negative output voltage hence v 2 is
called inverting input. Consequently, B1 is called noninverting input terminal and
B2 is called inverting input terminal.

Common mode Gain:

A common mode signal is one that drives both inputs of a differential amplifier
equally. The common mode signal is interference, static and other kinds of
undesirable pickup etc.

The connecting wires on the input bases act like small antennas. If a differential
amplifier is operating in an environment with lot of electromagnetic interference,
each base picks up an unwanted interference voltage. If both the transistors were
matched in all respects then the balanced output would be theoretically zero. This
is the important characteristic of a differential amplifier. It discriminates against
common mode input signals. In other words, it refuses to amplify the common
mode signals.

The practical effectiveness of rejecting the common signal depends on the degree
of matching between the two CE stages forming the differential amplifier. In
other words, more closely are the currents in the input transistors, the better is the
common mode signal rejection e.g. If v1 and v2 are the two input signals, then the
output of a practical op-amp cannot be described by simply

v0 = Ad (v1 – v2)

In practical differential amplifier, the output depends not only on difference

signal but also upon the common mode signal (average).

vd = (v1 – vd)

and vC = ½ (v1 + v2)

The output voltage, therefore can be expressed as

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vO = A1 v1 + A2 v2

Where A1 & A2 are the voltage amplification from input 1(2) to output under the
condition that input 2 (1) is grounded.

The voltage gain for the difference signal is Ad and for the common mode signal
is AC.

The ability of a differential amplifier to reject a common mode signal is expressed

by its common mode rejection ratio (CMRR). It is the ratio of differential gain Ad
to the common mode gain AC.

Date sheet always specify CMRR in decibels CMRR = 20 log CMRR.

Therefore, the differential amplifier should be designed so that r is large

compared with the ratio of the common mode signal to the difference signal. If r
= 1000, vC = 1mV, vd = 1 m V, then

It is equal to first term. Hence for an amplifier with r = 1000, a 1m V difference

of potential between two inputs gives the same output as 1mV signal applied with
the same polarity to both inputs.

Dual Input, Unbalanced Output Differential Amplifier:

In this case, two input signals are given however the output is measured at only
one of the two-collector w.r.t. ground as shown in fig. 2. The output is referred to
as an unbalanced output because the collector at which the output voltage is
measured is at some finite dc potential with respect to ground..

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Fig. 2

In other words, there is some dc voltage at the output terminal without any input
signal applied. DC analysis is exactly same as that of first case.

AC Analysis:

The output voltage gain in this case is given by

The voltage gain is half the gain of the dual input, balanced output differential
amplifier. Since at the output there is a dc error voltage, therefore, to reduce the
voltage to zero, this configuration is normally followed by a level translator
circuit.

Differential amplifier with swamping resistors:

By using external resistors R'E in series with each emitter, the dependence of
voltage gain on variations of r'e can be reduced. It also increases the linearity
range of the differential amplifier.

Fig. 3, shows the differential amplifier with swamping resistor R'E. The value of
R'E is usually large enough to swamp the effect of r'e.

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Fig. 3

Constant Current Bias:

In the dc analysis of differential amplifier, we have seen that the emitter current
IE depends upon the value of bdc. To make operating point stable IE current should
be constant irrespective value of bdc.

For constant IE, RE should be very large. This also increases the value of CMRR
but if RE value is increased to very large value, IE (quiescent operating current)
decreases. To maintain same value of IE, the emitter supply VEE must be
increased. To get very high value of resistance RE and constant IE, current, current
bias is used.

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Figure 5.1

Fig. 1, shows the dual input balanced output differential amplifier using a
constant current bias. The resistance RE is replace by constant current transistor
Q3. The dc collector current in Q3 is established by R1, R2, & RE.

Applying the voltage divider rule, the voltage at the base of Q3 is

Because the two halves of the differential amplifiers are symmetrical, each has
half of the current IC3.

The collector current, IC3 in transistor Q3 is fixed because no signal is injected

into either the emitter or the base of Q3.

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Besides supplying constant emitter current, the constant current bias also provides
a very high source resistance since the ac equivalent or the dc source is ideally an
open circuit. Therefore, all the performance equations obtained for differential
amplifier using emitter bias are also valid.

As seen in IE expressions, the current depends upon VBE3. If temperature changes,

VBE changes and current IE also changes. To improve thermal stability, a diode is
placed in series with resistance R1as shown in fig. 2.

Fig. 2

This helps to hold the current IE3 constant even though the temperature changes. Applying KVL
to the base circuit of Q3.

Therefore, the current IE3 is constant and independent of temperature because of

the added diode D. Without D the current would vary with temperature because
VBE3 decreases approximately by 2mV/° C. The diode has same temperature
dependence and hence the two variations cancel each other and IE3 does not vary
appreciably with temperature. Since the cut – in voltage VD of diode
approximately the same value as the base to emitter voltage V BE3 of a transistor
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the above condition cannot be satisfied with one diode. Hence two diodes are
used in series for VD. In this case the common mode gain reduces to zero.

Some times zener diode may be used in place of

diodes and resistance as shown in fig. 3. Zeners are
available over a wide range of voltages and can
have matching temperature coefficient

The voltage at the base of transistor QB is

Fig. 3

The value of R2 is selected so that I2 » 1.2 IZ(min) where IZ is the minimum current
required to cause the zener diode to conduct in the reverse region, that is to block
the rated voltage VZ.

Current Mirror:

The circuit in which the output current is forced to equal the input current is said
to be a current mirror circuit. Thus in a current mirror circuit, the output current
is a mirror image of the input current. The current mirror circuit is shown in fig.
4.

Fig. 4

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Once the current I2 is set up, the current IC3 is automatically established to be
nearly equal to I2. The current mirror is a special case of constant current bias and
the current mirror bias requires of constant current bias and therefore can be used
to set up currents in differential amplifier stages. The current mirror bias requires
fewer components than constant current bias circuits.

Since Q3 and Q4 are identical transistors the current and voltage are
approximately same

For satisfactory operation two identical transistors are necessary.

The operation amplifier:

An operational amplifier is a direct coupled high gain amplifier consisting of one

or more differential (OPAMP) amplifiers and followed by a level translator and
an output stage. An operational amplifier is available as a single integrated circuit
package. The block diagram of OPAMP is shown in fig. 1.

Fig. 1

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The input stage is a dual input balanced output differential amplifier. This stage
provides most of the voltage gain of the amplifier and also establishes the input
resistance of the OPAMP.The intermediate stage of OPAMP is another
differential amplifier which is driven by the output of the first stage. This is
usually dual input unbalanced output.

Because direct coupling is used, the dc voltage level at the output of intermediate
stage is well above ground potential. Therefore, level shifting circuit is used to
shift the dc level at the output downward to zero with respect to ground. The
output stage is generally a push pull complementary amplifier. The output stage
increases the output voltage swing and raises the current supplying capability of
the OPAMP. It also provides low output resistance.

Level Translator:

Because of the direct coupling the dc level at the

emitter rises from stages to stage. This increase
in dc level tends to shift the operating point of
the succeeding stages and therefore limits the
output voltage swing and may even distort the
output signal.

To shift the output dc level to zero, level

translator circuits are used. An emitter follower
with voltage divider is the simplest form of level
translator as shown in fig. 2.

Thus a dc voltage at the base of Q produces 0V

dc at the output. It is decided by R1 and R2.
Instead of voltage divider emitter follower
either with diode current bias or current mirror
bias as shown in fig. 3 may be used to get better
results. Fig. 2

In this case, level shifter, which is common

collector amplifier, shifts the level by 0.7V. If
this shift is not sufficient, the output may be
taken at the junction of two resistors in the
emitter leg.

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Fig. 3

Fig. 4, shows a complete OPAMP circuit having input different amplifiers with
balanced output, intermediate stage with unbalanced output, level shifter and an
output amplifier.

Fig. 4

The symbolic diagram of an OPAMP is shown in fig.

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741c is most commonly used OPAMP available in IC package. It is an 8-pin DIP

chip.

Parameters of OPAMP:

The various important parameters of OPAMP are follows:

1.Input Offset Voltage:

Input offset voltage is defined

as the voltage that must be
applied between the two input
terminals of an OPAMP to null
or zero the output fig. 2, shows
that two dc voltages are
applied to input terminals to
make the output zero.

Vio = Vdc1 – Vdc2

Vdc1 and Vdc2 are dc voltages

and RS represents the source
resistance. Vio is the difference
of Vdc1 and Vdc2. It may be
positive or negative. For a
741C OPAMP the maximum
value of Vio is 6mV. It means a Fig. 2
voltage ± 6 mV is required to
one of the input to reduce the
output offset voltage to zero.
The smaller the input offset
voltage the better the
differential amplifier, because
its transistors are more closely
matched.

2. Input offset Current:

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The input offset current Iio is the difference between the currents into inverting
and non-inverting terminals of a balanced amplifier.

Iio = | IB1 – IB2 |

The Iio for the 741C is 200nA maximum. As the matching between two input
terminals is improved, the difference between IB1 and IB2 becomes smaller, i.e.
the Iio value decreases further.For a precision OPAMP 741C, Iio is 6 nA

3.Input Bias Current:

The input bias current IB is the average of the current entering the input terminals
of a balanced amplifier i.e.

IB = (IB1 + IB2) / 2

For 741C IB(max) = 700 nA and for precision 741C IB = ± 7 nA

4. Differential Input Resistance: (Ri)

Ri is the equivalent resistance that can be measured at either the inverting or non-
inverting input terminal with the other terminal grounded. For the 741C the input
resistance is relatively high 2 MΩ. For some OPAMP it may be up to 1000 G
ohm.

5. Input Capacitance: (Ci)

Ci is the equivalent capacitance that can be measured at either the inverting and
noninverting terminal with the other terminal connected to ground. A typical
value of Ci is 1.4 pf for the 741C.

6. Offset Voltage Adjustment Range:

741 OPAMP have offset voltage null capability. Pins 1 and 5 are marked offset
null for this purpose. It can be done by connecting 10 K ohm pot between 1 and
5 as shown in fig. 3.

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Fig. 3

By varying the potentiometer, output offset voltage (with inputs grounded) can
be reduced to zero volts. Thus, the offset voltage adjustment range is the range
through which the input offset voltage can be adjusted by varying 10 K pot. For
the 741C the offset voltage adjustment range is ± 15 mV.

Parameters of OPAMP:

7. Input Voltage Range :

Input voltage range is the range of a common mode input signal for which a
differential amplifier remains linear. It is used to determine the degree of
matching between the inverting and noninverting input terminals. For the 741C,
the range of the input common mode voltage is ± 13V maximum. This means that
the common mode voltage applied at both input terminals can be as high as +13V
or as low as –13V.

8. Common Mode Rejection Ratio (CMRR).

CMRR is defined as the ratio of the differential voltage gain Ad to the common
mode voltage gain ACM

CMRR = Ad / ACM.

For the 741C, CMRR is 90 dB typically. The higher the value of CMRR the better
is the matching between two input terminals and the smaller is the output common
mode voltage.

9. Supply voltage Rejection Ratio: (SVRR)

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SVRR is the ratio of the change in the input offset voltage to the corresponding
change in power supply voltages. This is expressed in m V / V or in decibels,
SVRR can be defined as

SVRR = D Vio / D V

Where D V is the change in the input supply voltage and D Vio is the
corresponding change in the offset voltage.

For the 741C, SVRR = 150 µ V / V.

For 741C, SVRR is measured for both supply magnitudes increasing or

decreasing simultaneously, with R3 £ 10K. For same OPAMPS, SVRR is
separately specified as positive SVRR and negative SVRR.

10. Large Signal Voltage Gain:

Since the OPAMP amplifies difference voltage between two input terminals, the
voltage gain of the amplifier is defined as

Because output signal amplitude is much large than the input signal the voltage
gain is commonly called large signal voltage gain. For 741C is voltage gain is
200,000 typically.

11. Output voltage Swing:

The ac output compliance PP is the maximum unclipped peak to peak output

voltage that an OPAMP can produce. Since the quiescent output is ideally zero,
the ac output voltage can swing positive or negative. This also indicates the values
of positive and negative saturation voltages of the OPAMP. The output voltage
never exceeds these limits for a given supply voltages +VCC and –VEE. For a 741C
it is ± 13 V.

12. Output Resistance: (RO)

RO is the equivalent resistance that can be measured between the output terminal
of the OPAMP and the ground. It is 75 ohm for the 741C OPAMP.

Example - 1

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Determine the output voltage in each of the following cases for the open loop differential
amplifier of fig. 4:

a. vin 1 = 5 m V dc, vin 2 = -7 µVdc

b. vin 1 = 10 mV rms, vin 2= 20 mV rms

Fig. 4

Specifications of the OPAMP are given below:

A = 200,000, Ri = 2 M Ω , R O = 75Ω, + VCC = + 15 V, - VEE = - 15 V, and output voltage
swing = ± 14V.

Solution:

(a). The output voltage of an OPAMP is given by

Remember that vo = 2.4 V dc with the assumption that the dc output voltage is zero when the
input signals are zero.

(b). The output voltage equation is valid for both ac and dc input signals. The output voltage
is given by

Thus the theoretical value of output voltage vo = -2000 V rms. However, the OPAMP
saturates at ± 14 V. Therefore, the actual output waveform will be clipped as shown fig. 5.
This non-sinusoidal waveform is unacceptable in amplifier applications.

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Fig. 5

13. Output Short circuit Current :

In some applications, an OPAMP may drive a load resistance that is approximately zero.
Even its output impedance is 75 ohm but cannot supply large currents. Since OPAMP is low
power device and so its output current is limited. The 741C can supply a maximum short
circuit output current of only 25mA.

14. Supply Current :

IS is the current drawn by the OPAMP from the supply. For the 741C OPAMP the supply
current is 2.8 m A.

15. Power Consumption:

Power consumption (PC) is the amount of quiescent power (vin= 0V) that must be consumed
by the OPAMP in order to operate properly. The amount of power consumed by the 741C is
85 m W.

16. Gain Bandwidth Product:

The gain bandwidth product is the bandwidth of the OPAMP when the open loop voltage
gain is reduced to 1. From open loop gain vs frequency graph At 1 MHz shown in. fig. 6, It
can be found 1 MHz for the 741C OPAMP frequency the gain reduces to 1. The mid band
voltage gain is 100, 000 and cut off frequency is 10Hz.

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Fig. 6

17. Slew Rate:

Slew rate is defined as the maximum rate of change of output voltage per unit of time under
large signal conditions and is expressed in volts / m secs.

To understand this, consider a charging current of a capacitor shown in fig. 7.

Fig. 6

If 'i' is more, capacitor charges quickly. If 'i' is limited to Imax, then rate of change is also
limited.

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Slew rate indicates how rapidly the output of an OPAMP can change in response to changes
in the input frequency with input amplitude constant. The slew rate changes with change in
voltage gain and is normally specified at unity gain.

If the slope requirement is greater than the slew rate, then distortion occurs. For the 741C the
slew rate is low 0.5 V / m S. which limits its use in higher frequency applications.

18. Input Offset Voltage and Current Drift:

It is also called average temperature coefficient of input offset voltage or input offset current.
The input offset voltage drift is the ratio of the change in input offset voltage to change in
temperature and expressed in m V /° C. Input offset voltage drift = ( D Vio / D T).

Similarly, input offset current drift is the ratio of the change in input offset current to the
change in temperature. Input offset current drift = ( D Iio / D T).

For 741C,

D Vio / D T = 0.5 m V / C.
D Iio/ D T = 12 pA / C.

Example - 1

A 100 PF capacitor has a maximum charging current of 150 µA. What is the slew rate?

Solution:

C = 100 PF=100 x 10-12 F

I = 150 µA = 150 x 10-6 A

Slew rate is 1.5 V / µs.

Example - 2

An operational amplifier has a slew rate of 2 V / µs. If the peak output is 12 V, what is the
power bandwidth?

Solution:

The slew rate of an operational amplifier is

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As for output free of distribution, the slews determines the maximum frequency of operation
fmax for a desired output swing.

so
So bandwidth = 26.5 kHz.

Example - 3

For the given circuit in fig. 1. Iin(off) = 20 nA. If Vin(off) = 0, what is the differential input
voltage?. If A = 105, what does the output offset voltage equal?

Fig. 1

Solutin:

Iin(off) = 20 nA
Vin(off) = 0

(i) The differential input voltage = Iin(off) x 1k = 20 nA x 1 k = 20µ V

(ii) If A = 105 then the output offset voltage Vin(off) = 20 µ V x 105 = 2 volt

Output offset voltage = 2 volts.

Example - 4

R1 = 100Ω, Rf = 8.2 k, RC = 10 k. Assume that the amplifier is nulled at 25°C. If Vin is 20

mV peak sine wave at 100 Hz. Calculate Er, and Vo values at 45°C for the circuit shown in
fig. 2.

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Fig. 2

Solution:

The change in temperature ΔT = 45 - 25 = 20°C.

Error voltage = 51.44 mV

Output voltage is 1640 mV peak ac signal which rides either on a +51.44 mV or -51.44 mV
dc level.

Example - 5

Design an input offset voltage compensating network for the operational amplifier µA 715
for the circuit shown in fig. 3. Draw the complete circuit diagram.

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Fig. 3

Solution:

From data sheet we get vin = 5 mV for the operational amplifier µA 715.

V = | VCC | = | - VEE | = 15 V

Now,

If we select RC = 10Ω, the value of Rb should be

Rb = (3000) RC = 30000Ω = 304Ω

Since R > Rmax, let RS = 10 Rmax where Rmax = Ra / 4. Therefore,

If a 124Ω potentiometer is not available, we may prefer to use to the next lower value
avilable, such as 104Ω, so that the value of Ra will be larger than Rb by a factor of 10. If we
select a 10 kΩ potentiometer a s the Ra value, Rb is 12 times larger than Ra, Thus

Ra = 10 kΩ potentiometer
Rb = 30 kΩ
Rc = 10Ω.

The final circuit, which also includes the pin connections for the µA 715, shown in fig. 4.

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Fig. 4

The ideal OPAMP :

An ideal OPAMP would exhibit the following electrical characteristic.

1. Infinite voltage gain Ad

2. Infinite input resistance Ri, so that almost any signal source can drive it and there is
no loading of the input source.
3. Zero output resistance RO, so that output can drive an infinite number of other
devices.
4. Zero output voltage when input voltage is zero.
5. Infinite bandwidth so that any frequency signal from 0 to infinite Hz can be amplified
without attenuation.
6. Infinite common mode rejection ratio so that the output common mode noise voltage
is zero.
7. Infinite slew rate, so that output voltage changes occur simultaneously with input
voltage changes.

There are practical OPAMPs that can be made to approximate some of these characters using
a negative feedback arrangement.

Equivalent Circuit of an OPAMP:

Fig. 5, shows an equivalent circuit of an OPAMP. v1 and v2are the two input voltage
voltages. Ri is the input impedance of OPAMP. Ad Vd is an equivalent Thevenin voltage
source and RO is the Thevenin equivalent impedance looking back into the terminal of an
OPAMP.

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Fig. 5

This equivalent circuit is useful in analyzing the basic operating principles of OPAMP and in
observing the effects of standard feedback arrangements

vO = Ad (v1 – v2) = Ad vd.

This equation indicates that the output voltage vO is directly proportional to the algebraic
difference between the two input voltages. In other words the OPAMP amplifies the
difference between the two input voltages. It does not amplify the input voltages themselves.
The polarity of the output voltage depends on the polarity of the difference voltage vd.

Ideal Voltage Transfer Curve:

The graphic representation of the output equation is shown in fig. 6 in which the output
voltage vO is plotted against differential input voltage vd, keeping gain Ad constant.

Fig. 6

The output voltage cannot exceed the positive and negative saturation voltages. These
saturation voltages are specified for given values of supply voltages. This means that the

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output voltage is directly proportional to the input difference voltage only until it reaches the
saturation voltages and thereafter the output voltage remains constant.

Thus curve is called an ideal voltage transfer curve, ideal because output offset voltage is
assumed to be zero. If the curve is drawn to scale, the curve would be almost vertical because
of very large values of Ad.

Open loop OPAMP Configuration:

In the case of amplifiers the term open loop indicates that no connection, exists between input
and output terminals of any type. That is, the output signal is not fedback in any form as part
of the input signal.

In open loop configuration, The OPAMP functions as a high gain amplifier. There are three open loop
OPAMP configurations.

The Differential Amplifier:

Fig. 1, shows the open loop differential amplifier in which input signals vin1 and vin2 are
applied to the positive and negative input terminals.

Fig. 1

Since the OPAMP amplifies the difference the between the two input signals, this configuration is
called the differential amplifier. The OPAMP amplifies both ac and dc input signals. The source
resistance Rin1 and Rin2 are normally negligible compared to the input resistance Ri. Therefore voltage
drop across these resistances can be assumed to be zero.

Therefore

v1 = vin1 and v2 = vin2.

vo = Ad (vin1 – vin2 )

where, Ad is the open loop gain.

The Inverting Amplifier:

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If the input is applied to only inverting terminal and non-inverting terminal is grounded then it is
called inverting amplifier.This configuration is shown in fig. 2.

v1= 0, v2 = vin.

vo = -Ad vin

Fig. 2

The negative sign indicates that the output voltage is out of phase with respect to input 180 ° or is of
opposite polarity. Thus the input signal is amplified and inverted also.

The non-inverting amplifier:

In this configuration, the input voltage is applied to non-inverting terminals and inverting terminal is
ground as shown in fig. 3.

v1 = +vin v2 = 0

vo = +Ad vin

This means that the input voltage is amplified by Ad and there is no phase reversal at the output.

Fig. 3

In all there configurations any input signal slightly greater than zero drive the output to saturation
level. This is because of very high gain. Thus when operated in open-loop, the output of the OPAMP

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is either negative or positive saturation or switches between positive and negative saturation levels.
Therefore open loop op-amp is not used in linear applications.

Analog Inverter and Scale Changer:

The circuit of analog inverter is shown in fig. 1. It is same as inverting voltage amplifier.

Assuming OPAMP to be an ideal one,

the differential input voltage is zero.

i.e. vd = 0
Therefore, v1 = v2 = 0

Since input impedance is very high,

therefore, input current is zero. OPAMP
do not sink any current.

\ iin= if
vin / R = - vO / Rf
vo = - (Rf / R) vin

If R = Rf then vO = -vin, the circuit

behaves like an inverter. Fig. 1

If Rf / R = K (a constant) then the circuit

is called inverting amplifier or scale
changer voltages.

Inverting summer:

The configuration is shown in fig. 2. With three input voltages va, vb & vc. Depending upon
the value of Rf and the input resistors Ra, Rb, Rc the circuit can be used as a summing
amplifier, scaling amplifier, or averaging amplifier.

Again, for an ideal OPAMP, v1 =

v2. The current drawn by
OPAMP is zero. Thus, applying
KCL at v2 node

Fig. 2

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This means that the output

voltage is equal to the negative
sum of all the inputs times the
gain of the circuit Rf/ R; hence
the circuit is called a summing
amplifier. When Rf= R then the
output voltage is equal to the
negative sum of all inputs.

vo= -(va+ vb+ vc)

If each input voltage is amplified by a different factor in other words weighted differently at
the output, the circuit is called then scaling amplifier.

The circuit can be used as an averaging circuit, in which the output voltage is equal to the
average of all the input voltages.

In this case, Ra= Rb= Rc = R and Rf / R = 1 / n where n is the number of inputs. Here Rf / R =
1 / 3.

vo = -(va+ vb + vc) / 3

In all these applications input could be either ac or dc.

Noninverting configuration:

If the input voltages are connected to noninverting input through resistors, then the circuit can
be used as a summing or averaging amplifier through proper selection of R1, R2, R3 and Rf. as
shown in fig. 3.

To find the output voltage expression, v1

is required. Applying superposition
theorem, the voltage v1 at the noninverting
terminal is given by

Hence the output voltage is

Fig. 3

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This shows that the output is equal to the average of all input voltages times the gain of the
circuit (1+ Rf / R1), hence the name averaging amplifier.

If (1+Rf/ R1) is made equal to 3 then the output voltage becomes sum of all three input
voltages.

vo = v a + vb+ vc

Hence, the circuit is called summing amplifier.

Example - 1

Find the gain of VO / Vi of the circuit of fig. 4.

Solution:

Current entering at the inveting

terminal .

Applying KCL to node 1,

Applying KCL to node 2,

Thus the gain A = -8 V / VO

Integrator:

A circuit in which the output voltage waveform is the integral of the input voltage waveform
is called integrator. Fig. 4, shows an integrator circuit using OPAMP.

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Fig. 4

Here, the feedback element is a capacitor. The current drawn by OPAMP is zero and also the
V2 is virtually grounded.

Therefore, i1 = if and v2 = v1 = 0

Integrating both sides with respect to time from 0 to t, we get

The output voltage is directly proportional to the negative integral of the input voltage and
inversely proportional to the time constant RC.

If the input is a sine wave the output will be cosine wave. If the input is a square wave, the
output will be a triangular wave. For accurate integration, the time period of the input signal
T must be longer than or equal to RC.

Fig. 5, shows the output of integrator for square and sinusoidal inputs.

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Fig. 5

Example - 3

Prove that the network shown in fig. 6 is a non-inverting integrator with .

Solution:

The voltage at point A is vO / 2 and it is also the

voltage at point B because different input voltage
is negligible.

vB = VO / 2

Therefore, applying Node current equation at

point B,

Fig. 6

Differentator:

A circuit in which the output voltage waveform is the differentiation of input voltage is called
differentiator.as shown in fig. 1.

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Fig. 1

The expression for the output voltage can be obtained from the Kirchoff's current equation
written at node v2.

Thus the output vo is equal to the RC

times the negative instantaneous rate
of change of the input voltage vin with
time. A cosine wave input produces
sine output. fig. 1 also shows the
output waveform for different input
voltages.

The input signal will be differentiated

properly if the time period T of the
input signal is larger than or equal to
Rf C.

T ³ Rf C

As the frequency changes, the gain

changes. Also at higher frequencies the
circuit is highly susceptible at high
frequency noise and noise gets Fig. 2
amplified. Both the high frequency noise
and problem can be corrected by
additing, few components. as shown in
fig. 2.

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Voltage to current converter:

Fig. 3, shows a voltage to current converter in which load resistor RL is floating (not
connected to ground).

The input voltage is applied to the non-inverting input terminal and the feedback voltage
across R drives the inverting input terminal. This circuit is also called a current series
negative feedback, amplifier because the feedback voltage across R depends on the output
current iL and is in series with the input difference voltage vd.

Writing the voltage equation for the

input loop.

vin = vd + vf

But vd » since A is very

large,therefore,

vin = vf
vin = R iin
iin = v in / R.

and since input current is zero.

iL = iin = vin ./ R

The value of load resistance does not

appear in this equation. Therefore, the
output current is independent of the
value of load resistance. Thus the input Fig. 3
voltage is converted into current, the
source must be capable of supplying
this load current.

Current to voltage converter:

The circuit shown in fig. 1, is a current to voltage converter.

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Fig. 1

Due to virtual ground the current through R is zero and the input current flows through Rf.
Therefore,

vout =-Rf * iin

The lower limit on current measure with this circuit is set by the bias current of the inverting
input.

BIPOLAR JUNCTION TRANSISTOR (BJT)

A bipolar junction transistor (BJT) is a three-terminal device in which operation depends on
the interaction of both majority and minority carriers and hence the name bipolar. The BJT is
analogous to vacuum triode and is comparatively smaller in size. It is used in amplifier and
oscillator circuits, and as a switch in digital circuits. It has wide applications in computers,
satellites and other modern communication systems.

CONSTRUCTION OF BJT AND ITS SYMBOLS

The Bipolar Transistor basic construction consists of two PN-junctions producing three
connecting terminals with each terminal being given a name to identify it from the other two.
These three terminals are known and labelled as the Emitter ( E ), the Base ( B ) and the
Collector ( C ) respectively. There are two basic types of bipolar transistor construction, PNP
and NPN, which basically describes the physical arrangement of the P-type and N-type
semiconductor materials from which they are made. Transistors are three terminal active
devices made from different semiconductor materials that can act as either an insulator or a
conductor by the application of a small signal voltage. The transistor's ability to change
between these two states enables it to have two basic functions: "switching" (digital electronics)
or "amplification" (analogue electronics).

The principle of operation of the two transistor types PNP and

NPN, is exactly the same the only difference being in their biasing and the polarity of the power
supply for each type (fig 1). The construction and circuit symbols for both the PNP and NPN
bipolar transistor are given below with the arrow in the circuit symbol always showing the
direction of "conventional current flow" between the base terminal and its emitter terminal.
The direction of the arrow always points from the positive P-type region to the negative Ntype
region for both transistor types, exactly the same as for the standard diode symbol

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Transistor Operation:

Working of a n-p-n transistor:

The n-p-n transistor with base to emitter junction forward biased and collector base
junction reverse biased is as shown in figure.

As the base to emitter junction is forward biased the majority carriers emitted by the n-type
emitter i.e., electrons have a tendency to flow towards the base which constitutes the emitter current IE.

As the base is p-type there is chance of recombination of electrons emitted by the emitter with
the holes in the p-type base. But as the base is very thin and lightly doped only few electrons emitted
by the n-type emitter less than 5% combines with the holes in the p-type base, the remaining more

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than 95% electrons emitted by the n-type emitter cross over into the collector region constitute
the collector current.

IE = IB + IC
Working of a p-n-p transistor:

The p-n-p transistor with base to emitter junction is forward biased and collector to base junction
reverse biased is as show in figure. As the base to emitter junction is forward biased the majority
carriers emitted by the p-type emitter i.e., holes have a tendency to flow towards the base which
constitutes the emitter current IE.

As the base is n-type there is a chance of recombination of holes emitted by the emitter with the
electrons in the n-type base. But as the base us very thin and lightly doped only few electrons less
than 5% combine with the holes emitted by the p-type emitter, the remaining 95% charge carriers
cross over into the collector region to constitute the collector current.

IE = IB + IC

TRANSISTOR CURRENT COMPONENTS:

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The above fig shows the various current components, which flow across the forward biased
emitter junction and reverse- biased collector junction. The emitter current IE consists of hole
current IPE (holes crossing from emitter into base) and electron current InE(electrons crossing
from base into emitter).The ratio of hole to electron currents, IpE/ InE , crossing the emitter
junction is proportional to the ratio of the conductivity of the p material to that of the n
material. In a transistor, the doping of that of the emitter is made much larger than the doping
of the base. This feature ensures (in p-n-p transistor) that the emitter current consists an
almost entirely of holes. Such a situation is desired since the current which results from
electrons crossing the emitter junction from base to emitter does not contribute carriers,
which can reach the collector.
Not all the holes crossing the emitter junction JE reach the the collector junction JC
Because some of them combine with the electrons in n-type base. If IpC is hole current at junction JC
there must be a bulk recombination current (IPE- IpC ) leaving the base.
Actually, electrons enter the base region through the base lead to supply those charges, which have
been lost by recombination with the holes injected in to the base across J E.If the emitter were open
circuited so that IE=0 then IpC would be zero. Under these circumstances, the base and collector
current IC would equal the reverse saturation current ICO. If IE≠0 then
IC= ICO- IpC
For a p-n-p transistor, ICO consists of holes moving across JCfrom left to right (base to collector) and
electrons crossing JC in opposite direction. Assumed referenced direction for ICO i.e. from right to left,
then for a p-n-p transistor, ICOis negative. For an n-p-n transistor, ICO is positive. The basic operation
will be described using the pnp transistor. The operation of the pnp transistor is exactly the same if the
roles played by the electron and hole are interchanged.
One p-n junction of a transistor is reverse-biased, whereas the other is forward-biased.

Forward-biased junction of a pnp transistor

Reverse-biased junction of a pnp transistor

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Both biasing potentials have been applied to a pnp transistor and resulting majority and minority
carrier flows indicated.
Majority carriers (+) will diffuse across the forward-biased p-n junction into the n-type material. A
very small number of carriers (+) will through n-type material to the base terminal. Resulting IB is
typically in order of microamperes.
The large number of majority carriers will diffuse across the reverse-biased junction into the ptype
material connected to the collector terminal

Applying KCL to the transistor :

I E = IC + IB
The comprises of two components – the majority and minority carriers
IC = ICmajority + ICOminority
ICO – IC current with emitter terminal open and is called leakage current
Various parameters which relate the current components is given below
Emitter efficiency:

Transport Factor:

Large signal current gain:

The ratio of the negative of collector current increment to the emitter current change from zero
(cutoff)to IE the large signal current gain of a common base transistor.

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Since ICand IE have opposite signs, then α, as defined, is always positive. Typically numerical
values of α lies in the range of 0.90 to 0.995

The transistor alpha is the product of the transport factor and the emitter efficiency. This statement
assumes that the collector multiplication ratio * is unity. * is the ratio of total current crossing JC to
hole arriving at the junction.

Bipolar Transistor Configurations

As the Bipolar Transistor is a three terminal device, there are basically three possible ways
to connect it within an electronic circuit with one terminal being common to both the input
and output. Each method of connection responding differently to its input signal within a
circuit as the static characteristics of the transistor vary with each circuit arrangement.
• 1. Common Base Configuration - has Voltage Gain but no Current Gain.
• 2 Common Emitter Configuration - has both Current and Voltage Gain.
• 3. Common Collector Configuration - has Current Gain but no Voltage Gain.

COMMON-BASE CONFIGURATION
Common-base terminology is derived from the fact that the: base is common to both input
and output of the configuration. base is usually the terminal closest to or at ground potential.
Majority carriers can cross the reverse-biased junction because the injected majority carriers
will appear as minority carriers in the n-type material. All current directions will refer to
conventional (hole) flow and the arrows in all electronic symbols have a direction defined by
this convention.

Note that the applied biasing (voltage sources) are such as to establish current in the direction
indicated for each branch.

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To describe the behaviour of common-base amplifiers requires two set of characteristics:

1. Input or driving point characteristics.
2. Output or collector characteristics
The output characteristics has 3 basic regions:
• Active region –defined by the biasing arrangements
• Cutoff region – region where the collector current is 0A
• Saturation region- region of the characteristics to the left of VCB =0V

The curves (output characteristics) clearly indicate that a first approximation to the relationship
between IE and IC in the active region is given by
IC ≈IE
Once a transistor is in the ‘on’ state, the base-emitter voltage will be assumed to be VBE = 0.7V

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In the dc mode the level of IC and IE due to the majority carriers are related by a quantity called alpha
= αdc
IC = IE + ICBO
It can then be summarize to IC = IE (ignore ICBO due to small value)
For ac situations where the point of operation moves on the characteristics curve, an ac alpha defined
by αac
Alpha a common base current gain factor that shows the efficiency by calculating the current percent
from current flow from emitter to collector. The value of  is typical from 0.9 ~ 0.998.

COMMON-EMITTER CONFIGURATION
It is called common-emitter configuration since: emitter is common or reference to both input
and output terminals. emitter is usually the terminal closest to or at ground potential. Almost amplifier
design is using connection of CE due to the high gain for current and voltage. Two set of characteristics
are necessary to describe the behaviour for CE; input (base terminal) and output (collector terminal)
parameters.
Proper Biasing common-emitter configuration in active region

IB is microamperes compared to milliamperes of IC.

IB will flow when VBE> 0.7V for silicon and 0.3V for germanium
Before this value IB is very small and no IB.
Base-emitter junction is forward bias Increasing VCE will reduce IB for different values.

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Output characteristics for a common-emitter npn transistor

For small VCE (VCE< VCESAT, IC increase linearly with increasing of VCE
VCE> VCESAT IC not totally depends on VCE→ constant IC
IB(uA) is very small compare to IC (mA). Small increase in IB cause big increase in IC
IB=0 A → ICEO occur.
Noticing the value when IC=0A. There is still some value of current flows.

Beta () or amplification factor

The ratio of dc collector current (IC) to the dc base current (IB) is dc beta (dc) which is dc
current gain where IC and IB are determined at a particular operating point, Q-point (quiescent
point). It’s defined by the following equation:
30 <dc < 300 → 2N3904
On data sheet, dc=hfe with h is derived from ac hybrid equivalent cct. FE are derived from
forward-current amplification and common-emitter configuration respectively

COMMON COLLECTOR CONFIGURATION

Also called emitter-follower (EF). It is called common-emitter configuration since both the signal
source and the load share the collector terminal as a common connection point. The output voltage is
obtained at emitter terminal. The input characteristic of common-collector configuration is similar with
common-emitter. configuration. Common-collector circuit configuration is provided with the load
resistor connected from emitter to ground. It is used primarily for impedance-matching purpose since it
has high input impedance and low output impedance.

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For the common-collector configuration, the output characteristics are a plot of IE vs VCE for a
range of values of IB

THE TRANSISTOR AS AN AMPLIFIER

Consider the circuit fragment shown at right, which includes an NPN transistor connected
between two power supply “rails” VCC and VEE (with, naturally, VCC >VEE ). Assume that
some method has been used to bias the transistor’s base terminal at the voltage VB >VEE
so that the transistor’s base-emitter junction is forward-biased and conducting current IB as
shown (we’ll discuss ways of biasing the transistor in a subsequent section). What we want to
determine are the relationships between the various voltages and currents, the resistor values
RC and RE , and the transistor’s β We start the analysis by connecting the base and emitter
voltages using the forward bias diode drop.
VBE ≈ 0.6V across the base-emitter PN junction. As we know from our previous studyof
the semiconductor diode, this voltage will be a very weak function of the base current IB ,
sowewillusetheworkingassumptionthatitisafixed,constantvalue.Consequently,if we know VB ,
then we also know VE , and vice versa. Given VE , we now know the
voltage drop across the resistor RE , so we also know the current through it: I E = (VE -
VEE)RE.
Knowing IE and the transistor’s current gain β immediately tells us the other two
transistor currents IB and IC , since the currents are related through β as shown in below

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Figure The value of RC then gives us the collector voltage VC ,since I C = (VCC -VC) RC
.Thus we have succeeded in relating the circuit’s state variables (currents and voltages),as
we set out to do. Note that there are some conditions that must be met for our solution to be
realistic: all the currents must flow in the directions shown by the arrows in Figure, and it
must be the case that VEE <VE <VB ≤ VC <VCC. If one or more of these conditions is violated
by our solution, then our solution fails, and the transistor circuit is operating as a switch
rather than as an amplifier.

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FEEDBACK AMPLIFIERS

An amplifier circuit simply increases the signal strength. But while amplifying, it just increases
the strength of its input signal whether it contains information or some noise along with
information. This noise or some disturbance is introduced in the amplifiers because of their
strong tendency to introduce hum due to sudden temperature changes or stray electric and
magnetic fields. Therefore, every high gain amplifier tends to give noise along with signal in
its output, which is very undesirable.

The noise level in the amplifier circuits can be considerably reduced by using negative
feedback done by injecting a fraction of output in phase opposition to the input signal.

Principle of Feedback Amplifier

A feedback amplifier generally consists of two parts. They are the amplifier and the feedback
circuit. The feedback circuit usually consists of resistors. The concept of feedback amplifier
can be understood from the following figure.

From the above figure, the gain of the amplifier is represented as A. the gain of the amplifier
is the ratio of output voltage Vo to the input voltage Vi. the feedback network extracts a voltage
Vf = β Vo from the output Vo of the amplifier.

This voltage is added for positive feedback and subtracted for negative feedback, from the
signal voltage Vs. Now,

Vi=Vs+Vf=Vs+βVo
Vi=Vs−Vf=Vs−βVo
The quantity β = Vf/Vo is called as feedback ratio or feedback fraction.

Let us consider the case of negative feedback. The output Vo must be equal to the input
voltage (Vs - βVo) multiplied by the gain A of the amplifier.

Hence,

(Vs−βVo)A=Vo
Or

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AVs−AβVo=Vo
Or

AVs=Vo(1+Aβ)
Therefore,

Vo/Vs=A/1+Aβ
Let Af be the overall gain (gain with the feedback) of the amplifier. This is defined as the
ratio of output voltage Vo to the applied signal voltage Vs, i.e.,

Af=Output voltage/Input signal voltage=Vo/Vs

So, from the above two equations, we can understand that,

The equation of gain of the feedback amplifier, with negative feedback is given by

Af=A/1+Aβ
The equation of gain of the feedback amplifier, with positive feedback is given by

Af=A/1−Aβ
These are the standard equations to calculate the gain of feedback amplifiers.

Types of Feedbacks
The process of injecting a fraction of output energy of some device back to the input is known
as Feedback. It has been found that feedback is very useful in reducing noise and making the
amplifier operation stable.

Depending upon whether the feedback signal aids or opposes the input signal, there are two
types of feedbacks used.

Positive Feedback

The feedback in which the feedback energy i.e., either voltage or current is in phase with the
input signal and thus aids it is called as Positive feedback.

Both the input signal and feedback signal introduces a phase shift of 180o thus making a 360o
resultant phase shift around the loop, to be finally in phase with the input signal.

Though the positive feedback increases the gain of the amplifier, it has the disadvantages such
as

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• Increasing distortion
• Instability

It is because of these disadvantages the positive feedback is not recommended for the
amplifiers. If the positive feedback is sufficiently large, it leads to oscillations, by which
oscillator circuits are formed.

Negative Feedback

The feedback in which the feedback energy i.e., either voltage or current is out of phase with
the input and thus opposes it, is called as negative feedback.

In negative feedback, the amplifier introduces a phase shift of 180o into the circuit while the
feedback network is so designed that it produces no phase shift or zero phase shift. Thus, the
resultant feedback voltage Vf is 180o out of phase with the input signal Vin.

Though the gain of negative feedback amplifier is reduced, there are many advantages of
negative feedback such as

• Stability of gain is improved

• Reduction in distortion
• Reduction in noise
• Increase in input impedance
• Decrease in output impedance
• Increase in the range of uniform application

It is because of these advantages negative feedback is frequently employed in amplifiers.

Negative feedback in an amplifier is the method of feeding a portion of the amplified output
to the input but in opposite phase. The phase opposition occurs as the amplifier provides 180o
phase shift whereas the feedback network doesn’t.

While the output energy is being applied to the input, for the voltage energy to be taken as
feedback, the output is taken in shunt connection and for the current energy to be taken as
feedback, the output is taken in series connection.

There are two main types of negative feedback circuits. They are −

• Negative Voltage Feedback

• Negative Current Feedback

Negative Voltage Feedback

In this method, the voltage feedback to the input of amplifier is proportional to the output
voltage. This is further classified into two types −

• Voltage-series feedback
• Voltage-shunt feedback

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Negative Current Feedback

In this method, the voltage feedback to the input of amplifier is proportional to the output
current. This is further classified into two types.

• Current-series feedback
• Current-shunt feedback

Let us have a brief idea on all of them.

Voltage-Series Feedback

In the voltage series feedback circuit, a fraction of the output voltage is applied in series with
the input voltage through the feedback circuit. This is also known as shunt-driven series-fed
feedback, i.e., a parallel-series circuit.

The following figure shows the block diagram of voltage series feedback, by which it is evident
that the feedback circuit is placed in shunt with the output but in series with the input.

As the feedback circuit is connected in shunt with the output, the output impedance is decreased
and due to the series connection with the input, the input impedance is increased.

Voltage-Shunt Feedback

In the voltage shunt feedback circuit, a fraction of the output voltage is applied in parallel with
the input voltage through the feedback network. This is also known as shunt-driven shunt-fed
feedback i.e., a parallel-parallel proto type.

The below figure shows the block diagram of voltage shunt feedback, by which it is evident
that the feedback circuit is placed in shunt with the output and also with the input.

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As the feedback circuit is connected in shunt with the output and the input as well, both the
output impedance and the input impedance are decreased.

Current-Series Feedback

In the current series feedback circuit, a fraction of the output voltage is applied in series with
the input voltage through the feedback circuit. This is also known as series-driven series-fed
feedback i.e., a series-series circuit.

The following figure shows the block diagram of current series feedback, by which it is
evident that the feedback circuit is placed in series with the output and also with the input.

As the feedback circuit is connected in series with the output and the input as well, both the
output impedance and the input impedance are increased.

Current-Shunt Feedback

In the current shunt feedback circuit, a fraction of the output voltage is applied in series with
the input voltage through the feedback circuit. This is also known as series-driven shunt-fed
feedback i.e., a series-parallel circuit.

The below figure shows the block diagram of current shunt feedback, by which it is evident
that the feedback circuit is placed in series with the output but in parallel with the input.

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As the feedback circuit is connected in series with the output, the output impedance is increased
and due to the parallel connection with the input, the input impedance is decreased.

Let us now tabulate the amplifier characteristics that get affected by different types of negative
feedbacks.

THE OSCILLATOR

- Oscillators are electronic circuits that generate an output signal without the necessity of an
input signal.
- It produces a periodic waveform on its output with only the DC supply voltage as an input.
- The output voltage can be either sinusoidal or non sinusoidal, depending on the type of
oscillator.
- Different types of oscillators produce various types of outputs including sine waves, square
waves, triangular waves, and sawtooth waves.
- A basic oscillator is shown in Figure 1.
- Oscillators can be of 2 types.

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Feedback Oscillators

- One type of oscillator is the feedback oscillator, which returns a fraction of the output signal
to the input with no net phase shift, resulting in a reinforcement of the output signal.
- After oscillations are started, the loop gain is maintained at 1.0 to maintain oscillations.
- A feedback oscillator consists of an amplifier for gain (either a discrete transistor or an op-
amp) and a positive feedback circuit that produces phase shift and provides attenuation, as
shown in Figure 2.

Relaxation Oscillators
- A second type of oscillator is the relaxation oscillator.
- Instead of feedback, a relaxation oscillator uses an RC timing circuit to generate a waveform
that is generally a square wave or other non sinusoidal waveform.
- Typically, a relaxation oscillator uses a Schmitt trigger or other device that changes states to
alternately charge and discharge a capacitor through a resistor.

FEEDBACK OSCILLATORS
- Feedback oscillator operation is based on the principle of positive feedback.
- In this section, we will look at the general conditions required for oscillation to occur.

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- Feedback oscillators are widely used to generate sinusoidal waveforms.

Positive Feedback

- In positive feedback, a portion of the output voltage of an amplifier is fed back to the input
with no net phase shift, resulting in a strengthening of the output signal.
- This basic idea is illustrated in Figure 3(a).

- As you can see, the in-phase feedback voltage is amplified to produce the output voltage,
which in turn produces the feedback voltage.
- That is, a loop is created in which the signal maintains itself and a continuous sinusoidal
output is produced.
- This phenomenon is called oscillation.
- In some types of amplifiers, the feedback circuit shifts the phase and an inverting amplifier is
required to provide another phase shift so that there is no net phase shift.
- This is illustrated in Figure 3(b).

Conditions for Oscillation

- Two conditions, illustrated in Figure 4, are required for a sustained state of oscillation:
1. The phase shift around the feedback loop must be effectively.
2. The voltage gain, around the closed feedback loop (loop gain) must equal 1 (unity).

- The voltage gain around the closed feedback loop, , is the product of the amplifier gain, ,
and the attenuation, of the feedback circuit.

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- If a sinusoidal wave is the desired output, a loop gain greater than 1 will rapidly cause the
output to saturate at both peaks of the waveform, producing unacceptable distortion.
- To avoid this, some form of gain control must be used to keep the loop gain at exactly 1 once
oscillations have started.
- For example, if the attenuation of the feedback circuit is 0.01, the amplifier must have a gain
of exactly 100 to overcome this attenuation and not create unacceptable distortion .
- An amplifier gain of greater than 100 will cause the oscillator to limit both peaks of the
waveform.

Start-Up Conditions

- So far, you have seen what it takes for an oscillator to produce a continuous sinusoidal output.
- Now let’s examine the requirements for the oscillation to start when the dc supply voltage is
first turned on.
- As you know, the unity-gain condition must be met for oscillation to be maintained.
- For oscillation to begin, the voltage gain around the positive feedback loop must be greater
than 1 so that the amplitude of the output can build up to a desired level.
- The gain must then decrease to 1 so that the output stays at the desired level and oscillation
is sustained.
- The voltage gain conditions for both starting and sustaining oscillation are illustrated in Figure
5.

OSCILLATION WITH RC FEEDBACK CIRCUITS

- Three types of feedback oscillators that use RC circuits to produce sinusoidal outputs are the
• Wien-bridge oscillator
• Phase-shift oscillator
• Twin-T oscillator
- Generally, RC feedback oscillators are used for frequencies up to about 1 MHz.
- The Wien-bridge is by far the most widely used type of RC feedback oscillator for this range
of frequencies.

Wien-Bridge Oscillator

- One type of sinusoidal feedback oscillator is the Wien-bridge oscillator.

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- A fundamental part of the Wien-bridge oscillator is a lead-lag circuit like that shown in
Figure 6(a).
- R1 and C1 together form the lag portion of the circuit; R2 and C2 form the lead portion.
- The operation of this lead-lag circuit is as follows.
• At lower frequencies, the lead circuit takes over due to the high reactance of C2.
• As the frequency increases, XC2 decreases, thus allowing the output voltage to increase.
• At some specified frequency, the response of the lag circuit takes over, and the
decreasing value of XC1causes the output voltage to decrease.

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THE 555 TIMER AS OSCILLATOR

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ASTABLE OPERATION

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DIGITAL ELECTRONICS FUNDAMENTALS

Difference Between Analog And Digital Signal

Analog Signals Digital Signals
Continuous signals Discrete signals
Represented by sine waves Represented by square waves
Human voice, natural sound, analog electronic Computers, optical drives, and other electronic
devices are few examples devices
Continuous range of values Discontinuous values
Records sound waves as they are Converts into a binary waveform.
Suited for digital electronics like computers,
Only be used in analog devices.
mobiles and more.

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NUMBER SYSTEMS

A digital system can understand positional number system only where there are a few symbols
called digits and these symbols represent different values depending on the position they
occupy in the number.

A value of each digit in a number can be determined using

• The digit
• The position of the digit in the number
• The base of the number system (where base is defined as the total number of digits
available in the number system).

Decimal Number System

The number system that we use in our day-to-day life is the decimal number system. Decimal
number system has base 10 as it uses 10 digits from 0 to 9. In decimal number system, the
successive positions to the left of the decimal point represents units, tens, hundreds, thousands
and so on.

Each position represents a specific power of the base (10). For example, the decimal number
1234 consists of the digit 4 in the units position, 3 in the tens position, 2 in the hundreds
position, and 1 in the thousands position, and its value can be written as

(1×1000) + (2×100) + (3×10) + (4×l)

(1×103) + (2×102) + (3×101) + (4×l00)
1000 + 200 + 30 + 1
1234

Binary Number System

Characteristics

• Uses two digits, 0 and 1.

• Also called base 2 number system
• Each position in a binary number represents a 0 power of the base (2). Example: 20
• Last position in a binary number represents an x power of the base (2). Example: 2x
where x represents the last position - 1.

Example

Binary Number: 101012

Calculating Decimal Equivalent −

Step Binary Number Decimal Number

Step 1 101012 ((1 × 24) + (0 × 23) + (1 × 22) + (0 × 21) + (1 × 20))10

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Step 2 101012 (16 + 0 + 4 + 0 + 1)10

Step 3 101012 2110

Note: 101012 is normally written as 10101.

Octal Number System

Characteristics

• Uses eight digits, 0,1,2,3,4,5,6,7.

• Also called base 8 number system
• Each position in an octal number represents a 0 power of the base (8). Example: 80
• Last position in an octal number represents an x power of the base (8). Example: 8x
where x represents the last position - 1.

Example

Octal Number − 125708

Calculating Decimal Equivalent −

Step Octal Number Decimal Number

Step 1 125708 ((1 × 84) + (2 × 83) + (5 × 82) + (7 × 81) + (0 × 80))10

Step 2 125708 (4096 + 1024 + 320 + 56 + 0)10

Step 3 125708 549610

Note: 125708 is normally written as 12570.

Hexadecimal Number System

Characteristics

• Uses 10 digits and 6 letters, 0,1,2,3,4,5,6,7,8,9, A, B, C, D, E, F.

• Letters represents numbers starting from 10. A = 10, B = 11, C = 12, D = 13, E = 14,
F = 15.
• Also called base 16 number system.
• Each position in a hexadecimal number represents a 0 power of the base (16).
Example 160.
• Last position in a hexadecimal number represents an x power of the base (16).
Example 16x where x represents the last position - 1.

Example −

Hexadecimal Number: 19FDE16

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Calculating Decimal Equivalent −

Step Hexadecimal Number Decimal Number

Step 1 19FDE16 ((1 × 164) + (9 × 163) + (F × 162) + (D × 161) + (E × 160))10

Step 2 19FDE16 ((1 × 164) + (9 × 163) + (15 × 162) + (13 × 161) + (14 × 160))10

Step 3 19FDE16 (65536 + 36864 + 3840 + 208 + 14)10

Step 4 19FDE16 10646210

Note − 19FDE16 is normally written as 19FDE.

NUMBER SYSTEM CONVERSION

There are many methods or techniques which can be used to convert numbers from one base
to another. We'll demonstrate here the following −

• Decimal to Other Base System

• Other Base System to Decimal
• Other Base System to Non-Decimal
• Shortcut method − Binary to Octal
• Shortcut method − Octal to Binary
• Shortcut method − Binary to Hexadecimal
• Shortcut method − Hexadecimal to Binary

Decimal to Other Base System

Steps

• Step 1 − Divide the decimal number to be converted by the value of the new base.
• Step 2 − Get the remainder from Step 1 as the rightmost digit (least significant digit)
of new base number.
• Step 3 − Divide the quotient of the previous divide by the new base.
• Step 4 − Record the remainder from Step 3 as the next digit (to the left) of the new
base number.

Repeat Steps 3 and 4, getting remainders from right to left, until the quotient becomes zero in
Step 3.

The last remainder thus obtained will be the Most Significant Digit (MSD) of the new base
number.

Example −

Decimal Number: 2910

Calculating Binary Equivalent −

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Step Operation Result Remainder

Step 1 29 / 2 14 1

Step 2 14 / 2 7 0

Step 3 7 / 2 3 1

Step 4 3 / 2 1 1

Step 5 1 / 2 0 1

As mentioned in Steps 2 and 4, the remainders have to be arranged in the reverse order so
that the first remainder becomes the Least Significant Digit (LSD) and the last remainder
becomes the Most Significant Digit (MSD).

Decimal Number − 2910 = Binary Number − 111012.

Other Base System to Decimal System

Steps

• Step 1 − Determine the column (positional) value of each digit (this depends on the
position of the digit and the base of the number system).
• Step 2 − Multiply the obtained column values (in Step 1) by the digits in the
corresponding columns.
• Step 3 − Sum the products calculated in Step 2. The total is the equivalent value in
decimal.

Example

Binary Number − 111012

Calculating Decimal Equivalent −

Step Binary Number Decimal Number

Step 1 111012 ((1 × 24) + (1 × 23) + (1 × 22) + (0 × 21) + (1 × 20))10

Step 2 111012 (16 + 8 + 4 + 0 + 1)10

Step 3 111012 2910

Binary Number − 111012 = Decimal Number − 2910

Other Base System to Non-Decimal System

Steps

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• Step 1 − Convert the original number to a decimal number (base 10).

• Step 2 − Convert the decimal number so obtained to the new base number.

Example

Octal Number − 258

Calculating Binary Equivalent −

Step 1 − Convert to Decimal

Step Octal Number Decimal Number

Step 1 258 ((2 × 81) + (5 × 80))10

Step 2 258 (16 + 5 )10

Step 3 258 2110

Octal Number − 258 = Decimal Number − 2110

Step 2 − Convert Decimal to Binary

Step Operation Result Remainder

Step 1 21 / 2 10 1

Step 2 10 / 2 5 0

Step 3 5 / 2 2 1

Step 4 2 / 2 1 0

Step 5 1 / 2 0 1

Decimal Number − 2110 = Binary Number − 101012

Octal Number − 258 = Binary Number − 101012

Shortcut method - Binary to Octal

Steps

• Step 1 − Divide the binary digits into groups of three (starting from the right).
• Step 2 − Convert each group of three binary digits to one octal digit.

Example

Binary Number − 101012

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Calculating Octal Equivalent −

Step Binary Number Octal Number

Step 1 101012 010 101

Step 2 101012 28 58

Step 3 101012 258

Binary Number − 101012 = Octal Number − 258

Shortcut method - Octal to Binary

Steps

• Step 1 − Convert each octal digit to a 3 digit binary number (the octal digits may be
treated as decimal for this conversion).
• Step 2 − Combine all the resulting binary groups (of 3 digits each) into a single
binary number.

Example

Octal Number − 258

Calculating Binary Equivalent −

Step Octal Number Binary Number

Step 1 258 210 510

Step 2 258 0102 1012

Step 3 258 0101012

Octal Number − 258 = Binary Number − 101012

Shortcut method - Binary to Hexadecimal

Steps

• Step 1 − Divide the binary digits into groups of four (starting from the right).
• Step 2 − Convert each group of four binary digits to one hexadecimal symbol.

Example

Binary Number − 101012

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Calculating hexadecimal Equivalent −

Step Binary Number Hexadecimal Number

Step 1 101012 0001 0101

Step 2 101012 110 510

Step 3 101012 1516

Binary Number − 101012 = Hexadecimal Number − 1516

Shortcut method - Hexadecimal to Binary

Steps

• Step 1 − Convert each hexadecimal digit to a 4 digit binary number (the hexadecimal
digits may be treated as decimal for this conversion).
• Step 2 − Combine all the resulting binary groups (of 4 digits each) into a single
binary number.

Example

Hexadecimal Number − 1516

Calculating Binary Equivalent −

Step Hexadecimal Number Binary Number

Step 1 1516 110 510

Step 2 1516 00012 01012

Step 3 1516 000101012

Hexadecimal Number − 1516 = Binary Number − 101012

BOOLEAN ALGEBRA

Boolean Algebra is used to analyze and simplify the digital (logic) circuits. It uses only the
binary numbers i.e. 0 and 1. It is also called as Binary Algebra or logical Algebra. Boolean
algebra was invented by George Boole in 1854.

Rule in Boolean Algebra

Following are the important rules used in Boolean algebra.

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• Variable used can have only two values. Binary 1 for HIGH and Binary 0 for LOW.
• Complement of a variable is represented by an overbar (-). Thus, complement of
variable B is represented as . Thus, if B = 0 then = 1 and B = 1 then = 0.
• ORing of the variables is represented by a plus (+) sign between them. For example,
ORing of A, B, C is represented as A + B + C.
• Logical ANDing of the two or more variable is represented by writing a dot between
them such as A.B.C. Sometime the dot may be omitted like ABC.

Boolean Laws

There are six types of Boolean Laws.

Commutative law

Any binary operation which satisfies the following expression is referred to as commutative
operation.

Commutative law states that changing the sequence of the variables does not have any effect
on the output of a logic circuit.

Associative law

This law states that the order in which the logic operations are performed is irrelevant as their
effect is the same.

Distributive law

Distributive law states the following condition.

AND law

These laws use the AND operation. Therefore, they are called as AND laws.

OR law

These laws use the OR operation. Therefore they are called as OR laws.

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INVERSION law

This law uses the NOT operation. The inversion law states that double inversion of a variable
results in the original variable itself.

Important Boolean Theorems

Following are few important boolean Theorems.

Boolean function/theorems Description

Boolean Functions and Expressions, K-Map and NAND Gates

Boolean Functions realization

De Morgan's Theorems De Morgan's Theorem 1 and Theorem 2

LOGIC GATES

Logic gates are the basic building blocks of any digital system. It is an electronic circuit having
one or more than one input and only one output. The relationship between the input and the
output is based on a certain logic. Based on this, logic gates are named as AND gate, OR gate,
NOT gate etc.

AND Gate

A circuit which performs an AND operation is shown in figure. It has n input (n >= 2) and
one output.

Logic diagram

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Truth Table

OR Gate

A circuit which performs an OR operation is shown in figure. It has n input (n >= 2) and one
output.

Logic diagram

Truth Table

NOT Gate

NOT gate is also known as Inverter. It has one input A and one output Y.

Logic diagram

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Truth Table

NAND Gate

A NOT-AND operation is known as NAND operation. It has n input (n >= 2) and one output.

Logic diagram

Truth Table

NOR Gate

A NOT-OR operation is known as NOR operation. It has n input (n >= 2) and one output.

Logic diagram

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Truth Table

XOR Gate

XOR or Ex-OR gate is a special type of gate. It can be used in the half adder, full adder and
subtractor. The exclusive-OR gate is abbreviated as EX-OR gate or sometime as X-OR gate.
It has n input (n >= 2) and one output.

Logic diagram

Truth Table

XNOR Gate

XNOR gate is a special type of gate. It can be used in the half adder, full adder and
subtractor. The exclusive-NOR gate is abbreviated as EX-NOR gate or sometime as X-NOR
gate. It has n input (n >= 2) and one output.

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Logic diagram

Truth Table

COMBINATIONAL CIRCUITS

Combinational circuit is a circuit in which we combine the different gates in the circuit, for
example encoder, decoder, multiplexer and demultiplexer. Some of the characteristics of
combinational circuits are following −

• The output of combinational circuit at any instant of time, depends only on the levels
present at input terminals.
• The combinational circuit do not use any memory. The previous state of input does not
have any effect on the present state of the circuit.
• A combinational circuit can have an n number of inputs and m number of outputs.

Block diagram

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Half Adder

Half adder is a combinational logic circuit with two inputs and two outputs. The half adder
circuit is designed to add two single bit binary number A and B. It is the basic building block
for addition of two single bit numbers. This circuit has two outputs carry and sum.

Block diagram

Truth Table

Circuit Diagram

Full Adder

Full adder is developed to overcome the drawback of Half Adder circuit. It can add two one-
bit numbers A and B, and carry c. The full adder is a three input and two output combinational
circuit.

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Block diagram

Truth Table

Circuit Diagram

Multiplexers

Multiplexer is a special type of combinational circuit. There are n-data inputs, one output and
m select inputs with 2m = n. It is a digital circuit which selects one of the n data inputs and
routes it to the output. The selection of one of the n inputs is done by the selected inputs.
Depending on the digital code applied at the selected inputs, one out of n data sources is
selected and transmitted to the single output Y. E is called the strobe or enable input which is
useful for the cascading. It is generally an active low terminal that means it will perform the
required operation when it is low.

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Block diagram

Multiplexers come in multiple variations

• 2 : 1 multiplexer
• 4 : 1 multiplexer
• 16 : 1 multiplexer
• 32 : 1 multiplexer

Block Diagram

Truth Table

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Decoder

A decoder is a combinational circuit. It has n input and to a maximum m = 2n outputs. Decoder

is identical to a demultiplexer without any data input. It performs operations which are exactly
opposite to those of an encoder.

Block diagram

Examples of Decoders are following.

• Code converters
• BCD to seven segment decoders
• Nixie tube decoders
• Relay actuator

2 to 4 Line Decoder

The block diagram of 2 to 4 line decoder is shown in the fig. A and B are the two inputs where
D through D are the four outputs. Truth table explains the operations of a decoder. It shows
that each output is 1 for only a specific combination of inputs.

Block diagram

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Truth Table

Logic Circuit

SEQUENTIAL CIRCUITS

The combinational circuit does not use any memory. Hence the previous state of input does not
have any effect on the present state of the circuit. But sequential circuit has memory so output
can vary based on input. This type of circuits uses previous input, output, clock and a memory
element.

Block diagram

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Flip Flop

Flip flop is a sequential circuit which generally samples its inputs and changes its outputs only
at particular instants of time and not continuously. Flip flop is said to be edge sensitive or edge
triggered rather than being level triggered like latches.

S-R Flip Flop

It is basically S-R latch using NAND gates with an additional enable input. It is also called as
level triggered SR-FF. For this, circuit in output will take place if and only if the enable input
(E) is made active. In short this circuit will operate as an S-R latch if E = 1 but there is no
change in the output if E = 0.

Block Diagram

Circuit Diagram

Truth Table

Operation
S.N. Condition Operation

If S = R = 0 then output of NAND gates 3 and 4 are forced to

1 S = R = 0 : No change become 1.

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Hence R' and S' both will be equal to 1. Since S' and R' are
the input of the basic S-R latch using NAND gates, there will
be no change in the state of outputs.
Since S = 0, output of NAND-3 i.e. R' = 1 and E = 1 the
2 S = 0, R = 1, E = 1 output of NAND-4 i.e. S' = 0.

Hence Qn+1 = 0 and Qn+1 bar = 1. This is reset condition.

Output of NAND-3 i.e. R' = 0 and output of NAND-4 i.e. S'
= 1.
3 S = 1, R = 0, E = 1
Hence output of S-R NAND latch is Qn+1 = 1 and Qn+1 bar =
0. This is the reset condition.
As S = 1, R = 1 and E = 1, the output of NAND gates 3 and 4
both are 0 i.e. S' = R' = 0.
4 S = 1, R = 1, E = 1
Hence the Race condition will occur in the basic NAND
latch.

Master Slave JK Flip Flop

Master slave JK FF is a cascade of two S-R FF with feedback from the output of second to
input of first. Master is a positive level triggered. But due to the presence of the inverter in the
clock line, the slave will respond to the negative level. Hence when the clock = 1 (positive
level) the master is active and the slave is inactive. Whereas when clock = 0 (low level) the
slave is active and master is inactive.

Circuit Diagram

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Truth Table

Operation
S.N. Condition Operation

When clock = 0, the slave becomes active and master is

1 J = K = 0 (No change) inactive. But since the S and R inputs have not changed, the
slave outputs will also remain unchanged. Therefore outputs
will not change if J = K =0.
Clock = 1 − Master active, slave inactive. Therefore outputs
of the master become Q1 = 0 and Q1 bar = 1. That means S =
0 and R =1.

Clock = 0 − Slave active, master inactive. Therefore outputs

of the slave become Q = 0 and Q bar = 1.
2 J = 0 and K = 1 (Reset) Again clock = 1 − Master active, slave inactive. Therefore
even with the changed outputs Q = 0 and Q bar = 1 fed back
to master, its output will be Q1 = 0 and Q1 bar = 1. That
means S = 0 and R = 1.

Hence with clock = 0 and slave becoming active the outputs

of slave will remain Q = 0 and Q bar = 1. Thus we get a
stable output from the Master slave.
Clock = 1 − Master active, slave inactive. Therefore outputs
of the master become Q1 = 1 and Q1 bar = 0. That means S =
1 and R =0.
3 J = 1 and K = 0 (Set) Clock = 0 − Slave active, master inactive. Therefore outputs
of the slave become Q = 1 and Q bar = 0.

Again clock = 1 − then it can be shown that the outputs of

the slave are stabilized to Q = 1 and Q bar = 0.
Clock = 1 − Master active, slave inactive. Outputs of master
will toggle. So S and R also will be inverted.
4 J = K = 1 (Toggle)
Clock = 0 − Slave active, master inactive. Outputs of slave
will toggle.

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These changed output are returned back to the master inputs.

But since clock = 0, the master is still inactive. So it does not
respond to these changed outputs. This avoids the multiple
toggling which leads to the race around condition. The
master slave flip flop will avoid the race around condition.

DIGITAL REGISTERS

Flip-flop is a 1 bit memory cell which can be used for storing the digital data. To increase the
storage capacity in terms of number of bits, we have to use a group of flip-flop. Such a group
of flip-flop is known as a Register. The n-bit register will consist of n number of flip-flop and
it is capable of storing an n-bit word.

The binary data in a register can be moved within the register from one flip-flop to another.
The registers that allow such data transfers are called as shift registers. There are four mode of
operations of a shift register.

• Serial Input Serial Output

• Serial Input Parallel Output
• Parallel Input Serial Output
• Parallel Input Parallel Output

Serial Input Serial Output

Let all the flip-flop be initially in the reset condition i.e. Q3 = Q2 = Q1 = Q0 = 0. If an entry of
a four bit binary number 1 1 1 1 is made into the register, this number should be applied to Din
bit with the LSB bit applied first. The D input of FF-3 i.e. D3 is connected to serial data input
Din. Output of FF-3 i.e. Q3 is connected to the input of the next flip-flop i.e. D2 and so on.

Block Diagram

Operation

Before application of clock signal, let Q3 Q2 Q1 Q0 = 0000 and apply LSB bit of the number
to be entered to Din. So Din = D3 = 1. Apply the clock. On the first falling edge of clock, the
FF-3 is set, and stored word in the register is Q3 Q2 Q1 Q0 = 1000.

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Apply the next bit to Din. So Din = 1. As soon as the next negative edge of the clock hits, FF-2
will set and the stored word change to Q3 Q2 Q1 Q0 = 1100.

Apply the next bit to be stored i.e. 1 to Din. Apply the clock pulse. As soon as the third
negative clock edge hits, FF-1 will be set and output will be modified to Q3 Q2 Q1 Q0 = 1110.

Similarly with Din = 1 and with the fourth negative clock edge arriving, the stored word in the
register is Q3 Q2 Q1 Q0 = 1111.

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Truth Table

Waveforms

Serial Input Parallel Output

• In such types of operations, the data is entered serially and taken out in parallel
fashion.
• Data is loaded bit by bit. The outputs are disabled as long as the data is loading.
• As soon as the data loading gets completed, all the flip-flops contain their required
data, the outputs are enabled so that all the loaded data is made available over all the
output lines at the same time.
• 4 clock cycles are required to load a four bit word. Hence the speed of operation of
SIPO mode is same as that of SISO mode.

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Block Diagram

DIGITAL COUNTERS

Counter is a sequential circuit. A digital circuit which is used for a counting pulses is known
counter. Counter is the widest application of flip-flops. It is a group of flip-flops with a clock
signal applied. Counters are of two types.

• Asynchronous or ripple counters.

• Synchronous counters.

RIPPLE COUNTER

A n-bit ripple counter can count up to 2n states. It is also known as MOD n counter. It is known
as ripple counter because of the way the clock pulse ripples its way through the flip-flops. Some
of the features of ripple counter are:

1. It is an asynchronous counter.
2. Different flip-flops are used with a different clock pulse.
3. All the flip-flops are used in toggle mode.
4. Only one flip-flop is applied with an external clock pulse and another flip-flop clock is
obtained from the output of the previous flip-flop.
5. The flip-flop applied with external clock pulse act as LSB (Least Significant Bit) in the
counting sequence.

A counter may be an up counter that counts upwards or can be a down counter that counts
downwards or can do both i.e.count up as well as count downwards depending on the input
control. The sequence of counting usually gets repeated after a limit. When counting up, for n-
bit counter the count sequence goes from 000, 001, 010, … 110, 111, 000, 001, … etc. When
counting down the count sequence goes in the opposite manner: 111, 110, … 010, 001, 000,
111, 110, … etc.

A 3-bit Ripple counter using JK flip-flop –

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In the circuit shown in above figure, Q0(LSB) will toggle for every clock pulse because JK
flip-flop works in toggle mode when both J and K are applied 1, 1 or high input. The
following counter will toggle when the previous one changes from 1 to 0

Truth Table –

The 3-bit ripple counter used in the circuit above has eight different states, each one of which
represents a count value. Similarly, a counter having n flip-flops can have a maximum of 2 to
the power n states. The number of states that a counter owns is known as its mod (modulo)
number. Hence a 3-bit counter is a mod-8 counter.

A mod-n counter may also be described as a divide-by-n counter. This is because the most
significant flip-flop (the furthest flip-flop from the original clock pulse) produces one pulse for
every n pulses at the clock input of the least significant flip-flop (the one triggers by the clock
pulse). Thus, the above counter is an example of a divide-by-4 counter.

Timing diagram – Let us assume that the clock is negative edge triggered so above counter
will act as an up counter because the clock is negative edge triggered and output is taken from
Q.

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COMMUNICATION SYSTEMS

The communication system is a system which describes the information exchange between two
points. The process of transmission and reception of information is called communication. The
major elements of communication are the Transmitter of information, Channel or medium
of communication and the Receiver of information.

Types of Communication Systems

Depending on Signal specification or technology, the communication system is classified as

follows:

(1) Analog

Analog technology communicates data as electronic signals of varying frequency or amplitude.

Broadcast and telephone transmission are common examples of Analog technology.

(2) Digital

In digital technology, the data are generated and processed in two states: High (represented as
1) and Low (represented as 0). Digital technology stores and transmits data in the form of 1s
and 0s.

Depending on the communication channel, the communication system is categorized as

follows:

1. Wired (Line communication)

• Parallel wire communication

• Twisted wire communication
• Coaxial cable communication
• Optical fibre communication

2. Wireless (Space communication)

• Ground wave communication

• Skywave communication
• Space wave communication
• Satellite communication

Examples of Communication Systems

The following are a few examples of communication systems:

1. Internet

2. Public Switched Telephone network

3. Intranet and Extranet

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4. Television

Elements of Communication Systems

The definitions of the terms used in the communication system are discussed below.

Information

Message or information is the entity that is to be transmitted. It can be in the form of audio,
video, temperature, picture, pressure, etc.

Signal

The single-valued function of time that carries the information. The information is converted
into an electrical form for transmission.

Transducer

A device or an arrangement that converts one form of energy to the other. An electrical
transducer converts physical variables such as pressure, force, temperature into corresponding
electrical signal variations. Example: Microphone – converts audio signals into electrical
signals. Photodetector – converts light signals into electrical signals.

Amplifier

The electronic circuit or device that increases the amplitude or the strength of the transmitted
signal is called an amplifier. When the signal strength becomes less than the required value,
amplification can be done anywhere in between transmitter and receiver. A DC power source
will provide for the amplification.

Modulator

As the original message signal cannot be transmitted over a large distance because of their low
frequency and amplitude, they are superimposed with high frequency and amplitude wave
called carrier wave. This phenomenon of superimposing of message signal with a carrier wave
is called modulation. And the resultant wave is a modulated wave which is to be transmitted.

Again there are different types of Modulation.

i. Amplitude Modulation (AM)

The process of changing the amplitude of the signal wave by impressing or superimposing it
on a high-frequency carrier wave, keeping its frequency constant is called amplitude
modulation.

ii. Frequency Modulation (FM)

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Frequency modulation is a technique in which the frequency of the message signal is varied
by modulating with a carrier wave. It is better than deficient than amplitude modulation
because it eliminates noise from various sources.

iii. Phase Modulation (PM)

The phase of the carrier wave changes the phase of the signal wave. The phase shift after
modulation is dependent on the frequency of the carrier wave as well. Phase modulated
waves are immune to noise to a greater extent.

Transmitter

It is the arrangement that processes the message signal into a suitable form for transmission
and subsequently reception.

Antenna

An Antenna is a structure or a device that is radiate and receive electromagnetic waves. So,
they are used in both transmitters and receivers. An antenna is basically a metallic object,
often a collection of wires. The electromagnetic waves are polarised according to the position
of the antenna.

Channel

A channel refers to a physical medium such as wire, cables, space through which the signal is
passed from transmitter to the receiver. There are many channel impairments that affect the
channel performance to a pronounced level. Noise, Attenuation and distortion to mention the
major impairments.

Noise

Noise is one of the channel imperfection or impairment in the received signal at the
destination. There are external and internal sources that cause noise. External sources include
interference, i.e. interference from nearby transmitted signals (cross talk), interference
generated by natural source such as lightning, solar or cosmic radiation, from automobile
generated radiation, etc. The external noise can be minimised and eliminated by appropriate
design of the channel, shielding of cables. Also by digital transmission external noise can be
much minimised.

Internal sources include noise due to random motion and collision of electrons in the
conductors, thermal noise due to diffusion and recombination of charge carriers in other
electronic devices. Internal noise can be minimised by cooling and using digital technology
for transmission.

• A different cable design.

• Proper design of the channel.
• Use digital transmission
• Using BPF or LPF at the receiver side.

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Attenuation

Attenuation is a problem caused by the medium. When the signal is propagating for a longer
distance through a medium, depending on the length of the medium the initial power
decreases. The loss in initial power is directly proportional to the length of the medium.
Using amplifiers, the signal power is strengthened or amplified so as to reduce attenuation.
Also, digital signals are comparatively less prone to attenuation than analogue signals.

Distortion

It is also another type of channel problem. When the signal is distorted, the distorted signal
may have frequency and bandwidth different from the transmitted signal. The variation in the
signal frequency can be linear or non-linear.

Receiver

An arrangement that extracts the message or information from the transmitted signal at the
output end of the channel and reproduces it in a suitable form as the original message signal
is a receiver.

Demodulator

It is the inverse phenomenon of modulation. The process of separation of message signal

from the carrier wave takes place in the demodulator. The information is retrieved from the
modulated wave.

Repeaters

Repeaters are placed at different locations in between the transmitter and receiver. A repeater
receives the transmitted signal, amplifies it and send it to the next repeater without distorting
the original signal.

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Block Diagram of Communication Systems

The block diagram given below represents the flow of the signal from the source to the
destination. The role of every device and arrangement discussed above is better understood.

PRINCIPLE OF OPERATION OF MOBILE PHONE

A cellular/mobile system provides standard telephone operation by full-duplex two-way radio

at remote locations. It provides a wireless connection to the Public Switched Telephone
Network (PSTN) from any user location within the radio range of the system.

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The basic concept behind the cellular radio system is that rather than serving a given
geographical area within a single transmitter and receiver, the system divides the service area
into many small areas known as cells, as shown in Fig. below. The typical cell covers only
several square kilometers and contains its own receiver and low-power transmitter. The cell
area shown in Fig. below is ideal hexagon. However, in reality they will have circular or other
geometric shapes. These areas may overlap, and cells may be of different sizes.

Basic cellular system consists of mobile stations, base stations and a mobile switching center
(MSC). The MSC is also known as Mobile Telephone Switching Office (MTSO). The MTSO
controls ’11 the cells and provides the interface between each cell and the main telephone
office. Each mobile communicates via radio with one of the base stations and may be handed
off (switched from one cell to another) to any other base station throughout the duration of the
call.

Each mobile station consists of a transceiver, an antenna and control circuitry. The base station
consists of several transmitters and receivers which simultaneously handle full duplex
communication and generally have towers which support several transmitting and receiving
antennas. The base station serves as a bridge between all mobile users in the cell and connects
the simultaneous mobile calls via telephone lines or microwave link to the MSC. The MSC co-
ordinates the activities of all the base stations and connects the entire cellular system to the
PSTN, most of the cellular system also provide a service known as roaming.

The cellular system operates in the 800-900 MHz range. The newer digital cellular systems
have even greater capacity. Some of these systems operate in 1.7-1.8 GHz bands.

Cellular Telephone Unit

The Fig. below shows the block diagram of a cellular mobile radio unit. The unit consists of
five major sections:

Transmitter, receiver, synthesizer, logic unit, and control unit. The mobile unit contains built-
in rechargeable batteries to Provide operating power. The transmitter and receiver in the unit
share the common antenna.

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