ARM Processor Fundamentals

ARM core dataflow model

Data
Instruction
Decoder
Sign Extend

Read

r15 Register File Rd

r0 – r15
pc Result
R A B
n Rm
A B Acc
Barrel Shifter
N MAC

ALU

Address Register

Incrementer
Address
 Registers
• ARM has Load Store Architecture

• General Purpose Registers can hold data or address

• Total of 37 Registers, each of 32 bit

• There are 17 or 18 active Registers

– 16 data registers
– 2 status registers
 Registers – User Mode
• Registers R0 – R12 are General Purpose
Registers
• R13 is used as Stack Pointer (sp)
• R14 is used as Link register (lr)
• R15 is used as Program Counter (pc)
• CPSR is Current Program Status
Register
• SPSR is Saved Program Status Register
R0
R1
R2
 R3
R4
R5
R6
R7
R8
R9
R10
R11
R12
R13
R14
R15
CPSR
SPSR
 Current Program Status Register

• To monitor and control internal

operations
• Some ARM Processor core have extra bits
allocated
Flags Status Extension Control
Fields
Bit 31 30 29 28 7 6 5 4 0

NZ CV I F T Mode
Function Condition Flags Interrupt Processor Mode
Masks

Thumb State
 Processor Modes
• Determines which registers are active and the
access rights to the cpsr register itself
• Privileged & Nonprivileged
– Abort
– Fast Interrupt Request
– Interrupt – User
Request –
Supervisor
– System
– Undefined
Privileged

Nonprivileged
 Banked Registers
r0
r1 Banked Registers
r2
r3
r4
r5 Fast
r6 Interrupt
r7 Request
r8 r8_fiq
r9 r9_fiq
r10 r10_fiq Interrupt
r11 r11_fiq
Request Supervisor Undefined
r12 r12_fiq
r13 sp r13_fiq r13_irq r13_svc r13_undef r13_abt
r14 lr r14_fiq r14_irq r14_svc r14_undef r14_abt
r15 pc

cpsr
- spsr_fiq spsr_irq spsr_svc spsr_undef spsr_abt
 Banked Registers
• Banked registers are available only when the processor
is in a particular mode

• Every processor mode except user

can change mode
mode by writing to the
mode bits of the cpsr

• Banked registers are a subset of the main 16 registers

• If we change processor mode, a

banked register from
the new mode will replace an existing register
• Exceptions and Interrupts cause a mode change
 Changing mode on an exception
User Mode
r0
r1 • This change causes user
r2
r3
register r13 and r14 to be
r4
r5
banked
r6
r7 • The user registers are
r8
r9 replaced with registers
Interrupt
r10
r11 Request r13_irq and r14_irq
r12 Mode
r13 sp r13_irq • spsr stores the previous
r14 lr r14_irq
r15 pc mode cpsr
cpsr
spsr_irq
-
 Processor Mode
Mode Abbr: Privileged Mode[4:0]

Abort abt yes 10111

Fast Interrupt Request fiq yes 10001
Interrupt Request irq yes 10010
Supervisor svc yes 10011
System sys yes 11111
Undefined und yes 11011
User usr no 10000

cpsr is not copied into the spsr when a mode

change is forced due to a program writing
directly to the cpsr.
 Operation Modes
Mode Registers CPSR[4:0]
User User 10000
FIQ _fiq 10001
IRQ _irq 10010
Supervisor Mode _svc 10011
Abort _abt 10111
Undefined Instruction _und 11011
System User 11111
 Processor Modes
User Unprivileged mode for most applications to
run
FIQ Fast Interrupt Routine
IRQ Interrupt Routines
Supervisor Entered on reset and when there is a
exception
Abort Entered when data or instruction prefetch
aborted
Undefined When an undefined instructions is executed

System Privileged user mode for operating system

 State and Instruction Sets
• There are three instruction sets
– ARM
– Thumb
– Jazelle
The Jazelle instruction set is a closed instruction set and is
not openly available.

To take advantage of Jazelle extra software has to be

licensed from both ARM Limited and Sun Microsystems.
 State and Instruction Sets
ARM Thumb
(cpsr T = 0) (cpsr T = 1)
Instruction Size 32 bit 16 bit

Core Instruction 58 30

Conditional Execution Most Only branch instructions

Data Processing Instructions Access to barrel shifter Separate barrel and ALU
and ALU instructions
Program Status Register R/W in privileged mode No direct access
Register Usage 15 GPR + PC 8 GPR + 7 high registers
+ PC
 State and Instruction Sets

Jazelle
(cpsr T = 0, J = 1)
Instruction Size 8 bit

Core Instruction Over 60% of the java bytecodes are implemented in

hardware; the rest of the codes are implemented in
software
 Interrupt Masks
• Are used to stop specific interrupt
requests from interrupting the processor
– IRQ
– FIQ
• The I bit masks IRQ when set to binary 1,
and F bit masks FIQ when set to binary 1
 Condition Flags
Flag Flag Name Set when

Q Saturation The result causes an overflow and / or saturation

V oVerflow The result causes a signed overflow

C Carry The result causes an unsigned carry

Z Zero The result is zero, frequently used to indicate the

equality
N Negative Bit 31 of the result is a binary 1
 Condition Flags
• Condition flags are updated by
comparisons and the result of ALU
operations that specify the S instruction
suffix
– If SUBS results in a register
value of zero, then the Z
flag in the CPSR is set
 CPSR
Flags Status Extension Control
Fields
Bit 31 30 29 28 27 24 7 6 5 4 0

0 0 1 0 0 0 0 1 0 10011

Function nzCvq j i F t svc

cpsr = nzCvqjiFt_SVC
 CPSR
31 28 24 23 16 15 8 7 6 5 4 0
N Z C V J U n d e f i n e d I F T mode

 hold information about the most recently performed ALU operation

 set the processor operating mode
• Condition code flags
– N = Negative result from ALU • Interrupt Disable bits.
– Z = Zero result from ALU – I = 1: Disables the IRQ.
– C = ALU operation Carried out – F = 1: Disables the FIQ.
– V = ALU operation oVerflowed • T Bit
• J bit – Architecture xT only
– Architecture 5TEJ only – T = 0: Processor in ARM state
– J = 1: Processor in Jazelle – T = 1: Processor in Thumb state
state • Mode bits
– Specify the processor mode
 Pipeline
• Is a mechanism a RISC processor uses to
execute instructions

• Using a pipeline speeds up execution by

fetching the next instruction while other
instructions are being decoded and executed
ARM7 Three stage pipeline
Fetch Decode Execute

•Fetch loads an instruction from memory

•Decode identifies the instruction to be
executed
•Execute processes the instruction and
writes the result back to a register
Fe
Pipeline d tc
h
instruction sequence
Decode Execute
Cycle 1 ADD
Time
Cycle 2 SUB ADD

Cycle 3 CMP SUB ADD

• Filling the pipeline

• Allows the core to execute an
instruction every cycle
 ARM9 Five stage pipeline
Fetch Decode Execute Memory Write

•Higher operating frequency 

higher performance
•Latency increases
•Increase in instruction throughput by around
13% in 5 stage pipeline
•1.1 Dhrystone MIPS per MHz
 ARM9 Five stage pipeline
• Fetch
– The instruction is fetched from memory and placed in the
instruction pipeline
• Decode
– The instruction is decoded and register operands read from the
register file
• Execute
– An operand is shifted and the ALU result generated
• Memory (Buffer/Data)
– Data memory is accessed if required. Otherwise the ALU result is
buffered for one clock cycle to give the same pipeline flow for all
instructions
• Write (Write-Back)
– The results generated by the instruction are written back to the
register file, including any data loaded from memory
 ARM10 Six stage pipeline

Fetch Issue Decode Execute Memory Write

• Increase in instruction throughput by

around 34% in 6 stage pipeline
• 1.3 Dhrystone MIPS per MHz
• Code written for the ARM7 will execute on ARM9 and
ARM10
 ARM Instruction Sequence
Fetch Decode Execute
cpsr
Time Cycle 1 MSR IFt_SVC
cpsr
Cycle 2 ADD MSR IFt_SVC
cpsr
Cycle 3 AND ADD MSR iFt_SVC

Cycle 4 SUB AND ADD

 Pipeline Characteristics
• An instruction in the execute stage will
complete even though an interrupt has been
raised

• The execution of a branch instruction or

branching by the direct modification of the
PC causes the ARM core to flush its pipeline