Scribd
Upload
190 views

Chapter 7-User Defined Primitives

Verilog allows users to define their own primitives (UDPs) to model complex logic beyond built-in gates. UDPs are defined using the primitive keyword outside of modules. UDPs can model combinational or sequential logic. Combinational UDPs specify the output for each input combination using a state table. Sequential UDPs additionally specify the current state and can be either level-sensitive, where the output depends on current inputs and state, or edge-sensitive, where the output depends on input edge transitions. Initial values for sequential UDP outputs can be set using the initial keyword.

Uploaded by

Danh ZEUS49
Copyright
© © All Rights Reserved
Available Formats
Download as PDF, TXT or read online on Scribd
190 views

Chapter 7-User Defined Primitives

Verilog allows users to define their own primitives (UDPs) to model complex logic beyond built-in gates. UDPs are defined using the primitive keyword outside of modules. UDPs can model combinational or sequential logic. Combinational UDPs specify the output for each input combination using a state table. Sequential UDPs additionally specify the current state and can be either level-sensitive, where the output depends on current inputs and state, or edge-sensitive, where the output depends on input edge transitions. Initial values for sequential UDP outputs can be set using the initial keyword.

Uploaded by

Danh ZEUS49
Copyright
© © All Rights Reserved
Available Formats
Download as PDF, TXT or read online on Scribd
You are on page 1/ 19

VERILOG HDL

Chapter 7

User Defined Primitives

Trương Phong Tuyên


Introduction

• Verilog has built-in primitives like gates, transmission


gates, and switches. This is a rather small number of
primitives; if we need more complex primitives, then
Verilog provides UDP, or simply User Defined
Primitives. Using UDP we can model:
 Combinational Logic
 Sequential Logic

• We can include timing information along with these


UDP to model complete ASIC library models.

2
Syntax

• UDP begins with reserve word primitive and


ends with endprimitive
• Ports/terminals of primitive should follow. This
is similar to what we do for module definition.
• UDPs should be defined outside module and
endmodule

3
Syntax

• Example

4
UDP ports rules

• An UDP can contain only one output and up to


10 inputs.
• Output port should be the first port followed by
one or more input ports.
• All UDP ports are scalar, i.e. Vector ports are
not allowed.
• UDPs can not have bidirectional ports.
• The output terminal of a sequential UDP
requires an additional declaration as type reg.
• It is illegal to declare a reg for the output
terminal of a combinational UDP.

5
The Body of UDP

• Functionality of primitive (both combinational


and sequential) is described inside a table,
and it ends with reserved word endtable as
shown in the code below. For sequential
UDP, we can use initial to assign an initial
value to output.

6
The Body of UDP (cont.)

Note: An UDP cannot


use 'z' in the input table

7
Table and Initial
• Table
 Table is used for describing the function of
UDP. Verilog reserved word table marks the
start of table and reserved word endtable
marks the end of table.
 Each line inside a table is one condition;
when an input changes, the input condition
is matched and the output is evaluated to
reflect the new change in input.
• Initial
 Initial statement is used for initialization of
sequential UDPs. This statement begins with
the keyword 'initial'. The statement that
follows must be an assignment statement
that assigns a single bit literal value to the
output terminal reg.

8
Symbol
• UDP uses special symbols to describe functions like rising edge,
don't care and so on. The table below shows the symbols that are
used in UDPs.

9
Combinational UDPs

• In combinational UDPs, the output is determined as a


function of the current input. Whenever an input changes
value, the UDP is evaluated and one of the state table
rows is matched. The output state is set to the value
indicated by that row. This is similar to condition
statements: each line in table is one condition.
• Combinational UDPs have one field per input and one field
for the output. Input fields and output fields are separated
with colon. Each row of the table is terminated by a
semicolon. For example, the following state table entry
specifies that when the three inputs are all 0, the output is
0.

10
Combinational UDPs (cont.)
• The order of the inputs in the state
table description must correspond to
the order of the inputs in the port list
in the UDP definition header. It is not
related to the order of the input
declarations.
• Each row in the table defines the
output for a particular combination of
input states. If all inputs are specified
as x, then the output must be
specified as x. All combinations that
are not explicitly specified result in a
default output state of x.

11
Combinational UDPs (cont.)

• In the below example entry, the ? represents a


don't-care condition. This symbol indicates
iterative substitution of 1, 0, and x. The table
entry specifies that when the inputs are 0 and
1, the output is 1 no matter what the value of
the current state is.
• You do not have to explicitly specify every
possible input combination. All combinations
that are not explicitly specified result in a
default output state of x.
• It is illegal to have the same combination of
inputs, specified for different outputs.

12
The Body of UDP (cont.)

13
Level Sensitive Sequential UDP
• Level-sensitive sequential behavior is represented in the
same way as combinational behavior, except that the
output is declared to be of type reg, and there is an
additional field in each table entry. This new field
represents the current state of the UDP.
 The output is declared as reg to indicate that there is an internal
state. The output value of the UDP is always the same as the
internal state.
 A field for the current state has been added. This field is
separated by colons from the inputs and the output.
• Sequential UDPs have an additional field inserted
between the input fields and the output field, compared to
combinational UDP. This additional field represents the
current state of the UDP and is considered equivalent to
the current output value. It is delimited by colons.

14
Level Sensitive Sequential UDP (cont.)

• Example

15
Edge-Sensitive UDPs
• In level-sensitive behavior, the values of the inputs and the
current state are sufficient to determine the output value.
Edge-sensitive behavior differs in that changes in the output
are triggered by specific transitions of the inputs.
• As in the combinational and the level-sensitive entries, a ?
implies iteration of the entry over the values 0, 1, and x. A
dash (-) in the output column indicates no value change.
• All unspecified transitions default to the output value x. Thus,
in the previous example, transition of clock from 0 to x with
data equal to 0 and current state equal to 1 result in the
output q going to x.
• All transitions that should not affect the output must be
explicitly specified. Otherwise, they will cause the value of the
output to change to x. If the UDP is sensitive to edges of any
input, the desired output state must be specified for all edges
of all inputs.
16
Edge-Sensitive UDPs (cont.)

17
Example UDP with initial

18
The End

You might also like

pFad - Phonifier reborn

Pfad - The Proxy pFad of © 2024 Garber Painting. All rights reserved.

Note: This service is not intended for secure transactions such as banking, social media, email, or purchasing. Use at your own risk. We assume no liability whatsoever for broken pages.


Alternative Proxies:

Alternative Proxy

pFad Proxy

pFad v3 Proxy

pFad v4 Proxy