1742 IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS, VOL. 21, NO.

9, SEPTEMBER 2013

[5] S. Mahapatra, V. Vaish, C. Wasshuber, K. Banerjee, and A. M. Ionescu,

“Analytical modeling of single electron transistor (SET) for hybrid
CMOS-SET analog IC design,” IEEE Trans. Electron. Devices, vol. 51,
no. 11, pp. 1772–1782, Nov. 2004.
[6] H. Grabert and M. H. Devoret, Single Charge Tunneling: Coulomb
Blockade Phenomena in Nanostructures. New York: Plenum,
1992.
[7] I. Koren, Computer Arithmetic Algorithms, 2nd ed. Natick, MA:
A. K. Peters, 2002.
[8] M. M. Dastjerdi, A. A. Kusha, and M. Pedram, “BZFAD: A low power
low area multiplier based on shift and add architecture,” IEEE Trans.
Very Large Scale Integr. (VLSI) Syst., vol. 17, no. 2, pp. 302–306,
Feb. 2009.
[9] S. S. Dan and S. Mahapatra, “Impact of energy quantization on the
performance of current-biased SET circuits,” IEEE Trans. Electron.
Devices, vol. 56, no. 8, pp. 1562–1566, Aug. 2009.
[10] M. Goossens, J. Ritskes, C. Verhoeven, and A. van Roermund, “Learning
single electron tunneling neural nets,” in Proc. ProRISC Workshop
Circuits, Syst. Signal Process., 1997, pp. 179–186.
Fig. 1. LDO structure without output capacitors.

Fast Transient Low-Dropout Voltage Regulator With voltage (VOUT ) [4], [5]. In SoC applications [6]–[9], to reduce the
Hybrid Dynamic Biasing Technique for SoC Application undershoot or overshoot of the output voltage, the use of a large
output capacitor will require an extra pin, which is therefore not
Chia-Min Chen, Student Member, IEEE, Tung-Wei Tsai, and preferred. To effectively increase the slew rate instantly seems to be
Chung-Chih Hung, Senior Member, IEEE a better approach to cope with output voltage spikes.
There are many ways to solve the voltage spike problem. One
Abstract— This brief presents a low-dropout (LDO) voltage regulator method is to use a constant bias current to increase the slew rate,
without output capacitors that achieves fast transient responses by where the bias current is not dependent on the output current. Besides,
hybrid dynamic biasing. The hybrid dynamic biasing in the proposed a previous design incorporates a 600-pF on-chip capacitor to reduce
transient improvement circuit is activated through capacitive coupling. the output voltage ripple [10]. This method does not meet the power-
The proposed circuit senses the LDO regulator output change so as to
saving and area-limited requirements of SoC designs.
increase the bias current instantly. The proposed circuit was applied to
an LDO regulator without output capacitors implemented in standard The other method is the push–pull biasing method [11]. More
0.35-µm CMOS technology. The device consumes only 25 µA of quiescent bias current will be used at the transient instant only if the output
current with a dropout voltage of 180 mV. The proposed circuit reduces current changes. The error amplifier uses a push–pull output stage
the output voltage spike of the LDO regulator to 80 mV when the output to increase the current for charging and discharging the gate capaci-
current is changed from 0 to 100 mA. The output voltage spike is reduced
to 20 mV when the supply voltage varies between 1.3 and 2.3 V with a tance of the power transistor (CPAR_IN ) during the transient instant.
load current of 100 mA. A differential-input common-gate amplifier activates the push–pull
output stage. However, the fast-changing voltage spike cannot be
Index Terms— Capacitive coupling, hybrid dynamic biasing,
low-dropout regulator, transient response, voltage spike. detected effectively because the differential common-gate amplifier
has limited bandwidth. This approach is also not suitable for low
output voltages.
I. I NTRODUCTION
Another method is to raise the bias current based on the signifi-
Nowadays, on-chip power management units have been exten- cance of the output current [12], [13]. For circuits to react to a change
sively developed, implying there are multiple power domains in in the output voltage quickly, an adaptive bias current should maintain
the system-on-chip (SoC) design. The power management system a minimum value in the steady state.
scales down the supply voltage by low-dropout (LDO) to power In this brief, an LDO with hybrid dynamic biasing is proposed
many circuit blocks. Transient response time is an important dynamic to improve the output voltage transient speed under abrupt changes
specification in LDO designs because the voltage spike affects the of the output current. Through capacitive coupling, the fast transient
overall performance. For the LDO loop bandwidth, it is necessary circuit senses transient changes in voltage at the LDO output and
to control the locations of the loop’s poles and zeros in small- instantly increases the bias current. The quiescent current is only
signal analysis [1]–[3]. Increasing the loop bandwidth can improve 25 μA.
small-signal performance at low and moderate frequencies. If the The rest of this brief is organized as follows. Section II presents
design focuses on the large-signal behavior, typical approaches are the LDO architecture and operation principle of the proposed fast
to increase the bias current to achieve a high slew rate, or to use transient circuit through hybrid dynamic biasing. Section III shows
large capacitors to reduce the undershoot and overshoot of the output experimental results. The final section addresses the conclusion of
this brief.
Manuscript received November 22, 2011; revised July 6, 2012; accepted
August 31, 2012. Date of publication October 9, 2012; date of current version
August 2, 2013. This work was supported in part by the National Science II. LDO A RCHITECTURE
Council and National Chip Implementation Center.
The authors are with the Institute of Communications Engineering,
A. LDO Architecture Without the Output Capacitor
National Chiao Tung University, Hsinchu 300, Taiwan (e-mail: jeremy. Fig. 1 shows an LDO structure without the output capacitor [10].
cm97g@g2.nctu.edu.tw; twtsai.cm96g@g2.nctu.edu.tw; cchung@mail.nctu. Fig. 2 illustrates the large-signal responses of this structure. In
edu.tw).
Fig. 2(a), when the output voltage (VOUT ) suddenly drops, it instantly
Color versions of one or more of the figures in this paper are available
online at http://ieeexplore.ieee.org. decreases the VSG of transistor M1 and turns it off. To provide the
Digital Object Identifier 10.1109/TVLSI.2012.2217766 same bias current (IBIAS ), CPAR_IN itself releases the current. In this
1063-8210/$31.00 © 2012 IEEE

Authorized licensed use limited to: Viettel Group. Downloaded on November 26,2020 at 12:05:44 UTC from IEEE Xplore. Restrictions apply.
IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS, VOL. 21, NO. 9, SEPTEMBER 2013 1743

Fig. 2. Large-signal responses of the LDO structure without an output

capacitor. (a) Undershoot. (b) Overshoot.
Fig. 4. Operation of the proposed circuit (undershoot).

Fig. 3. LDO structure with the proposed fast transient circuit through hybrid
dynamic biasing.
Fig. 5. Operation of the proposed circuit (overshoot).
way, the current flowing through transistor MP increases when the
VSG of transistor MP increases. This current pulls VOUT back to the
of undershoot and overshoot, respectively. The voltage gain of the
original voltage. Fig. 2(b) shows that, when VOUT rises suddenly, it
two op amps is A v = −gm1 (ro1 //ro3 ). The gain of the proposed
increases the drain voltage of transistor M1 and the source voltage of
circuit is larger than that of the circuit in [8], enabling it to amplify
transistor M2 . Thus, a decrease in the VGS of transistor M2 turns off
the detected transient signals more efficiently to enhance the transient
transistor M2 . As a result, all current flowing through transistor M4 is
driving capabilities and slew rates of transistors M4 and M3 . Thus,
charged to CPAR_IN . This phenomenon increases the gate voltage of
the gate charge of power transistor M P can be promptly sourced or
transistor MP and decreases the VSG of transistor MP. This effectively
sunk, i.e., the power transistor can respond efficiently. Each op amp
reduces the current through the transistor MP. To maintain the same
consumes only 3.5 μA.
IBIAS , VOUT is pulled down to keep the same IBIAS current, thereby
In addition to the capacitive coupling circuit, we also propose a
returning to the original voltage. The power transistor has a large size
dynamic bias circuit. The dynamic bias circuit can speed up the
and generates a large parasitic gate capacitance. Owing to the large
discharge of transistor M2 according to the transient output of the
parasitic capacitance and the high impedance at this node, the gate of
capacitive coupling circuit, thereby reducing the response time of
the power transistor forms a dominant pole. The other nodes are all of
the power transistor. In contrast, the circuit in [8] uses a fixed
low impedance. Therefore, in the negative feedback loop, there only
bias voltage, which limits the response time of the power transistor,
appears one pole within loop bandwidth, so the LDO does not require
resulting in a larger variation of the output voltage unless a larger
an output capacitor, which is therefore suitable for SoC applications.
bias current has been used. The inclusion of the dynamic bias circuit
enables the power transistor to respond quickly to an abrupt increase
B. Structure and Operation Principles of the Proposed Fast Transient in load, thereby reducing the variation of the output voltage and
Circuit expediting the recovery of output voltage. The detailed operation of
Fig. 3 illustrates the proposed architecture. The most critical feature the dynamic bias circuit is given in Section II-D.
of the structure is the dynamic enhancement of the slew rate. When Fig. 4 shows that, when VOUT suddenly drops, the capacitive
the output voltage changes dramatically, the bias current immediately coupling of VOUT causes the gate voltage of transistors M B1 and
changes to improve the slew rate and reduce the LDO undershoot MT 1 to drop. This, in turn, increases the output voltage of two
and overshoot. Figs. 4 and 5 analyze the large-signal performance differential amplifiers, decreasing the VSG of transistor M4 and

Authorized licensed use limited to: Viettel Group. Downloaded on November 26,2020 at 12:05:44 UTC from IEEE Xplore. Restrictions apply.
1744 IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS, VOL. 21, NO. 9, SEPTEMBER 2013

Fig. 6. Bias generation circuit.

Fig. 8. Dynamic bias circuit.

ensuring that VSG(ML6) = VSG(M1) . Therefore, the output voltage

VOUT = V1 = VREF . Meanwhile, the bias current is designed as
IML7 = IML6 = I M1 by selecting the size of transistor M3 to be
twice that of M L7 .

D. Proposed Dynamic Bias Circuit

The design principle of the dynamic bias circuit is to make VDYN
change with VOP , as shown in Fig. 8. The primary purpose of the
dynamic bias circuit is to momentarily change the bias current of
the feedback loop of the main circuit when voltage spikes appear
at the LDO output in order to quickly charge or discharge gate
Fig. 7. Linking voltage generation circuit. parasitic capacitance (CPAR_IN ) of the power transistor. A sudden
drop in VOUT increases VOP , which decreases the drain voltage of
increasing the VGS of transistor M3 . The current flowing through transistor M D4 . A decrease in the drain and gate voltage of transistor
transistor M3 becomes higher. As the VSG of transistor M4 decreases, M D3 decreases the gate voltage of transistor MD2 . Because the VSG
the current flowing through transistor M4 decreases. This instantly of transistor M D2 is larger, the current flowing through it becomes
removes current from CPAR_IN , causing the gate voltage of transistor larger as well, which causes VDYN to increase instantly. A drop in
M P to drop quickly. When the VSG of transistor M P increases, it VOUT causes an increase in VDYN . A sudden drop at the gate of
increases the current flowing through transistor M P . This, in turn, power transistor (M P ) increases the VSG of the power transistor as
charges the output parasitic capacitance (CPAR_OUT ) and pulls VOUT well as the current flowing through it. This enables a more rapid
back to the original steady state. In Fig. 5, when VOUT suddenly pull-up of VOUT , returning it to a steady voltage. The addition of
rises, the capacitive coupling of VOUT causes the gate voltage of the dynamic bias circuit makes the whole circuit respond even faster
transistors M B1 and MT 1 to rise. This decreases the output voltage with better performance.
of two differential amplifiers, increasing the VSG of transistor M4
and decreasing the VGS of transistor M3 . In this case, the current E. Enhancement of Transient Responses
flowing through transistor M3 decreases, and the current flowing In Fig. 3, the high-pass network comprises resistor RT (R B ) and
through transistor M4 increases. Thus, some current flowing through capacitor C T (C B ). The values of both C T and C B are 2 pF and the
transistor M4 charges CPAR_IN , which increases the gate voltage of
values of both RT and R B are 400 k. Thus, the corner frequency of
transistor MP. In this way, the VSG of transistor MP decreases, which the high-pass network is 199 kHz. When the load current of the LDO
decreases the current flowing through transistor MP. Thus, CPAR_OUT regulator is 100 mA, the crossover frequency of the main feedback
discharges, making VOUT to pull down and return to the original
loop is 500 kHz. The corner frequency of the high-pass network
steady voltage. In order to reduce the overshoot, increasing the gate must be designed to be less than the crossover frequency of the LDO
voltage of the power transistor M P is more effective than discharging feedback loop. VOUT needs to vary at least 5 mV within 5 μs, so the
LDO output by transistor M1 .
fast transient circuit and the dynamic bias circuit can be efficiently
The bias generation circuit for VIP and VIN of Figs. 4 and 5 is triggered to respond to and reduce the output spikes.
shown in Fig. 6. The op amps in the proposed LDO regulator require Fig. 9 shows the measurement results of the load transient
additional bias voltages (VIP and VIN ), while the circuit of [8] also
responses when VDD = 1.3 V, VOUT = 1.1 V, and IOUT =
requires two additional bias voltages. 1−100 mA. There are three parts in Fig. 9. The top one is the
load transient response of the LDO with the proposed circuit, and
C. Proposed Linking Voltage Generation Circuit (LVGC) the middle one is that of the LDO without the proposed circuit.
Fig. 7 shows that VREF locking V1 makes V1 = VREF by The bottom one shows that IOUT changes between 1 and 100 mA.
connecting op amp in the unity-gain feedback configuration. The op Both the rise and fall time of the load current range from 1 to
amp provides one stage of high gain and one stage of low gain. 100 mA is 200 ns. The proposed dynamic hybrid biasing improves
The closed-loop gain is A f ≈ gmL1 (roL4 //roL2 ) (2gmL5 /gmL6 ) = the undershoot of the output voltage from 480 to 117 mV, while
46 dB. The gain, which is larger than that of [8], is sufficient to the recovery time is improved from 6 to 1.4 μs. The overshoot is
force V1 to nearly equal VREF . The LVGC is designed to make improved from 173 to 28 mV. The proposed approach effectively
the currents flowing through transistor M L6 and M1 to be the extends the bandwidth of the feedback loop, and ensures high-speed
same. The size of transistor M L6 equals the size of transistor M1 , transient response to signal change.

Authorized licensed use limited to: Viettel Group. Downloaded on November 26,2020 at 12:05:44 UTC from IEEE Xplore. Restrictions apply.
IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS, VOL. 21, NO. 9, SEPTEMBER 2013 1745

Fig. 11. Input–output characteristics of the regulated voltage.

Fig. 9. Comparison of two LDO structures with and without the proposed
fast transient circuit, at VDD = 1.3 V, VOUT = 1.1 V, IOUT(MAX) =
100 mA, IOUT(MIN) = 1 mA.

Fig. 12. Line transient measurement result of the proposed LDO voltage
regulator without an off-chip output capacitor.

Fig. 10. Die photograph of the proposed LDO voltage regulator.

Fig. 13. Load transient measurement result of the proposed LDO voltage
III. E XPERIMENTAL R ESULTS regulator without an off-chip output capacitor.
The proposed LDO regulator was fabricated using the 0.35-μm 100 mA at 1.3 V supply voltage, while the rise time and fall time
mixed-signal CMOS 2P4M process. The design of our regulator of the load current are 5 ns/mA. These measurement results show
uses only 3.3 V MOS transistors; therefore, the maximum operation that the load transient voltage spike is only 80 mV.
voltage is 3.3 V. Fig. 10 shows the die photograph of the The quiescent current of 25 μA was measured with a load current
prototype voltage regulator. Fig. 11 shows the input–output voltage IOUT = 100 mA. All bias current flows into the ground; therefore,
characteristics of LDO regulator at IOUT = 100 mA, the dropout we simply measure the current flowing into the ground pin to obtain
region, and line regulation performance. The size of the power the quiescent current. The current efficiency was obtained from (1).
transistor is 26 000 μm/0.35 μm to provide high output current. Fig. 14 shows the current efficiency as a function of load current
The dropout voltage is 180 mV. Fig. 12 shows the measured line
IOUT 100 mA
transient response. The supply voltage switches between 1.3 and ηI = = = 99.97%. (1)
2.3 V with 100 mA output current, and voltage spike is 20 mV. IGND + IOUT 25 μA + 100 mA
Fig. 13 shows the measured load transient response without an Performance comparison between some previously reported LDOs
off-chip output capacitor. The output current varies from 0 to and the proposed LDO is summarized in Table I. The figure of merit

Authorized licensed use limited to: Viettel Group. Downloaded on November 26,2020 at 12:05:44 UTC from IEEE Xplore. Restrictions apply.
1746 IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS, VOL. 21, NO. 9, SEPTEMBER 2013

TABLE I
P ERFORMANCE C OMPARISON W ITH P REVIOUSLY R EPORTED LDOs

[2] [4] [8] [10] This Brief

Technology (μm) 0.5 0.35 0.35 0.09 0.35
Supply Voltage (V) 1.4–4.2 2.0 0.95–1.4 1.2 1.28–3.3
IOUT,MAX (mA) 100 200 100 100 100
VOUT (V) 1.21 1.8 1.2 0.9 1.1
Iq 45 μA 20 μA 43 μA 6000 μA 25 μA
Vdropout (V) 0.2 0.2 0.2 0.3 0.18
120 54 70 90 80
VOUT (mV)
(IOUT = 100 mA) IOUT = 200 mA (IOUT = 99 mA) (IOUT = 100 mA) (IOUT = 100 mA)
Current efficiency 99.95% 98.8% 99.95% 94.3% 99.97%
Current Capacitor 100 nF 1 μF 0–100 pF 600 pF 0–100 pF
FOM1 (ps) 59 27 0.03 32 0.02
TR(measure) (μ s) 2.5 15.4 3 0.00054 0.75
FOM2 (ns) 1.125 1.54 1.29 0.032 0.187
Active area 0.263 mm2 0.264 mm2 0.155 mm2 0.098 mm2 0.126 mm2

biasing. The dynamic biasing in the proposed fast transient circuit

is activated through capacitive coupling. The fast transient through
hybrid dynamic biasing circuit senses the LDO output change so as
to increase the bias current instantly. The output voltage spike of the
LDO with the proposed circuit decreases to 80 mV when the output
current changes from 0 to 100 mA and 20 mV when a supply voltage
of 1 V input step is applied to the circuit.
The proposed LDO regulator is stable for output current in the
complete range of 0–100 mA and does not require any off-chip output
capacitor. The proposed circuit improves both the overshoot and the
undershoot of the LDO regulator. The FOM of this LDO compares
favorably with that of other published designs.

R EFERENCES
Fig. 14. Current efficiency as a function of load current.
[1] G. A. Rincon-Mora, “Active capacitor multiplier in Miller-compensated
circuits,” IEEE J. Solid-State Circuits, vol. 35, no. 1, pp. 26–32, Jan.
2000.
(FOM), given in (2) [10], is adopted in Table I [2] A. Garimella, M. W. Rashid, and P. M. Furth, “Reverse nested miller
Iq COUT · VOUT Iq compensation using current buffers in a three-stage LDO,” IEEE Trans.
FOM1 = TR = . (2) Circuits Syst. II, Exp. Briefs, vol. 57, no. 4, pp. 250–254, Apr.
IOUT,MAX IOUT,MAX IOUT,MAX
2010.
To show an FOM directly obtained from the measurement data, a [3] Y.-H. Lin, K.-L. Zheng, and K.-H. Chen, “Smooth pole tracking tech-
measured response time (TR(measure) ) from load transient responses nique by power MOSFET array in low-dropout regulators,” IEEE Trans.
is taken into account. Another FOM is defined as Power Electron., vol. 23, no. 5, pp. 2421–2427, Sep. 2008.
[4] M. Al-Shyoukh, H. Lee, and R. Perez, “A transient-enhanced low-
Iq
F O M2 = TR(measure) . (3) quiescent current low-dropout regulator with buffer impedance atten-
IOUT,MAX uation,” IEEE J. Solid-State Circuits, vol. 42, no. 8, pp. 1732–1742,
Although our FOM2 is larger than that of [10], the latter actually Aug. 2007.
[5] C. K. Chava and J. Silva-Martinez, “A frequency compensation scheme
has an on-chip output capacitance of 600 pF, which has effectively for LDO voltage regulators,” IEEE Trans. Circuits Syst. I, Reg. Papers,
reduced the measured response time. Therefore, to compare the vol. 51, no. 6, pp. 1041–1050, Jun. 2004.
performance with [10], FOM1 seems to be a fair index. In addition, [6] Y.-H. Lee and K.-H. Chen, “A 65 nm sub-1 V multi-stage low-dropout
our measurement condition for the load transient response ranges (LDO) regulator design for SoC systems,” in Proc. IEEE Int. Midwest
from 0 to 100 mA, while the measurement condition in [8] ranges Symp. Circuits Syst. Conf., Aug. 2010, pp. 584–587.
[7] R. J. Milliken, J. Silva-Martinez, and E. Sanchez-Sinencio, “Full on-
from 1 to 100 mA. The output impedance changes abruptly for load chip CMOS low-dropout voltage regulator,” IEEE Trans. Circuits Syst.
currents ranging from 0 to 100 mA; however, the output impedance I, Reg. Papers, vol. 54, no. 9, pp. 1879–1890, Sep. 2007.
does not change a great deal for load currents ranging from 1 to [8] P. Y. Or and K. N. Leung, “An output-capacitorless low-dropout regulator
100 mA. In other words, the measurement conditions for load with direct voltage-spike detection,” IEEE J. Solid-State Circuits, vol. 45,
transient response are far stricter in this case than in [8]. Therefore, no. 2, pp. 458–466, Feb. 2010.
[9] C.-M. Chen and C.-C. Hung, “A capacitor-free CMOS low-dropout
the proposed LDO regulator is superior both in static and transient voltage regulator,” in Proc. IEEE Int. Symp. Circuits Syst. Conf., May
characteristics to the LDO regulator in [8]. By using 0.35-μm CMOS 2009, pp. 2525–2528.
technology, the chip area of the proposed design is smaller than that [10] P. Hazucha, T. Karnik, B. A. Bradley, C. Parsons, D. Finan, and S.
in both [4] and [8]. Borkar, “Area-efficient linear regulator with ultrafast load regulation,”
IEEE J. Solid-State Circuits, vol. 40, no. 4, pp. 933–940, Apr. 2005.
IV. C ONCLUSION [11] T. Y. Man, P. K. T. Mok, and M. Chan, “A high slew-rate push-pull
output amplifier for low-quiescent current low-dropout regulators with
This brief presented an LDO voltage regulator without the output transient-response improvement,” IEEE Trans. Circuits Syst. II, Exp.
capacitor that achieves fast transient responses by hybrid dynamic Briefs, vol. 54, no. 9, pp. 755–759, Sep. 2007.

Authorized licensed use limited to: Viettel Group. Downloaded on November 26,2020 at 12:05:44 UTC from IEEE Xplore. Restrictions apply.
IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS, VOL. 21, NO. 9, SEPTEMBER 2013 1747

[12] G. A. Rincon-Mora and P. E. Allen, “A low-voltage, low quiescent maximum current charging or hysteretic control [2]–[4]. Moreover,
current, low drop-out regulator,” IEEE J. Solid-State Circuits, vol. 33, voltage accuracy over full load current and voltage scaling range is
no. 1, pp. 36–44, Jan. 1998. an important specification, because smaller design margin is allowed,
[13] W.-J. Huang, S.-H. Lu, and S.-I. Liu, “A capacitor-free CMOS low
dropout regulator with slew rate enhancement,” in Proc. Int. Symp. VLSI leading to further power saving while eliminating any slack periods
Design, Autom. Test, Apr. 2006, pp. 1–4. caused by egregious low power supply. Accurate output needs high
gain error amplifier (EA) and power devices with low resistance.
The type-III compensator is often implemented in buck converter
for high loop gain, but large off-chip capacitors and resistors limit
Digital Error Corrector for Phase Lead-Compensated its implementation in integrated power converters. Though recent
Buck Converter in DVS Applications advances in research are successful for monolithically integrate
Shaowei Zhen, Xiaohui Zhu, Ping Luo, Yajuan He, and Bo Zhang type-III compensator by pseudotype-III compensation [5] or extend-
ing loop bandwidth [6], the passive components still occupy large area
to generate low-frequency pole, or the loop bandwidth is limited [6].
In contrast, the phase lead compensator (PLC) stabilizes buck con-
Abstract— Modern low-power system on a chip needs direct current
converter with dynamic voltage scaling (DVS) ability for core power verter by only one high-frequency zero, so the area is tremendously
supply. The converter output should be accurate voltage across the full reduced with comparable bandwidth with type-III compensation [7].
load current and voltage scaling range. An integrated buck converter However, the primary drawback of the PLC is that the loop gain is
for DVS application is proposed in this brief. Voltage mode phase severely curtailed. Thus, its application in DVFS systems is limited.
lead compensation is implemented in the converter, with much smaller
This brief details the design of a novel error correction method
passive components than conventional type-III compensation. To improve
accuracy, the output voltage error accompanied with load current presented in [8]. The digital error corrector (DEC) is implemented in
and reference voltage caused by finite loop gain in analog control a phase lead-compensated buck converter. Extra digitally controlled
loop is corrected by the digital error corrector. The output voltage is offset voltage is introduced to cancel output error because of low loop
compared by two comparators whose threshold voltage is about 10 mV gain and parasitical resistors. This brief is organized as follows. In
above and below the reference voltage, respectively. The duty cycle is
slightly adjusted by finite state machine according to outputs of the Section II, the error correction scheme is proposed and the detailed
two comparators. Experimental results show that the converter is well circuit implementation is introduced. Section III shows and discusses
regulated over an output range of 0.7–1.8 V, with step voltage of 25 mV. experimental performance, and Section IV summarizes this brief.
When load current suddenly changes between 170 and 500 mA, the
overshoot and undershoot voltage are 32 and 50 mV, respectively. Load
regulation is maintained about 1% throughout the full load range. The II. I MPLEMENTATION OF B UCK C ONVERTER W ITH DEC
voltage error is within ±10 mV in the voltage scaling range.
Index Terms— Buck converter, digital error corrector, phase lead The simplified block diagram of the proposed buck converter
compensation, voltage mode control. with the proposed DEC is illustrated in Fig. 1. Output voltage
VOUT is fed back to the PLC, and the operational transconductance
I. I NTRODUCTION amplifier (OTA) GM converts voltage error between VREF and VC
into differential current in R1 and R2, respectively. The differential
Low-power design techniques have become increasingly important current is compared with sawtooth current ISAW by comparator
for modern system on chips (SoCs). The dynamic voltage and Comp to generate pulse-width modulation (PWM) signal. ISAW and
frequency scaling (DVFS) technique controls the supply voltage and global clock signal CLK are provided by OSC. Power devices MP
operation frequency of each module in SoC in response to workload and MN are controlled and driven by RS latch and driver. There are
demands, leading to substantial power saving while maintaining two comparators designed accompanied with GM whose outputs are
system performance. Direct current (dc–dc) converter with dynamic Comp_H and Comp_L, respectively. The threshold voltages to trigger
voltage scaling (DVS) ability acts as a hardware platform in a Comp_H and Comp_L are defined as VOUT, MAX and VOUT, MIN ,
typical DVFS system. It is one of the hot topics in current research respectively. The proposed DEC introduces digitally controlled cur-
[1]–[4]. Compared to traditional dc-dc converters, the converter in rent source at node V1 to adjust duty cycle slightly according to
the DVFS system should have several extra characteristics [1], [2]. Comp_H and Comp_L, until VOUT is between VOUT, MAX and
Efforts have been made to achieve fast voltage scaling response, by VOUT, MIN . Then there is digitally controlled input offset voltage of
EA introduced by DEC. The original output voltage error due to low
Manuscript received January 24, 2012; revised August 7, 2012; accepted
August 31, 2012. Date of publication October 9, 2012; date of current version loop gain is compensated by the offset voltage. Thus the regulation
August 2, 2013. This work was supported in part by the National S&T and output accuracy are enhanced.
Special Project of China under Grant 2009ZX01031-003-003, the Fundamen-
tal Research Funds for the Central Universities under Grant ZYGX2009J026,
and the NLAIC Project under Grant 9140C0903091004.
A. Analog Control Loop
S. Zhen and P. Luo are with the State Key Laboratory of Electronic
Thin Films and Integrated Devices, Chengdu 610054, China (e-mail: The schematic of control blocks in Fig. 1, such as PLC, GM
swzhen@uestc.edu.cn; pingl@uestc.edu.cn). comparators, and ISAW generation, is shown in Fig. 2. PLC is realized
X. Zhu was with the University of Electronic Science and Technology
of China, Chengdu 610054, China. He is now with Texas Instruments
by operational amplifier OP, resistors RC1 , RC2 , and capacitor CC .
Semiconductor Technologies Company, Ltd., Shanghai 200030, China (e-mail: GM is designed on the basis of symmetrical OTA. Voltage error
326465632@qq.com). between VC and VREF is converted into current error in R1 and R2 .
Y. He and B. Zhang are with the University of Electronic Science and ISAW generated by ISAW generation block flows out from node V2
Technology of China, Chengdu 610054, China (e-mail: yjhe@uestc.edu.cn; and output current of DEC flows from node V1 . The two comparators
zhangbo@uestc.edu.cn).
are current comparators, and IB1 and IB2 are designed to make
Color versions of one or more of the figures in this paper are available
online at http://ieeexplore.ieee.org. VOUT, MAX about 10 mV higher than VREF and VOUT, MIN about
Digital Object Identifier 10.1109/TVLSI.2012.2217513 10 mV lower.
1063-8210/$31.00 © 2012 IEEE

Authorized licensed use limited to: Viettel Group. Downloaded on November 26,2020 at 12:05:44 UTC from IEEE Xplore. Restrictions apply.