2015 International Conference on Advances in Computer Engineering and Applications (ICACEA)

IMS Engineering College, Ghaziabad, India

Performance, Analysis and Comparison of Digital

Adders
Jasmine Saini Somya Agarwal, Aditi Kansal
E.C.E Professor B.Tech E.C.E Students
JIIT ,Noida JIIT, Noida

Abstract -- This paper primarily discusses the construction of Ripple Carry Adder (RCA), since the carry signal
different high speed adders using very high speed integrated propagates from the least significant bit position to the most
circuit hardware design in the platform Modelsim 5.5c. The significant one. First full adder do not have any carry input so
reason for this investigation is that adders are the most important it can be replaced with a half adder or a full adder with ‘0’ as
circuits requiring improved designs in order to obtain maximum
carry input.
gain possible. In any digital system adders are the most
fundamental unit. Addition is an indispensible operation in any
Digital, Analog, or Control system. They are not only as
arithmetic logic unit in computers and some processors but used
in some other kind of processors too, where they are used to
calculate addresses, table indices, and similar operations [6].
Today technology in measured by its ability to measure
computational algorithms. This paper discusses the drawbacks
and gains of ripple carry, carry look ahead, carry select and
kogges stone in terms of area, speed, delay. This paper focuses on
implementation and simulation of 64 bit full adder using very high
speed integrated circuit hardware description language(VHDL).

Index terms --Adder, VHDL, delay Fig. 1.1 Ripple Carry Adder

The most serious drawback of this adder is that the delay

I. INTRODUCTION increases linearly with the bit length as each full adder has to
wait for the carry out of the previous stage to output steady-
Addition is the most basic operation of any digital system. state result. They are preferred where less area is required as
An effective functioning of adders holds a role of major less hardware implementation is required. But they are slow in
importance in the architecture of more complex structures such terms of speed as each Full Adder has to wait for carry bit from
as arithmetic logic units of microprocessors. Arithmetic previous adder.
calculations are covered under logical levels while the area and
other factors are covered under circuit levels. In the next B. Carry look ahead adder
sections different architectures of different adders are discussed
with the preference to area, number of components and speed This is a comparatively fast method of adding numbers than
of each device. ripple carry adder as the carry signal need not to wait stage by
stage but it calculates carry bits before the sum, which reduces
II. TYPE OF ADDERS the delay time to calculate the result of the larger value bits.
Figure 1.2 shows a carry look ahead of 4-bits in which all the
A. Ripple Carry Adder 1-bit add their results. To reduce the delay time from ripple
adder which position will propagate a carry if one comes in
The ripple carry adder is constructed by joining full adders
from the right is known which further helps to know which
(FA) blocks in series. To add a number of N bits, N blocks of
group will propagate carry if one comes in from right [9]. The
full adder has to be implemented, connecting output carry of
time delay is saved as the propagation of carry bit wise is now
each adder to the carry input of subsequent adder. Figure 1.1
propagated group wise. The carry which had to propagate all
shows block diagram of 4-bit ripple carry adder. To add a 4-bit
along each 1-bit adder in Ripple Carry Adder is known to the
number, four full adders are cascaded. Each full adder is taking
next group of four 1-bit adders faster when propagated through
(Xi Yi) as input and the sum and a carry is obtained as output.
a group.
The output carry Ci of first full adder is connected as the carry
input to next full adder. This kind of architecture is called a
978-1-4673-6911-4/15/$31.00©2015 IEEE

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 2015 International Conference on Advances in Computer Engineering and Applications (ICACEA)
IMS Engineering College, Ghaziabad, India

Because of the simulation technique to enhance the speed the

required area of this adder is particularly doubled with respect
to RCA.

D. Kogges stone

The Kogge stone adder is a parallel prefix form of carry

look ahead adder. The architecture of this adder is explained in
figure 1.4 to add 4-bits.

Fig. 1.2 Carry Look Ahead Adder

This fast calculation is allowed at the expense of more

hardware .The hardware becomes complex with the increasing
bit size thereby decreasing the speed. The CLA has the fastest
growing area with respect to the bit size

C. Carry select adder

The main idea to save delay in carry select is to calculate all

the bits and thus choosing only the correct one to obtain the
result. In carry-select adders both sum and carry bits are Fig.1.4 Kogge Stone Adder
calculated for the two alternatives: input carry ‘0’ and ‘1’.
Once the carry-in is delivered, the correct calculated result is Each block generates a PG (Propagation Generation) block.
chosen using a multiplexer to produce the desired output. P bit is computed by XOR the two bits and G bit is obtained by
Hence the time is saved for the calculation of the sum it is AND operation. The last stage are the carry bits and these are
simply chosen once the carry in gets in. XOR’d with the propagate bits of PG block of first level to
Figure 1.3 shows a carry select adder of 4-bits in which obtain sum bits [1].
every bit (Ai, Bi) is added one with carry in as ‘0’ and other as This adder generates carry bit fast at the cost of area and is
carry in’1’.When the carry out is known for first adder known as the fastest adder algorithm possible till far.
accordingly all the multiplexer chose the results and Si is given
as output. First block need only one full adder as carry-in is
known. III. COMPARISON

The results observed by simulating these adders and

studying them on aspects of delay, components and area are
contrasted in tables as:-
Delay is computed with the help of code, used to simulate
these adders. Table I gives the delay of 64 bit adders

TABLE I . DELAY (ns)

ADDER DELAY(ns)

Ripple-Carry 47.06
Carry-Look-Ahead 21.7
Carry-Select 14.76
Kogge-Stone 11.37
Fig. 1.3 Carry Select Adder

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 2015 International Conference on Advances in Computer Engineering and Applications (ICACEA)
IMS Engineering College, Ghaziabad, India

With the implementation of new algorithms of adders delay is

decreased subsequently from Ripple adder to Kogge Stone
adder. No of components are calculated taking into account all
the operators and devices required to calculate sum and carry
bits. Table II gives the number of components required for the
architecture of 64 bit adders.

TABLE II . NUMBER OF COMPONENTS Fig. 1.5 Simulation of Ripple Carry Adder

ADDER AND OR XOR MUX BUFFER

Ripple- 128 64 128 0 0

Carry
Fig. 1.6 Simulation of Carry Look Ahead Adder

Carry- 176 80 0 0 0
Look-
Ahead
Carry- 256 127 256 63 0
Select

Kogge- 336 136 128 0 56 Fig. 1.7 Simulation of Carry Select Adder
Stone

Area is increased with the increase in number of components.

So a similar pattern in area can be estimated.

IV. RESULTS AND SIMULATIONS

Figure 1.5 shows simulations of Ripple Carry Adder. The Fig. 1.8 Simulation of Kogge Stone Adder
first two rows are the input numbers of 64 bit. The third row
shows the sum bits. In fourth row Cin is given as ‘0’. Fifth row
shows the Carry out output. Subsequent rows show the V. CONCLUSIONS
intermediate carry bits.
Figure 1.6 shows simulations of Carry Look Ahead which New and fast algorithms are implemented at the cost of one
proves results of sum and carry out. The input of the two 64 bit or the other factors Ripple carry is the most basic adder made
numbers is given in the first two rows and sum is obtained in just by joining adders with no exercise on speed or hardware.
the third row. Carry in was given as ‘0’ while carry out was As the speed increases in carry look its hardware becomes
obtained as ‘1’. complex which would play a unfavourable role in addition of
Figure 1.7 is of the simulation results of Carry Select Adder large bits. Carry select adder almost doubles its components
with two 64 bit numbers and Cin input and sum and Cout as and adds up the multiplexer’s too. The most efficient way to
output. add n bits numbers is by the use of Kogge Stone adder in
Figure 1.8 is the simulation of Kogge Stone Adder with which the number is added bit by bit from LSB to MSB. The
first two rows as the input of 64 bit numbers, then the third row carry generated by each stage is used by higher stage so it
with intermediate carry bits. Fourth and fifth row shows Carry reduces it hardware as it is not proportional on the number of
out and Carry in respectively while last result is of sum bits. bits [3]. Kogge stone adder has the best concept compared to
these adders and finds a way out to perform better taking
aspects of speed and area into account.

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 2015 International Conference on Advances in Computer Engineering and Applications (ICACEA)
IMS Engineering College, Ghaziabad, India

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