Two marks

1. Differentiate between Computer Organization and Computer Architecture

Computer Organisation Computer Architecture

1. It refers to the operational units and their ecture refers to those attributes that have
interconnections direct impact on the logical execution of a
program
2. Organization attributes include hardware details 2. Architecture attributes include the
transparent to programmers such as control signal, instruction sets, IO mechanism techniques
interface between computer and peripherals and the for addressing memory and number of bits
memory used to represent various data types
technology used

3. Example: Suppose if there is a multiply 3. Example: It is a architectural design

instruction (MUL A,#5),then organization issue is issue whether a computer will have a
whether to implement special multiply unit or multiply instruction
implement mechanism that makes
repeated use of add unit of the system

2. What is stored program concept in digital computer

Since the task of entering and altering programs for ENIAC was extremely tedious a
machine with stored program concept was made. This is called Von Neumann machine or
IAS computer. Here for processing a program, the program could be stored in memory
alongside the data. Now the computer could get its instruction by reading them from
memory. The design of a new stored program computer, referred to as the IAS computer.
3. Draw flowchart for booths algorithm for two complement multiplication

4. Represent (127.125)10 in single and double precision IEEE 754 standards for
Floating Point number representation.

(127)​10 =(01111111)​
​ 2

(​.​125)​10​ =(.001)​2
​

(127.125)​10​=(01111111.001)​2
Normalization:1.111111*2​6
Single precision
Biasing:6+127=133
Double precision
Biasing:6+1023=1029
The format is:

I)SINGLE PRECISION

Sign Exponent Significant

(1bit) (8bits) (23bits)
0 10000101 11111100100000000000000

II)DOUBLE PRECISION

Sign Exponent Significant

(1bit) (11bits) (23bits)
0 10000000101 11111100100000000000000...

5.List the memory hierarchy

Hierarchy List
1. Registers
2. L1 Cache
3. L2 Cache
4. Main memory
5. Disk cache
6. Disk
7. Optical
8. Tape

6.List any two difference between static and dynamic RAM

SRAM versus DRAM

Both volatile
Power needed to preserve data

Static RAM
Uses flip flop to store information
Needs more space
Faster, digital device
 Expensive, big in size
Don't require refreshing circuit
Used in cache memory

Dynamic RAM

Uses capacitor to store information

More dense i.e. more cells can be accommodated per unit area
Slower, analog device
Less expensive, small in size o Needs refreshing circuit
Used in main memory, larger memory units

5. Define locality of reference

The reference to memory at any given interval of time tends to be confined within
a few localized area of memory. This property is called locality of reference. This is
possible because the program loops and subroutine calls are encountered frequently.
When program loop is executed, the CPU will execute same portion of program
repeatedly. Similarly, when a subroutine is called, the CPU fetched starting address of
subroutine and executes the subroutine program. Thus loops and subroutine localize
reference to memory.
.
6. List the difference between spatial and temporal locality.

Spatial Locality

It refers to the tendency of execution to involve a number of memory locations

that are clustered.

It reflects tendency of a program to access data locations sequentially, such as

when processing a table of data.

Temporal Locality

It refers to the tendency for a processor to access memory locations that have been
used frequently. For e.g. Iteration loops executes same set of instructions
repeatedly.
 7. What is write through

All write operations are made to main memory as well as to cache, so main memory is
always valid

Disadvantage
Other CPU’s monitor traffic to main memory to update their caches when needed
This generates substantial memory traffic and may create a bottleneck
Anytime a word in cache is changed, it is also changed in main memory
Both copies always agree
Generates lots of memory writes to main memory

Multiple CPUs can monitor main memory traffic to keep local (to CPU) cache up
to date
Lots of traffic
Slows down writes
Remember bogus write through caches!

8. What is write back

When an update occurs, an UPDATE bit associated with that slot is set, so when
the block is replaced it is written back first

Advantage
During a write, only change the contents of the cache
Update main memory only when the cache line is to be replaced

Disadvantage
Causes “cache coherency” problems -- different values for the contents of an
address are in the cache and the main memory
Complex circuitry to avoid this problem
Accesses by I/O modules must occur through the cache

Five marks
1. Explain role of different registers-like IR, PC,IBR,AC,MAR and MBR used in Von
Neumann model

a) ​Memory Buffer Register(MBR)

i) it contains data or word to be stored in memory

ii) it contains word to be sent to the I/O unit
 iii) used to receive a word from memory
iv) used to receive a word from I/O unit

b) ​Memory Address Register (MAR)

i) specifies the address in memory for the word to be ​written into t​ he memory buffer
register
ii) specifies the address in memory of the word to be ​read into ​memory buffer register

c) ​Instruction Register (IR)

Contains the 8 bit opcode instruction being executed.

d) ​Instruction Buffer Register(IBR)

Employed to temporarily hold the right hand instruction from a word in memory

e) ​Program Counter (PC)

Contains the address of the next instruction pair to be fetched from memory

Accumulator (AC) & Multiplier Quotient (MQ)

Employed to hold temporarily operands and results of ALU operations

For eg for 40 X 40 bits we get more than 40 bits .the result of

multiplying two 40 its numbers is an 80 bit number

The Most significand bits are stored in AC and Least significand number in MQ.

2. Multiply (4) and (4) using Booth's Algorithm.

3. Using Booth's Algorithm show the multiplication of 7x5.
4. Using Booth's algorithm show the multiplication of -7 *4
5. Draw flow chart of binary restoring division and use it to divide 16 by 4
6. Divide 11 by 4 using non restoring division algorithm
7. Explain IEEE 754 standards for Floating Point number representation.
8. Explain the different cache mapping techniques with neat diagram
9. Explain cache Coherency
10. Explain interleaved and associative memory with neat diagram