IEEE TRANSACTIONS ON INDUSTRY APPLICATIONS, VOL. 45, NO.

2, MARCH/APRIL 2009 843

An Efficient High-Frequency Drive Circuit for

GaN Power HFETs
Bo Wang, Member, IEEE, Naveen Tipirneni, Member, IEEE, Marco Riva, Member, IEEE,
Antonello Monti, Senior Member, IEEE, Grigory Simin, Senior Member, IEEE,
and Enrico Santi, Senior Member, IEEE

Abstract—The requirements for driving gallium nitride (GaN)

heterostructure field-effect transistors (HFETs) and the design of a
resonant drive circuit for GaN power HFET switches are discussed
in this paper. The use of wideband III-nitride (such as GaN)
devices today is limited to telecom and low-power applications.
The current lack of high-frequency high-power drivers prevents
their application in power converters. The proposed circuit is
based upon resonant switching transition techniques, by means
of an LC tag, to recover part of the power back into the voltage
source in order to reduce the power loss. This circuit also uses level
shifters to generate the zero and negative gate–source voltages
required to turn the GaN HFET on and off, and it is highly tolerant
to input-signal timing variances. The circuit reduces the overall
power consumed in the driver and thus reduces the power loss.
This is particularly important for high-frequency driver operation
to take full advantage, in terms of efficiency, of the superior Fig. 1. On-resistance comparison of HFET and SiC transistors.
switching speed of GaN devices. In this paper, the topology of
the low-power-loss high-speed drive circuit is introduced. Some over SiC or bulk AlN substrates), chemical inertness, and
simulation results and preliminary experimental measurements radiation hardness [1]. Compared with Si FETs, GaN het-
are discussed. erostructure field-effect transistors (HFETs) have lower spe-
Index Terms—Gallium nitride (GaN) heterostructure field- cific on-resistance due to the high-density 2-D electron gas
effect transistors (HFETs), high speed, resonant drive circuit. (i.e., above 1013 cm−2 ) and high electron mobility (i.e., above
1500 cm2 /V). As shown in Fig. 1, the static on-resistance
I. I NTRODUCTION of GaN HFETs is almost three orders lower than that of Si
MOSFETs, reaching as low as 3.4 mΩ · cm2 as introduced

T HE RESEARCH on wideband III-nitride semiconductor

materials (such as GaN) has been rapidly developing in
the past few years. These materials have unique properties,
in [2].
GaN HFETs can work at high temperature ranges which Si
MOSFETs cannot reach, and they also have higher breakdown
including high electron mobility, high saturation velocity, high fields than Si MOSFETs due to the large bandgap energy of
sheet-carrier concentration at heterojunction interfaces, high GaN material. The III-nitride transistors have been shown to op-
breakdown voltages, low thermal impedance (when grown erate at up to 300 ◦ C [3], with no noticeable parameter degrada-
tion, and can have high breakdown voltages (up to 1600 V) [2].
Paper IPCSD-08-056, presented at the 2006 Industry Applications Society
Furthermore, the switching speeds of GaN HFETs are expected
Annual Meeting, Tampa, FL, October 8–12, and approved for publication in to be higher than those of Si MOSFETs due to the small input
the IEEE TRANSACTIONS ON INDUSTRY APPLICATIONS by the Power Elec- capacitance (for example, the input capacitance for a 100-V
tronics Devices and Components Committee of the IEEE Industry Applications
Society. Manuscript submitted for review November 1, 2007 and released for
1-A GaN HFET device is about 2 pF, while it is 150–200 pF
publication July 9, 2008. Current version published March 18, 2009. This work for a 100-V 1-A power MOSFET). Both the low input capac-
was supported by the U.S. Office of Naval Research under Grant N00014-05- itor and the low on-resistance are important to obtain good
1-0734 and Grant N00014-07-1-0603.
B. Wang, G. Simin, and E. Santi are with the Department of Electrical
switching characteristics. When applied to power electron-
Engineering, University of South Carolina, Columbia, SC 29208 USA (e-mail: ics, the AlGaN/GaN HFETs allow for high-power switching
wangb@engr.sc.edu; simin@engr.sc.edu; santi@engr.sc.edu). with submicrosecond and nanosecond switching times. These
N. Tipirneni is with the Advanced Technology and High Voltage MOSFET
Group, Vishay Siliconix, Santa Clara, CA 95054 USA (e-mail: tipirneni.
properties make the use of III-nitride technology a promising
naveen@gmail.com). approach for high-power, high-temperature, high-speed, and
M. Riva is with the Department of Physics, Università degli Studi di Milan, high-efficiency applications. Using insulated-gate III-nitride
20133 Milan, Italy (e-mail: riva@unimi.it).
A. Monti is with the Institute for Automation of Complex Power Systems, HFETs (MOSHFETs) further increases the achievable power
E.ON Energy Research Center, RWTH Aachen University, 52056 Aachen, levels and improves high-temperature stability.
Germany (e-mail: amonti@eonerc.rwth-aachen.de). The described characteristics would be extremely useful in
Color versions of one or more of the figures in this paper are available online
at http://ieeexplore.ieee.org. industrial power-electronic application and would improve the
Digital Object Identifier 10.1109/TIA.2009.2013578 efficiency and the regulation in ac–dc and dc–dc converters.
0093-9994/$25.00 © 2009 IEEE

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844 IEEE TRANSACTIONS ON INDUSTRY APPLICATIONS, VOL. 45, NO. 2, MARCH/APRIL 2009

Fig. 3. “Totem-pole” driver schematic.

Fig. 2. Complementary emitter follower driver topology.
an easy schematic, well suited for low-frequency applications.
However, drivers for GaN HFET switches are not currently However, when the frequency increases, both the losses due to
commercially available. This is one of the factors preventing the switching operations in the auxiliary MOSFETs Q1 and Q2
their application to power converters [4]. Modified driver and the losses in the gate port of the power MOSFET become
ICs for power Si-MOSFETs can be used to drive the HFET unacceptable [13].
switches; unfortunately, most of them work at low frequencies In conventional MOSFET drivers, the consumed switching
(below 1 MHz) [5]–[8]. A few of the driver ICs can work at power depends directly on the switching frequency fs and
around 5 MHz; however, the output impedance characteristics parasitic input parameters [13]
of these drivers are not compatible with the GaN devices and
can lead to unnecessary power loss [9]–[11]. The purpose of P = QDD V DDfs = Ciss V DD2 fs (1)
this paper is to design a driver for III-nitride HFETs, which
can best exploit the characteristics of these devices and make where
available their use in power electronic circuits. Ciss input capacitance;
QDD gate charge needed to charge Ciss of the power
transistor from zero to V DD.
II. C ONSIDERATIONS FOR THE D ESIGN Equation (1) is only correct for low-frequency operations
when the cross-conduction loss for the complementary pair is
GaN HFETs have transfer characteristics similar to junction
small enough to be neglected. When the operation frequency
FETs—blocking current when the gate is driven negative and
increases, the cross-conduction loss increases and cannot be
conducting when the gate has zero voltage. Consequently, a
neglected.
negative voltage needs to be generated to turn off the device,
and zero voltage is required to turn it on. At the same time, a
drive current with a proper value needs to be provided to charge B. Basic Resonant Drive Circuit
and discharge the input capacitor of the device and support
Many techniques have been proposed for driving semicon-
high-frequency operations.
ductor devices at high frequencies of which [12]–[15] were
Designing a gate driver that will operate a GaN HFET to its
considered to present a scheme, resonant gate driving, which is
full switching performance presents major technical challenges.
most suitable for coping with the high-efficiency requirement of
When a device works at high switching frequencies, switching
HFETs. In this topology, the switching-loss reduction, critical
power loss starts to dominate the losses, resulting in a decline
in high-frequency applications, is obtained by means of reso-
of the overall efficiency of the circuit. In order to make GaN
nant transitions in an ad hoc L−C circuit that involves the input
HFETs work at high frequencies, it is critical to design a
capacitance of the switches.
drive circuit which can reduce the switching power loss of the
Fig. 4 shows the schematic for a basic resonant circuit. The
devices.
principle of the circuit operation is that the energy stored in the
capacitor is recycled and then stored back in the capacitor with
III. I NTRODUCTION OF THE R EFERENCE D RIVE C IRCUITS the opposite polarity voltage. Thus, the energy is always stored
in the capacitor; however, the “effective” capacitor voltage
A. Basic Drive Circuit for Si MOSFETs
is alternated between positive- and negative-voltage states. In
Typically, the conventional gate-drive circuit is constituted this way, a quasi-square-wave voltage can be imposed on the
by complementary devices—either a pair of emitter followers capacitor in a low-loss manner. The process described earlier
in a class B amplifier, as shown in Fig. 2, or pMOS and nMOS is achieved when an inductor and a capacitor are resonating
in a “totem-pole” configuration, as shown in Fig. 3. These together, with resonance being stopped when the capacitor
devices supply the charge needed for the input capacitance voltage is either at a maximum or minimum [14].
(Ciss ) and allow the switch to turn on and off [12], [13]. Ciss The circuit works under zero voltage and low negative
represents the equivalent input capacitance accounting for the voltage supply (VSS). It generates an output voltage from
gate–source and Miller capacitances. These approaches offer VSS_High to V_POS (where VSS_High is a high negative

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WANG et al.: EFFICIENT HIGH-FREQUENCY DRIVE CIRCUIT FOR GaN POWER HFETs 845

Fig. 4. Basic resonant drive circuit.

Fig. 6. Waveforms of the resonant driver circuit in [15].

both the voltage VGS and current iLR will increase sinusoidally,
with the following resonance period:
2π 
T = = 2π LR Ciss (2)
ω0
where ω0 is the resonance frequency.
When the gate voltage reaches V DD, the inductor current
reaches its peak at Ipeak = V DD/Z 0 (where Z0 is the L−C
characteristic impedance Z0 = LR /Ciss . The rise time is
tr = t2 − t1 = T /4.
When the voltage across Ciss reaches the value slightly
higher than V DD at t2 , the diode DDR1 conducts and clamps
VGS at V DD, and the inductor current continues to flow,
Fig. 5. Resonant driver with efficient energy recovery in [15].
freewheeling along DDR1 . At time t3 , when MDR1 turns off,
the inductor current decreases, which makes the body diode of
voltage with greater absolute value than VSS and V_POS MDR2 conduct, resulting in the inductor current flowing from
is a positive voltage). The values of V_POS and VSS_High the GN D to V DD by way of the body diode of MDR2 , LR , and
depend on the Q factor of the resonant circuit and the supply DDR1 and returning energy to the voltage source. Between t3
voltage VSS. However, for GaN HFETs applications, one of and t4 , the inductor current iLR decreases from IPEAK to zero,
the key problems is that high forward gate leakage currents and the gate–source voltage of the switch remains at V DD.
cause degradation of device parameters. When the gate voltage At time t5 , the nMOS transistor MDR2 turns on, and the
becomes positive, the forward leakage current shunts the gate- inductor current begins to flow in the opposite direction, dis-
channel capacitance, limiting both the maximum device current charging the MOSFET gate capacitor Ciss . When the gate
and the reliability of the device [1]. Consequently, avoiding pos- voltage VGS reaches zero, the inductor current reaches its nega-
itive gate–source voltage becomes a fundamental requirement, tive peak current at −Ipeak = −V DD/Z0 , and tr = t6 − t5 =
and therefore, the drive circuit shown in Fig. 4 is not suitable T /4. Until the voltage across Ciss is slightly lower than zero at
for driving GaN HFETs. t6 , the diode DDR2 conducts and clamps VGS at zero, and the
inductor current continues to flow, freewheeling along DDR2 .
At time t7 , when MDR2 turns off, the inductor current increases,
C. Resonant Circuit With Efficient Energy Recovery
which makes the body diode of MDR1 conduct, and the inductor
1) Circuit Introduction: A low-loss high-speed voltage- current flows from GN D to V DD by way of DDR2 , LR , and
clamping efficient energy-recovery resonant circuit is intro- the body diode of MDR1 and returns energy to the voltage
duced in [15]. Figs. 5 and 6 show the resonant circuit and its source. Between t7 and t8 , the inductor current iLR increases
relevant waveforms, respectively. from −IPEAK to zero, and the gate–source voltage of the switch
The operation of the circuit is described as follows, beginning remains at GN D [15].
at the negative storage position when VGS is equal to zero and 2) Power-Loss Calculation: There are three types of power
both MDR1 and MDR2 are turned off. At time t1 , when pMOS loss in the drive circuit: conduction loss, switching loss, and
MDR1 turns on, the inductor current iLR begins to flow and cross-conduction loss. The resonant drive circuit in Fig. 5 can
charges the input capacitor Ciss of the MOSFET switch M1 . reduce them all.
The resonant is built up through V DD, MDR1 , the resonant Conduction loss: From the description reported earlier,
inductor LR , and the input capacitor Ciss . Due to the resonance, it is clear that the conduction loss of the drive circuit can be

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846 IEEE TRANSACTIONS ON INDUSTRY APPLICATIONS, VOL. 45, NO. 2, MARCH/APRIL 2009

reduced by using the resonant drive topology to recover part of way as described earlier, results in the inductor current (9) and
the gate-drive energy. discharge energy (10) dissipation
Assuming that the initial value of the gate voltage is VGS and


the initial value for the inductor current is ILR , the inductor RG
V DD − 2L t 1 1
current iLR (t) and gate voltage VGS (t) can be calculated by iLR (t) ≈ −  e R sin t (9)
LR 2 LR Ciss
using the following: Ciss

t6
dVGS (t)
iLR (t) = Ciss (3) Edis_charge = RG i2LR (t)dt
dt
t5
diLR
VGS (t) = V DD − RG iLR − LR . (4)
dt tf
= RG i2LR (t)dt
Solving (3) and (4) obtains
0
⎛ ⎞
4LR
− RG
2 πV DD2 RG Ciss
R
− 2LG t Ciss = . (10)
iLR (t) = ILR e R cos ⎝ t⎠ 4Z0
2LR
Therefore, by using an L−C resonant circuit topology and
2V DD − 2VGS − RG ILR two clamp diodes, the power losses of the drive circuit are
+ 
Ciss − RG
4LR 2 reduced to [15]
⎛ ⎞
Ploss = (Echarge + Edis_charge )fs
Ciss − RG
4LR 2
RG
− 2L t
· e R sin ⎝ t⎠ . (5)
2LR πV DD2 RG Ciss π RG
= = QDD V DDfs . (11)
2Z0 2 Z0
During the charging phase, the initial values are VGS =
Equation (11) establishes that, as the MOSFET gate resistance
VGS (t1 ) = 0 and ILR = ILR (t1 ) = 0; solving (5) using these
decreases, the power loss of the driver will also decrease. In
two values results in
the aforementioned analysis, it was assumed that all the energy
⎛ ⎞ used for the commutation would be recovered. In practice, the
2V DD R
4LR
Ciss − RG
2
pMOS and nMOS in the “totem-pole” pair and the two block-
− 2LG t
iLR (t) =  e R sin ⎝ t⎠ . (6)
4LR
− 2
RG 2LR ing Schottky diodes lead to additional power losses; however,
Ciss choosing pMOS and nMOS with a small on-resistance and
two Schottky diodes with a small forward voltage and a small
Assuming that Z0  RG , (6) can be simplified to leakage current for DDR1 and DDR2 will make the relevant

power loss as small as possible.
RG
V DD − 2L t 1 1 Switching loss: This drive circuit also reduces the switch-
iLR (t) ≈  e R sin t . (7)
LR 2 LR Ciss ing loss of the device by adding the resonant inductor LR .
Ciss
During the turn on of M1 , the gate voltage VGS charges up
first. Once it reaches the threshold voltage, M1 turns on, and
Consequently, the energy dissipation by the series gate resistor the drain–source voltage of M1 , represented by VDS , decreases.
RG equals Meanwhile, the drain current of M1 , represented by Id , in-
creases. The turn-on switching loss occurs during this interval.
t2 When there is no resonant inductor, the drain current increases
Echarge = RG i2LR (t)dt rapidly and reaches the output current before the drain–source
t1 voltage reaches zero, which produces a high overlap between
tr Id and VDS , leading to a significant switching loss. When the
resonant inductor is added, the slew rate di/dt for M1 decreases
= RG i2LR (t)dt
so that the drain current does not reach the output current when
0 the drain–source voltage becomes zero. In this situation, the
πV DD2 RG Ciss
3/2 overlap between Id and VDS gets smaller so that the switching
= √ loss decreases. However, there is a tradeoff between the speed
4 LR
and the switching power loss, and the value of the inductor
πV DD2 RG Ciss should be chosen carefully to satisfy the requirements of the
= . (8)
4Z0 drive circuit.
Cross-conduction loss: In the drive circuit, two separated
During the discharging phase, VGS = VGS (t5 ) = V DD, and small-width pulse signals are used to drive the pMOS and
ILR = ILR (t5 ) = 0. Using these values to solve (5) in the same nMOS transistors in the “totem-pole” pair. Accordingly, there

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WANG et al.: EFFICIENT HIGH-FREQUENCY DRIVE CIRCUIT FOR GaN POWER HFETs 847

is no chance for both the pMOS and nMOS transistors to be

turned on at the same time. Consequently, the cross-conduction
loss should be very small [15].
In summary, this resonant drive circuit reduces the conduc-
tion, switching, and cross-conduction losses so that the total
gate-drive loss of the circuit is reduced.

IV. D ESIGN OF THE D RIVE C IRCUIT FOR GaN HFETs

Section III explained that the resonant circuit with efficient
energy recovery is a suitable drive circuit for high-frequency
switches. This circuit also has the property of voltage clamping,
which is required for driving GaN HFETs. However, this circuit
is not directly applicable to HFET devices. In order to apply this
topology to drive GaN HFETs, there are several problems that Fig. 7. Schematic of the proposed drive circuit for GaN HFETs.
need to be considered.
1) GaN HFETs are zero-voltage turn-on devices. They re-
quire zero voltage to turn them on and a negative voltage
to turn them off. Therefore, the drive circuit must be
able to work under a negative voltage supply V SSH
and GN D.
2) Most of the commercially available power MOSFETs
have long delays and long rise and fall times; even the
high-frequency power MOSFETs have rise and fall times
of around 10 ns. For example, in the experimental tests
described later, the nMOS transistor has 5-ns rise time,
5-ns fall time, and 8-ns turn-off delay time, while the
pMOS transistor has 7-ns rise time, 10-ns fall time,
and 11.2-ns turn-off delay time. Using a discrete power
pMOS and nMOS as the “totem-pole” pair will add
extra delay to the drive circuit and consequently limit the
operation frequency of the drive circuit. Fig. 8. Schematic of the topology implemented in the demonstrator.
3) GaN HFETs operating above 10 MHz demand a high-
change the polarity and the drive capability of the input control
speed drive circuit with an output current of about 50 mA.
signals. The two amplified signals coming out of the buffer
However, most of the commercially available power
stages were used to drive the GaN HFET devices by means of
pMOS and nMOS transistors have much higher output-
the high-efficiency resonant driver which consists of a pair of
current rates which are not compatible with the GaN
high-speed low-loss pMOS, nMOS, two Schottky diodes, and a
devices and lead to unnecessary power loss. For example,
resonant inductor.
the output drive currents of pMOS and nMOS used for
tests are around 1 A and are much bigger than the required
drive current for the GaN HFET device desired to be V. S IMULATION AND E XPERIMENTAL R ESULTS
driven. This high output current leads to high conduction
A. Design of the Prototype Board
energy dissipation, based on Ed = Ron ∗ Id2 .
4) In the following application, the input control signals In order to verify the topology of the drive circuit explained
are 3.3-V low-power digital signals from digital systems, in Section IV, a prototype board realized with discrete com-
such as field-programmable gate arrays (FPGAs) and ponents was built. Fig. 8 shows the complete schematic of the
DSPs. Considering that the drive signal required for GaN circuit implemented.
HFETs is a signal with a voltage level from 0 to −7 V, The input signals are two 3.3-V control signals coming from
an extra circuit needs to be added to change the polar- an FPGA board. The power supplies were chosen as V DD =
ity, voltage level, and current level of the input control 3.3 V (see V DD in Fig. 7) and V SSH = −7 V.
signals. Two high-speed operational-amplifiers (Op-Amps) LT1364
5) A small-sized easily implemented drive circuit must be were used as the buffer stages to change the 3.3-V input control
designed to fulfill the demand for convenient applications signals to −7-V signals with a higher drive capability.
for GaN HFETs. In a real circuit, the on-resistances of the diodes and the
In order to drive the GaN HFET devices, the resonant drive transistors in the “totem-pole” pair lead to power loss in the
circuit described in Section III was modified, as shown in Fig. 7. driver. In order to reduce this type of power loss, low on-
As shown in Fig. 7, the drive circuit is working under a resistance transistors were chosen for the “totem pole,” and
negative voltage V SSH. Two buffer stages were added to Schottky diodes were used for D5 and D6 because they have

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848 IEEE TRANSACTIONS ON INDUSTRY APPLICATIONS, VOL. 45, NO. 2, MARCH/APRIL 2009

low forward voltages and small reverse-recovery charges. In

the prototype board, a pair of low on-resistance high-frequency
transistors (ZXMD63P02X and ZXMD63N02X) and Schottky
diodes (10bq015) were chosen for the supplementary drive and
for the recovery path, respectively. In Fig. 8, LR is the parasitic
inductance of the interconnect wire, which can be changed by
adjusting the length of the wire. Ciss is the input capacitance of
the HFET device, and the load R is 1 kΩ.
The GaN HFET switches were produced in the microelec-
tronic laboratory of the University of South Carolina (USC). In
the experimental evaluation, 100-μm-wide AlGaN/GaN HFET
devices, with a gate length of 2 μm, gate-to-drain distance of
10 μm, and gate-to-source distance of 2 μm, built on sapphire,
were used with the resonant driver. The devices had a measured
current density of 0.8 A/mm, breakdown voltage above 300 V,
and dynamic on-resistance of around 5 mΩ · cm2 . The devices
were passivated with silicon nitride and had a field plate with an
overhang length of 2 μm for the suppression of current collapse.
Compared with the property of the drive circuit, the current
level of the GaN device is low (0.1 A), and it is not a good
choice for these experimental tests. However, this device was
used because it was the only one available in our lab at the
time. One-millimeter GaN devices with a 1-A current level are
Fig. 9. Aim–Spice simulation waveforms of the dashed block in Fig. 8.
now being fabricated in the USC semiconductor lab, and these Reference is made to 10-MHz switching frequency.
devices will be used for future tests.

B. Aim–Spice Simulation Results

The resonant drive circuit itself can work at very high fre-
quencies since the gate capacitance of the GaN devices is small.
Aim–Spice simulation was run for the resonant circuit (the
dashed block in Fig. 8) situated after the Op-Amps. Fig. 9
shows the simulation result for a 10-MHz switching frequency
with a pulsewidth of 10 ns for the input control signals.
In Figs. 8–10, VIN1 and VIN2 are the two input small
pulsewidth control signals, V_BUF1 and V_BUF2 are the two
signals which come out of the Op-Amps, and OUT_DRV is the
gate–source drive signal for GaN HFET. Referring to the input
control signals (VIN1 and VIN2) from the FPGA board, the
delay time is around 8 ns; the rise time tr is about 3 ns, and the
fall time tf is about 3 ns when the HFET device is loaded by a
1-kΩ resistor. The power loss of the drive circuit is 1 W, while
the power loss for a traditional driver is 15.1 W.
The Aim–Spice simulation waveforms for the entire circuit Fig. 10. Spice simulation waveforms for the whole drive circuit shown in
are shown in Fig. 10. Fig. 8.
As shown in Fig. 10, the delay time is 20 ns referring to the
input signals (VIN1 and VIN2), the rise time is 8 ns, and the switch signal shown in Fig. 10, compared with the simulation
fall time is 8 ns. All of these values are much larger than those results shown in Fig. 9.
shown in Fig. 9. The main reason is the mismatch between the
Op-Amps and power transistors in the “totem-pole” arrange-
C. Experimental Results
ment. Two high-speed Op-Amp chips LT1364 were used as the
buffer stages. Considering that the output currents of this Op- The testing waveforms for the complete circuit in Fig. 8
Amp are approximately 50 mA, which is not large enough to are shown in Fig. 11 which demonstrates the experimental
drive the power transistors pMOS and nMOS in the “totem- waveforms with switching frequencies of 1, 2, and 5.55 MHz.
pole” arrangement, the drive signals (V_BUF1 and V_BUF2 The input signals are at a voltage level of 3.3 V. As shown
in Fig. 10) from the Op-Amp are distorted. These distorted in Fig. 11, the drive circuit shifts the output voltage level and
signals, as well as the power MOSFETs themselves, lead to generates the 0−7-V gate–source switch signal for the GaN
longer delay, rise, and fall times for the output gate–source HFET switch.

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WANG et al.: EFFICIENT HIGH-FREQUENCY DRIVE CIRCUIT FOR GaN POWER HFETs 849

delay, rise, and fall times, as well as limit the operation

frequency of the circuit. As shown in Fig. 11(a), for the
1-MHZ switching frequency, the rise and the fall times
are both about 10 ns for the gate–source voltage of the
GaN HFET.
2) Fig. 11 shows significant ripples on the gate–source volt-
age of the GaN device. The ripples are ascribable to the
large parasitic inductors in the test circuit. In the proto-
type board, several different voltage supplies were used
for different chips. In order to reduce the noise induced
by these voltage supplies, each part of the circuit was
situated far from each other. This leads to a parasitic in-
ductance much bigger than that required for the LC tank.
Furthermore, in these experimental tests, a long cable
with large parasitic inductance was used to connect the
drive circuit board and the GaN HFET because of the lack
of the packaged GaN devices. These parasitic inductors
together produce significant ripples on the gate–source
voltage waveforms with the high frequencies shown in
Fig. 11. The same value as these parasitic inductors was
used to perform the Spice simulation, yielding the same
results as the experimental tests (Fig. 12).
In order to solve the problem brought by the un-
packaged GaN devices and to better verify our topology
of the drive circuit, a high-speed p-channel MOSFET
(ZVP3310F), with 40-pF input capacitance, was chosen
to repeat the same tests as those we did for GaN HFETs.
The experimental results (shown in Fig. 13) are much
better than those in Fig. 11. The ripples were reduced in
Fig. 13 since the big parasitic inductance corresponding
to the long interconnect cable was removed.
3) Another difficulty is due to the mismatch between the out-
put properties of the power MOSFETs in the drive circuit
and the drive GaN devices. The output drive current of
the driver is too large for the GaN devices.

VI. I MPROVEMENT OF THE D RIVE C IRCUIT : D ESIGN OF

THE I NTERGRATED C IRCUIT

In order to solve all the problems listed earlier, an inte-

grated drive circuit is introduced in this paper. The entire
drive circuit is implemented in a single integrated-circuit (IC)
chip using Smart-Voltage-eXtension (SVX) technology, which
builds HV devices in standard CMOS technologies by com-
bining the existing layers without modification of the process
steps.
Fig. 14 shows the schematic of the driver IC circuit for GaN
HFETs, including the level shifters, charge pump, digital block,
and resonant driver. The operation of the chip is as follows.
The charge-pump circuit generates the negative high voltage
Fig. 11. Experimental measurements of the drive circuit demonstrator: with
reference to (a) 1 MHz, (b) 2 MHz, and (c) 5.55 MHz. V SSH required for the resonant driver, from the positive low-
voltage power supply V DD. Initially, the digital block converts
the 3.3-V high-speed control signal, which is from digital sys-
Implementing this circuit with the prototype board presented tems (i.e., FPGAs, DSPs), into two narrow pulsewidth control
several problems. signals in order to reduce the cross-conduction loss of the drive
1) The experimental waveforms show the distorted signals circuit. Next, the level shifters change the polarity of the control
due to the device mismatch described earlier. These dis- signals, with a corresponding increase in the voltage and power
torted signals and the big power devices lead to large levels; the amplified signals are used to drive GaN HFETs by

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850 IEEE TRANSACTIONS ON INDUSTRY APPLICATIONS, VOL. 45, NO. 2, MARCH/APRIL 2009

Fig. 12. Aim–Spice simulation results with the parasitic inductor for the
cable.

means of a small-loss resonant circuit with efficient energy

recovery described in Section III.
The resonant topology is constituted by the HV nMOS and
HV pMOS connected in a “totem-pole” pair configuration,
which will generate suitable current for GaN HFET. Proper
values of LR , obtained by adjusting the length of the printed
circuit board (PCB) wire, and the Ciss of GaN HFETs govern
the resonant transition.
In the CMOS process, the functions of the drain and the
source on a transistor switch places, so to speak, if the polarity
of their voltage changes. Thus, in the resonant driver, in order Fig. 13. Experimental measurements with P-channel MOSFET, with refer-
to avoid the improper operation of the transistors, diodes D1 ence to (a) 1 MHz, (b) 3 MHz, and (c) 4 MHz.
and D2 are connected to the pMOS and nMOS to make
them conduct unidirectionally. The body diodes of the pMOS inductance, two discrete Schottky diodes were used for the
and nMOS are always inverse biased to guarantee the proper blocking diodes D5 and D6 , and placed as close as possible
operation of the devices; thus, diodes D3 and D4 are used, to the gate of the GaN devices. These diodes lead to additional
together with D5 and D6 , to form the low-impedance path power loss. However, this power loss is small because of the
in order to recover the energy. Since the bond wire and the following reasons: the short time during which the current flows
package of the IC chip contribute to a large part of the parasitic through the diodes to recover the energy, the small peak current

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WANG et al.: EFFICIENT HIGH-FREQUENCY DRIVE CIRCUIT FOR GaN POWER HFETs 851

Fig. 14. Schematic of the IC of the driver IC for GaN HFETs.

Fig. 15. Cadence–IC simulation waveforms of the circuit shown in Fig. 12 with reference to 10-MHz switching frequency.

(50 mA) of the diodes, and the small forward voltage (300 mV) VIII. A DVANTAGES OF THE N EW R ESONANT D RIVER FOR
and small leakage current for the Schottky diodes chosen for GaN HFET SWITCHES
D5 and D6 .
The proposed gate driver is specifically designed for GaN
HFETs and has several advantages over the conventional solu-
VII. C ADENCE -IC S IMULATION R ESULTS tion. These advantages are listed as follows.
The schematic and layout for the driver circuit shown in 1) The drive circuit uses the topology of the resonant circuit
Fig. 14 is being built using Cadence-IC and other IC design with effective energy recovery, which has the advantages
tools. The process H35B4 in Austriamicrosystems was selected of low gate-drive loss, fast switching speed, voltage
for the design. The simulation for the design of the driver is clamping, small cross-conduction power loss, and high
shown in Fig. 15, where the prelayout simulation results for a tolerance of timing variation of the control signals [15].
10-MHz switching frequency with a pulsewidth of 30 ns for the 2) SVX is used to implement the integrated drive circuit so
input control signals is shown. In the simulation, the parasitic that, instead of discrete power MOSFETs, HV nMOS
capacitances of all the components, except for the wire traces, and pMOS are used for the “totem-pole” pair in the
are included. The input signals are 3.3-V LV signals, and the resonant drive circuit. The sizes of the HV transistors can
voltage swing of the output signal is from −7 to 0 V. For the be carefully chosen to obtain a good match between the
simulation, the output drive current is about 50 mA. The rise driver and the GaN devices and also to reduce the time
time is about 2.5 ns, the fall time is nearly 2.5 ns, and the delay delay induced by the drive circuit.
time is around 8 ns. The total power loss for the drive circuit is 3) Using a parasitic inductor as the inductor in the LC tank
198 mW. allows the circuit to operate free of magnetic components.

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852 IEEE TRANSACTIONS ON INDUSTRY APPLICATIONS, VOL. 45, NO. 2, MARCH/APRIL 2009

R EFERENCES
[1] M. A. Khan, G. Simin, S. G. Pytel, A. Monti, E. Santi, and J. L. Hudgins,
“New developments in gallium nitride and the impact on power electron-
ics,” in Proc. IEEE Power Electron. Spec. Conf., Recife, Brazil, 2005,
pp. 15–26.
[2] N. Tipirneni, A. Koudymov, V. Adivarahan, J. Yang, G. Simin, and
M. A. Khan, “The 1.6-kV AlGaN/GaN HFETs,” IEEE Electron Device
Lett., vol. 27, no. 9, pp. 716–718, Sep. 2006.
[3] G. Simin, A. Tarakji, X. Hu, A. Koudymov, J. Yang, M. Asif Khan,
M. S. Shur, and R. Gaska, “High-temperature performance of
AlGaN/GaN metal–oxide–semiconductor heterostructure field-effect-
transistors,” Phys. Stat. Sol. (A), vol. 188, no. 1, pp. 219–222, 2001.
[4] M. A. de Rooij, J. T. Strydom, J. D. van Wyk, and P. Beamer, “Develop-
ment of a 1 MHz MOSFET gate-driver for integrated converters,” in Conf.
Rec. 37th IEEE IAS Annu. Meeting, 2002, pp. 2622–2629.
[5] “2.0A gate drive optocoupler with integrated (VCE) desaturation detec-
tion and fault status feedback,” Hewlett Packard Technical Datasheet for
Fig. 16. Level shifter cell. the HCPL316J Integrated Circuit.
[6] “High and low side driver,” International Rectifier Technical Datasheet
for the IR2113 Integrated Circuit.
For GaN-based HFET switches, the input capacitor is [7] “IGBT-driving hybrid ICs (EXB8.-series),” Fuji Electric Application
small so that only a small inductor (1–20 nH) is required Manual.
[8] “Hybrid Dual MOSFET-Driver,” Semikron Technical Datasheet for the
in this circuit. Typically, an inch of PCB conductor has an SKHI 21 A Hybrid Gate Driver Circuit.
inductance of 15 nH. It is possible to take advantage of [9] Datasheet of DS0026, Nat. Semicond., Santa Clara, CA, Feb. 2002.
this kind of parasitic inductance in the circuit and obtain [10] Datasheet of LM5112, Nat. Semicond., Santa Clara, CA, Oct. 2004.
[11] Datasheet of UCC27323/4/5, Texas Instrum., Dallas, TX, 2007.
the inductance required for the LC tank by adjusting the [12] J. T. Strydom, M. A. de Rooij, and J. D. van Wyk, “A comparison of
length of the PCB wire between the drive circuit and the fundamental gate-driver topologies for high frequency applications,” in
GaN device. Proc. IEEE APEC, 2004, pp. 1045–1052.
[13] Y. Chen, “Resonant gate drive techniques for power MOSFETs,” M.S.
4) The level shifter changes the polarity and increases the thesis, Virginia Polytech. Inst. State Univ., Blacksburg, VA, 2000.
voltage level and drive capability of the input signals. [14] I. D. de Vries, “A resonant power MOSFET/IGBT gate driver,” in Proc.
Fig. 16 shows a proposed circuit for a basic level-shifter IEEE APEC, Mar. 10–14, 2002, vol. 1, pp. 179–185.
[15] Y. Chen, F. C. Lee, L. Amoroso, and H.-P. Wu, “A resonant MOSFET
cell [16]. gate driver with efficient energy recovery,” IEEE Trans. Power Electron.,
5) The design of the integrated drive circuit reduces the vol. 19, no. 2, pp. 470–477, Mar. 2004.
size of the driver and also makes the application of GaN [16] H. Ballan, “High-voltage devices and circuits in standard CMOS tech-
nologies,” Ph.D. dissertation, EPFL, Lausanne, Switzerland, 1997.
HFETs convenient.
6) Decreasing the parasitic resistance of the GaN HFET
switch reduces the power loss of the drive system. The
GaN HFET switch discussed in this paper is designed
Bo Wang (S’00–M’05) received the B.S. and M.S.
and fabricated at USC. Progress is still being made to degrees in electrical engineering from Nanjing Uni-
improve the characteristics of these devices, for example, versity of Science and Technology, Nanjing, China,
to reduce the parasitic gate resistance and, thus, the in 1999 and 2002, respectively. Since 2005, she has
been working toward the Ph.D. degree in the Depart-
power loss. ment of Electrical Engineering, University of South
Carolina, Columbia.
From 2002 to 2004, she was a Digital Integrated-
Circuit (IC) Design Engineer with the Transporta-
IX. F UTURE W ORK tion and Standard Product Group, Semiconductor
Product Section, Motorola Electronics, Ltd., Suzhou,
Fabricating the IC for the proposed drive circuit is in China. Her research interests include IC design and power electronics. In
progress at the Microelectronic Laboratory of USC. Further particular, she is interested in mixed-signal IC design and gate-drive design
improvements in the circuit will be considered. The packaged for power devices.
GaN HFETs will be made in the USC semiconductor lab for
testing.

Naveen Tipirneni (M’07) received the B.Tech.

X. C ONCLUSION degree in electrical and electronics engineering
from Jawaharlal Nehru Technological University,
The requirement for driving GaN HFETs and the design of Hyderabad, India, in 2001, and the M.S. and Ph.D.
degrees in electrical engineering from the University
the gate-drive circuit have been discussed in this paper. The of South Carolina, Columbia, in 2003 and 2007,
presented topology provides a practical solution for the design respectively.
of a high-speed gate driver for the GaN-based HFETs. The He is currently a Staff Design Engineer with the
Advanced Technology and High Voltage MOSFET
circuit also benefits from the use of GaN as a superior material Group, Vishay Siliconix, Santa Clara, CA. His re-
in power electronics converters. Experimental results based search interests include employing novel physical
upon a demonstrator confirm the efficiency of the resonant and electrical properties of new materials to come up with environmentally
friendly electronic devices. He shows extended interest in understanding device
strategy used and the possibility of reaching high switching and material issues with wide bandgap semiconductors, such as SiC and (In, Al,
frequencies. Ga) III-N material systems for making efficient power electronic switches.

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WANG et al.: EFFICIENT HIGH-FREQUENCY DRIVE CIRCUIT FOR GaN POWER HFETs 853

Marco Riva (M’99) received the M.S. degree in Grigory Simin (A’01–M’03–SM’03) received the
electrical engineering and the Ph.D. degree from M.S.S.E. degree from Leningrad Electrotechnical In-
the Politecnico di Milano, Milan, Italy, in 1994 and stitute, Leningrad, Russia, in 1971, the Ph.D. degree
1997, respectively. in physics of semiconductors and dielectrics from
From 1994 to 1997, he was with the Power Elec- Giricond Science and Research Institute, Leningrad,
tronics and Electrical Drives Laboratory, Department and the Senior Research Scientist Diploma from the
of Electrical Engineering, Politecnico di Milano, Supreme State Committee on Academic Degrees in
where his research activity was mainly addressed 1985, where, during this period, his research in-
in the field of electronic converters’ analysis and cluded Gunn effect devices, GaAs metal semicon-
control system optimization. Since 1998, he has been ductor field-effect transistors, microwave and optical
with Electronic Laboratory, Department of Physics, integrated circuits (ICs), and semiconductor lasers.
Università degli Studi di Milan, Milan, where he is currently an Assistant Since 2001, he has been an Associate Professor with the Department of
Professor. He is the author or coauthor of about 70 scientific papers and holds Electrical Engineering, University of South Carolina, Columbia. His research
three patents. His research topics include modeling and design innovation of interests include GaN-based electronic devices and monolithic microwave ICs.
high-frequency converters, in both low- and high-voltage ranges, and design He has published four books, several book chapters, and more than 150 articles
and stability analysis of high-efficiency and low-weight power converters, in refereed journals.
most frequently addressed to onboard space satellite electronic systems and
equipment.
Dr. Riva serves on the Administration Committee of the Italian Association
of Electrical, Electronic and Telecommunication Engineers (AEIT-Federazione
Italiana di Elettrotecnica, Elettronica, Automazione, Informatica e Telecomu-
nicazioni) and on the Technical Committee 22 (Power Electronics) of the Enrico Santi (S’91–M’93–SM’01) received the
Italian institution for technical standards in the electrical, electronic, and Dr.Ing. degree in electrical engineering from the
telecommunication fields (CEI-Comitato Elettrotecnico Italiano). He is also University of Padua, Padova, Italy, in 1988, and
a member of the Italian Association for Automation (ANIPLA-Associazione the M.S. and Ph.D. degrees from the California In-
Nazionale Italiana per l’Automazione) and of the IEEE Power Electronics and stitute of Technology, Pasadena, in 1989 and 1994,
IEEE Industrial Electronics Societies. respectively.
From 1993 to 1998, he was a Senior Design
Engineer with TESLAco, Irvine, CA, where he was
Antonello Monti (S’88–M’89–SM’02) received the responsible for the development of various switching
M.S. degree in electrical engineering and the Ph.D. power supplies for commercial applications, such as
degree from the Politecnico di Milano, Milan, Italy, dc–dc power converters for telecommunications, and
in 1989 and 1994, respectively. fluorescent light electronic ballasts for avionic applications. Since 1998, he has
From 1990 to 1994, he was with the Research been with the University of South Carolina, Columbia, where he is currently
Laboratory, Ansaldo Industria, Milan, where he was an Associate Professor in the Department of Electrical Engineering. He has
responsible for the design of the digital control of published over 90 technical papers and book chapters on power electronics
a large power cycloconverter drive. He became an and modeling and simulation and holds two patents. His current research
Assistant Professor with the Department of Electrical interests include power electronics. Specifically, he is interested in physics-
Engineering, Politecnico di Milano, in 1995. Since based modeling of power semiconductor devices, control of power electronics
August 2000, he has been an Associate Professor systems, modeling and simulation of advanced power systems, and develop-
with the Department of Electrical Engineering, University of South Carolina, ment of hybrid power sources. He is involved in the development of the Virtual
Columbia. He is currently the Director of the Institute for Automation of Test Bed.
Complex Power Systems, E.ON Energy Research Center, RWTH Aachen Uni- Dr. Santi serves as an Associate Editor of the IEEE TRANSACTIONS ON
versity, Aachen, Germany. He is the author or coauthor of more than 200 papers POWER ELECTRONICS and of the IEEE TRANSACTIONS ON INDUSTRY
in the fields of power electronics and electrical drives. APPLICATIONS. He is a member of the IEEE Power Electronics Society
Dr. Monti served as the Chair of the IEEE Power Electronics Committee Administrative Committee, Faculty Advisor of the Student Chapter of the
on Simulation, Modeling, and Control and as an Associate Editor of the IEEE IEEE, and Chair of the Power Electronics Devices and Components Committee
TRANSACTIONS ON AUTOMATION SCIENCE AND ENGINEERING. of the IEEE Industry Applications Society.

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