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Behavioral Verilog and Timescale: ECE 551 Discussion 2/18/03

This document discusses behavioral Verilog and timescale directives. It outlines behavioral Verilog constructs like initial, always blocks and procedural statements. It describes blocking vs non-blocking assignments and how they determine flow. It also discusses conditional always blocks and procedural continuous assignments. For timescale, it explains how the timescale compiler directive sets the time unit and precision for simulation and provides an example.

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105 views

Behavioral Verilog and Timescale: ECE 551 Discussion 2/18/03

This document discusses behavioral Verilog and timescale directives. It outlines behavioral Verilog constructs like initial, always blocks and procedural statements. It describes blocking vs non-blocking assignments and how they determine flow. It also discusses conditional always blocks and procedural continuous assignments. For timescale, it explains how the timescale compiler directive sets the time unit and precision for simulation and provides an example.

Uploaded by

priyajeejo
Copyright
© © All Rights Reserved
Available Formats
Download as PDF, TXT or read online on Scribd
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Behavioral Verilog and Timescale

ECE 551 Discussion 2/18/03


David Leonard

Outline
1) Tip: WS_FTP
2) Behavioral Verilog Discussion
3) Timescale Discussion
4) Problem Set #3 Questions

Tip: WS_FTP
A graphical way to ftp files securely between accounts
In Windows, go to CAE Applications > Internet > WS_FTP.
Get a copy for your PC at (may not work anymore)
http://shelf.doit.wisc.edu/PC/WiscWorld/Client_Updates/WS_FTP/

Behavioral Verilog Discussion


Behavioral Verilog consists of procedures, procedural statements, and flow
control.
o Procedures
initial (executed once)
always (repetitively executed)
o Procedural Statements
Blocking (=)
Nonblocking (<=)
Procedural continuous assignments (assign, force)
o Flow Control
Conditional operator (?:)
Case statements (case, casex, casez)
Branching (if-else)
Loops (forever, repeat, while, for)
Each procedure construct starts a separate activity flow (thread), which are run in
parallel (just like hardware).
By default, procedures only include the next statement. An arbitrary number of
statements maybe included by use of begin and end.
module behave;
reg [1:0] a, b;
initial begin
a = b1;
b = b0;
end
always begin
#50 a = ~a;
end
always
#100 b = ~b;
endmodule

The always procedure can be executed conditionally using the @ symbol.


o Signals value changes - always@(signal)
o Transition of signal
Positive edge - always@(posedge clk)
Negative edge - always@(negedge clk)
o Multiple conditions - always@(signalA or signalB)
- always@(posedge clk or signalA)
- always@(posedge clk or posedge reset)
o posedge and negedge CANNOT be mixed in the conditional.
Procedural statements update register variables (reg, integer, etc.). In other
words, only register variables can be on LHS. However, there are several ways in
which they can be assigned. Assume a and b are 8-bit registers.
o Whole variable (a = )
o Partial variable
Subrange (a[6:0] = )
Bit (a[7] = )
o Concatenated variables ({a,b} = )
Blocking and nonblocking procedural assignments determine different flo ws
through begin-end blocks.
o A blocking statement (=) evaluates its RHS and updates its LHS before
flow continues to the next statement within a begin-end block.
o A nonblocking statement (<=) allows for assignment scheduling without
interrupting activity flow. Simply put, all RHS of consecutive
nonblocking statements evaluate before all their LHS update.
Procedural Assignment Flow Design Logic
Blocking Sequential Sequential
Nonblocking Parallel Combinational
Procedural continuous assignments (assign) override all procedural assignments
to a register while active. This assignment can only be changed by reassignment
(another assign) or de-assignment (deassign).
Timescale Discussion
`timescale - a compiler directive that sets the simulations time unit size and
precision
`timescale <time_unit> / <time_precision>
o time_unit constant multiplier of time values
o time_precision minimum step size during simulation, which determines
rounding of numerical values
Allowed unit/precision values: {1 | 10 | 100, s | ms | us | ns | ps}
Different timescales can be used for different sequences of modules.
Smallest time_precision determines the precision of the simulation.
Must be used in synthesis designs.

Example:
`timescale 10ps / 1ps

module sampleDesign (z,x1,x2);


input x1, x2;
output z;

nor #3.57 (z, x1, x2);


endmodule

The nor gates delay is 36 ps (3.57 x 10 = 35.7 ps rounded to 36).

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