MTD3055VL

Preferred Device

Power MOSFET
12 Amps, 60 Volts
NChannel DPAK3
This Power MOSFET is designed to withstand high energy in the
avalanche and commutation modes. Designed for low voltage, high
speed switching applications in power supplies, converters and power http://onsemi.com
motor controls, these devices are particularly well suited for bridge
circuits where diode speed and commutating safe operating areas are 12 AMPERES
critical and offer additional safety margin against unexpected voltage
transients. 60 VOLTS
Avalanche Energy Specified RDS(on) = 120 m (Typ)
IDSS and VDS(on) Specified at Elevated Temperature NChannel
D
MAXIMUM RATINGS (TC = 25C unless otherwise noted)
Rating Symbol Value Unit
DrainSource Voltage VDSS 60 Vdc G
DrainGate Voltage (RGS = 1.0 M) VDGR 60 Vdc
GateSource Voltage S
Continuous VGS 15 Vdc 4 MARKING DIAGRAMS
Single Pulse (tp 50 ms) VGSM 20 Vpk
4
Drain Current Continuous @ 25C ID 12 Adc 1 2 Drain
Drain Current Continuous @ 100C ID 8.0 3
Drain Current Single Pulse (tp 10 s) IDM 42 Apk

3055VL
DPAK3

YWW
Total Power Dissipation @ 25C PD 48 Watts CASE 369C
Derate above 25C 0.32 W/C Style 2
Total Power Dissipation @ TA = 25C 2.1 Watts 4
(Note 2) 2
1 3
Drain
Operating and Storage Temperature TJ, Tstg 55 to C Gate Source
175 4
Range
Drain
1
Single Pulse DraintoSource Avalanche EAS 72 mJ 2
3
Energy Starting TJ = 25C 3055VL
YWW

(VDD = 25 Vdc, VGS = 5.0 Vdc, DPAK3

IL = 12 Apk, L = 1.0 mH, RG = 25 ) CASE 369D
Style 2
Thermal Resistance C/W
JunctiontoCase RJC 3.13 3055VL Device Code
JunctiontoAmbient (Note 1) RJA 100
Y = Year
JunctiontoAmbient (Note 2) RJA 71.4 1 2 3
WW = Work Week
Gate Drain Source
Maximum Temperature for Soldering TL 260 C
Purposes, 1/8 from case for ORDERING INFORMATION
10 seconds
Device Package Shipping
1. When surfaced mounted to an FR4 board using the minimum recom-
mended pad size. MTD3055VL DPAK3 75 Units/Rail
2. When surface mounted to an FR4 board using 0.5 sq. in. pad size. DPAK3
MTD3055VL1 75 Units/Rail
(Straight Lead)
MTD3055VLT4 DPAK3 2500 Tape & Reel

For information on tape and reel specifications,

including part orientation and tape sizes, please
refer to our Tape and Reel Packaging Specifications
Brochure, BRD8011/D.

Preferred devices are recommended choices for future use

and best overall value.

Semiconductor Components Industries, LLC, 2003 1 Publication Order Number:

December, 2003 Rev. 5 MTD3055VL/D
 MTD3055VL

ELECTRICAL CHARACTERISTICS (TJ = 25C unless otherwise noted)

Characteristic Symbol Min Typ Max Unit
OFF CHARACTERISTICS
DrainSource Breakdown Voltage V(BR)DSS
(VGS = 0 Vdc, ID = 250 Adc) 60 Vdc
Temperature Coefficient (Positive) 62 mV/C
Zero Gate Voltage Drain Current IDSS Adc
(VDS = 60 Vdc, VGS = 0 Vdc) 10
(VDS = 60 Vdc, VGS = 0 Vdc, TJ = 150C) 100
GateBody Leakage Current (VGS = 15 Vdc, VDS = 0 Vdc) IGSS 100 nAdc
ON CHARACTERISTICS (Note 3)
Gate Threshold Voltage VGS(th)
(VDS = VGS, ID = 250 Adc) 1.0 1.6 2.0 Vdc
Threshold Temperature Coefficient (Negative) 3.0 mV/C
Static DrainSource OnResistance (VGS = 5.0 Vdc, ID = 6.0 Adc) RDS(on) 0.12 0.18 Ohm
DrainSource OnVoltage (VGS = 5.0 Vdc) VDS(on) Vdc
(ID = 12 Adc) 1.6 2.6
(ID = 6.0 Adc, TJ = 150C) 2.5
Forward Transconductance (VDS = 8.0 Vdc, ID = 6.0 Adc) gFS 5.0 8.8 mhos
DYNAMIC CHARACTERISTICS
Input Capacitance Ciss 410 570 pF
Output Capacitance (VDS = 25 Vdc,
Vd VGS = 0 Vdc,
Vd
Coss 114 160
f = 1.0 MHz)
Reverse Transfer Capacitance Crss 21 40

SWITCHING CHARACTERISTICS (Note 4)

TurnOn Delay Time td(on) 9.0 20 ns
Rise Time (VDD = 30 Vdc, ID = 12 Adc, tr 85 190
VGS = 5.0
5 0 Vdc,
Vdc
TurnOff Delay Time RG = 9.1 ) td(off) 14 30
Fall Time tf 43 90
Gate Charge QT 8.1 10 nC
(S Figure
(See Fi 8)
(VDS = 48 Vdc, ID = 12 Adc, Q1 1.8
VGS = 5 Vdc) Q2 4.2
Q3 3.8
SOURCEDRAIN DIODE CHARACTERISTICS
Forward OnVoltage (Note 3) VSD Vdc
(IS = 12 Adc, VGS = 0 Vdc)
0.97 1.3
(IS = 12 Adc, VGS = 0 Vdc, TJ = 150C)
0.86
Reverse Recovery Time trr 55.7 ns
(S Figure
(See Fi 14)
ta 37
(IS = 12 Adc,
Adc VGS = 0 Vdc,
Vdc
dIS/dt = 100 A/s) tb 18.7
Reverse Recovery Stored QRR 0.116 C
Charge

INTERNAL PACKAGE INDUCTANCE

Internal Drain Inductance LD 3.5 nH
(Measured from the drain lead 0.25 from package to center of die)

Internal Source Inductance LS 7.5 nH

(Measured from the source lead 0.25 from package to source bond pad)
3. Pulse Test: Pulse Width 300 s, Duty Cycle 2%.
4. Switching characteristics are independent of operating junction temperature.

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 MTD3055VL

TYPICAL ELECTRICAL CHARACTERISTICS

24 24
TJ = 25C VGS = 10 V 5V VDS 10 V TJ =
55C
25C
20 4.5 V 20 100C
I D , DRAIN CURRENT (AMPS)

I D , DRAIN CURRENT (AMPS)

16 16
4V

12 12
3.5 V
8 8
3V
4 4
2.5 V

0 0
0 1 2 3 4 5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0
VDS, DRAINTOSOURCE VOLTAGE (VOLTS) VGS, GATETOSOURCE VOLTAGE (VOLTS)

Figure 1. OnRegion Characteristics Figure 2. Transfer Characteristics

R DS(on) , DRAINTOSOURCE RESISTANCE (OHMS)

R DS(on) , DRAINTOSOURCE RESISTANCE (OHMS)

0.32 0.27
VGS = 5 V
TJ = 25C

0.26
0.22

0.20 TJ = 100C
0.17
0.14 25C

55C 0.12 5V
0.08
VGS = 10 V

0.02 0.07
0 4 8 12 16 20 24 0 4 8 12 16 20 24
ID, DRAIN CURRENT (AMPS) ID, DRAIN CURRENT (AMPS)

Figure 3. OnResistance versus Drain Current Figure 4. OnResistance versus Drain Current
and Temperature and Gate Voltage

2.0 100
R DS(on) , DRAINTOSOURCE RESISTANCE

VGS = 5 V VGS = 0 V
ID = 6 A

1.5
10 TJ = 125C
I DSS , LEAKAGE (nA)
(NORMALIZED)

1.0

1.0 100C

0.5

0 0.1

50
25 0 25 50 75 100 125 150 175 0 10 20 30 40 50 60
TJ, JUNCTION TEMPERATURE (C) VDS, DRAINTOSOURCE VOLTAGE (VOLTS)

Figure 5. OnResistance Variation with Figure 6. DrainToSource Leakage

Temperature Current versus Voltage

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 MTD3055VL

POWER MOSFET SWITCHING

Switching behavior is most easily modeled and predicted The capacitance (Ciss) is read from the capacitance curve at
by recognizing that the power MOSFET is charge a voltage corresponding to the offstate condition when
controlled. The lengths of various switching intervals (
t) calculating td(on) and is read at a voltage corresponding to the
are determined by how fast the FET input capacitance can onstate when calculating td(off).
be charged by current from the generator. At high switching speeds, parasitic circuit elements
The published capacitance data is difficult to use for complicate the analysis. The inductance of the MOSFET
calculating rise and fall because draingate capacitance source lead, inside the package and in the circuit wiring
varies greatly with applied voltage. Accordingly, gate which is common to both the drain and gate current paths,
charge data is used. In most cases, a satisfactory estimate of produces a voltage at the source which reduces the gate drive
average input current (IG(AV)) can be made from a current. The voltage is determined by Ldi/dt, but since di/dt
rudimentary analysis of the drive circuit so that is a function of drain current, the mathematical solution is
complex. The MOSFET output capacitance also
t = Q/IG(AV)
complicates the mathematics. And finally, MOSFETs have
During the rise and fall time interval when switching a finite internal gate resistance which effectively adds to the
resistive load, VGS remains virtually constant at a level resistance of the driving source, but the internal resistance
known as the plateau voltage, VSGP. Therefore, rise and fall is difficult to measure and, consequently, is not specified.
times may be approximated by the following: The resistive switching time variation versus gate
tr = Q2 x RG/(VGG VGSP) resistance (Figure 9) shows how typical switching
performance is affected by the parasitic circuit elements. If
tf = Q2 x RG/VGSP
the parasitics were not present, the slope of the curves would
where maintain a value of unity regardless of the switching speed.
VGG = the gate drive voltage, which varies from zero to VGG The circuit used to obtain the data is constructed to minimize
common inductance in the drain and gate circuit loops and
RG = the gate drive resistance is believed readily achievable with board mounted
and Q2 and VGSP are read from the gate charge curve. components. Most power electronic loads are inductive; the
During the turnon and turnoff delay times, gate current is data in the figure is taken with a resistive load, which
not constant. The simplest calculation uses appropriate approximates an optimally snubbed inductive load. Power
values from the capacitance curves in a standard equation for MOSFETs may be safely operated into an inductive load;
voltage change in an RC network. The equations are: however, snubbing reduces switching losses.
td(on) = RG Ciss In [VGG/(VGG VGSP)]
td(off) = RG Ciss In (VGG/VGSP)

1400
VDS = 0 V VGS = 0 V TJ = 25C
1200 Ciss
C, CAPACITANCE (pF)

1000

800

600
Crss Ciss
400
Coss
200
Crss
0
10 5 0 5 10 15 20 25
VGS VDS

GATETOSOURCE OR DRAINTOSOURCE VOLTAGE (VOLTS)

Figure 7. Capacitance Variation

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 MTD3055VL

6 60 1000
VGS, GATETOSOURCE VOLTAGE (VOLTS)

VDS , DRAINTOSOURCE VOLTAGE (VOLTS)

QT VDD = 30 V
ID = 12 A
50 VGS = 5 V
TJ = 25C
4 40 100 tr

t, TIME (ns)
VGS
tf
30
Q1 Q2 td(off)
2 20 10 td(on)
ID = 12 A
TJ = 25C
10

Q3 VDS
0 0 1
0 2 4 6 8 10 1 10 100
Qg, TOTAL GATE CHARGE (nC) RG, GATE RESISTANCE (OHMS)

Figure 8. GateToSource and DrainToSource Figure 9. Resistive Switching Time

Voltage versus Total Charge Variation versus Gate Resistance

DRAINTOSOURCE DIODE CHARACTERISTICS

12
VGS = 0 V
TJ = 25C
10
I S , SOURCE CURRENT (AMPS)

0
0.50 0.55 0.60 0.65 0.70 0.75 0.80 0.85 0.90 0.95 1.0
VSD, SOURCETODRAIN VOLTAGE (VOLTS)

Figure 10. Diode Forward Voltage versus Current

SAFE OPERATING AREA

The Forward Biased Safe Operating Area curves define reliable operation, the stored energy from circuit inductance
the maximum simultaneous draintosource voltage and dissipated in the transistor while in avalanche must be less
drain current that a transistor can handle safely when it is than the rated limit and adjusted for operating conditions
forward biased. Curves are based upon maximum peak differing from those specified. Although industry practice is
junction temperature and a case temperature (TC) of 25C. to rate in terms of energy, avalanche energy capability is not
Peak repetitive pulsed power limits are determined by using a constant. The energy rating decreases nonlinearly with an
the thermal response data in conjunction with the procedures increase of peak current in avalanche and peak junction
discussed in AN569, Transient Thermal temperature.
ResistanceGeneral Data and Its Use. Although many EFETs can withstand the stress of
Switching between the offstate and the onstate may draintosource avalanche at currents up to rated pulsed
traverse any load line provided neither rated peak current current (IDM), the energy rating is specified at rated
(IDM) nor rated voltage (VDSS) is exceeded and the continuous current (ID), in accordance with industry
transition time (tr,tf) do not exceed 10 s. In addition the total custom. The energy rating must be derated for temperature
power averaged over a complete switching cycle must not as shown in the accompanying graph (Figure 12). Maximum
exceed (TJ(MAX) TC)/(RJC). energy at currents below rated continuous ID can safely be
A Power MOSFET designated EFET can be safely used assumed to equal the values indicated.
in switching circuits with unclamped inductive loads. For

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 MTD3055VL

SAFE OPERATING AREA

100 75
VGS = 5 V
ID = 12 A

EAS, SINGLE PULSE DRAINTOSOURCE

SINGLE PULSE
TC = 25C
I D , DRAIN CURRENT (AMPS)

10 s

AVALANCHE ENERGY (mJ)

10 50
100 s

1 ms
1.0 10 ms 25
dc
RDS(on) LIMIT
THERMAL LIMIT
PACKAGE LIMIT
0.1 0
0.1 1.0 10 100 25 50 75 100 125 150 175
VDS, DRAINTOSOURCE VOLTAGE (VOLTS) TJ, STARTING JUNCTION TEMPERATURE (C)

Figure 11. Maximum Rated Forward Biased Figure 12. Maximum Avalanche Energy versus
Safe Operating Area Starting Junction Temperature

1.0
D = 0.5
TRANSIENT THERMAL RESISTANCE
r(t), NORMALIZED EFFECTIVE

0.2

0.1
0.1 0.05 P(pk)
RJC(t) = r(t) RJC
0.02 D CURVES APPLY FOR POWER
PULSE TRAIN SHOWN
0.01 t1 READ TIME AT t1
t2 TJ(pk) TC = P(pk) RJC(t)
SINGLE PULSE
DUTY CYCLE, D = t1/t2
0.01
1.0E05 1.0E04 1.0E03 1.0E02 1.0E01 1.0E+00 1.0E+01
t, TIME (s)

Figure 13. Thermal Response

di/dt
IS
trr
ta tb
TIME

tp 0.25 IS

IS

Figure 14. Diode Reverse Recovery Waveform

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 MTD3055VL

PACKAGE DIMENSIONS

DPAK3
CASE 369C01
ISSUE O
T SEATING
PLANE
B C
INCHES MILLIMETERS
V R E DIM MIN MAX MIN MAX
A 0.235 0.245 5.97 6.22
B 0.250 0.265 6.35 6.73
4 C 0.086 0.094 2.19 2.38
Z D 0.027 0.035 0.69 0.88
A E 0.018 0.023 0.46 0.58
S F 0.037 0.045 0.94 1.14
1 2 3 G 0.180 BSC 4.58 BSC
U H 0.034 0.040 0.87 1.01
K J 0.018 0.023 0.46 0.58
K 0.102 0.114 2.60 2.89
L 0.090 BSC 2.29 BSC
F J R 0.180 0.215 4.57 5.45
L S 0.025 0.040 0.63 1.01
H U 0.020 0.51
V 0.035 0.050 0.89 1.27
D 2 PL Z 0.155 3.93
G 0.13 (0.005) M T STYLE 2:
PIN 1. GATE
2. DRAIN
3. SOURCE
4. DRAIN
SOLDERING FOOTPRINT*

6.20 3.0
0.244 0.118
2.58
0.101

5.80 1.6 6.172

0.228 0.063 0.243

SCALE 3:1
inches

mm 

Figure 15. DPAK3

*For additional information on our PbFree strategy and soldering

details, please download the ON Semiconductor Soldering and
Mounting Techniques Reference Manual, SOLDERRM/D.

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 MTD3055VL

PACKAGE DIMENSIONS

DPAK3 (SINGLE GAUGE)

CASE 369D01
ISSUE B
B C NOTES:
1. DIMENSIONING AND TOLERANCING PER
V R E ANSI Y14.5M, 1982.
2. CONTROLLING DIMENSION: INCH.

INCHES MILLIMETERS
4 DIM MIN MAX MIN MAX
Z A 0.235 0.245 5.97 6.35
A B 0.250 0.265 6.35 6.73
S C 0.086 0.094 2.19 2.38
1 2 3
D 0.027 0.035 0.69 0.88
E 0.018 0.023 0.46 0.58
T F 0.037 0.045 0.94 1.14
SEATING G 0.090 BSC 2.29 BSC
PLANE K H 0.034 0.040 0.87 1.01
J 0.018 0.023 0.46 0.58
K 0.350 0.380 8.89 9.65
R 0.180 0.215 4.45 5.45
J S 0.025 0.040 0.63 1.01
F V 0.035 0.050 0.89 1.27
H
Z 0.155 3.93
D 3 PL
STYLE 2:
G 0.13 (0.005) M T PIN 1. GATE
2. DRAIN
3. SOURCE
4. DRAIN

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to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability
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