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Arithmetic and logic Unit (ALU)

ALU is responsible to perform the operation in the computer.
The basic operations are implemented in hardware level. ALU is having collection of two types
of operations:

Arithmetic operations

Logical operations

Consider an ALU having 4 arithmetic operations and 4 logical operation.

To identify any one of these four logical operations or four arithmetic operations, two control
lines are needed. Also to identify the any one of these two groups- arithmetic or logical, another
control line is needed. So, with the help of three control lines, any one of these eight operations
can be identified.
Consider an ALU is having four arithmetic operations - Addition, subtraction, multiplication and
division. Also consider that the ALU is having four logical operations: OR, AND, NOT & EXOR.
We need three control lines to identify any one of these operations. The input combination of
these control lines are shown below:
Control line

is used to identify the group: logical or arithmetic, ie

: arithmetic operation

: logical operation.

Control lines
and
are used to identify any one of the four operations in a group. One
possible combination is given here.

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A
decode is used to decode the instruction. The block diagram of the ALU is shown in
figure 2.1.

Figure 2.1: Block Diagram of the ALU

The ALU has got two input registers named as A and B and one output storage register, named
as C. It performs the operation as:
C = A op B
The input data are stored in A and B, and according to the operation specified in the control
lines, the ALU perform the operation and put the result in register C.
As for example, if the contents of controls lines are, 000, then the decoder enables the addition
operation and it activates the adder circuit and the addition operation is performed on the data
that are available in storage register A and B . After the completion of the operation, the result is
stored in register C.
We should have some hardware implementations for basic operations. These basic operations
can be used to implement some complicated operations which are not feasible to implement
directly in hardware.
There are several logic gates exists in digital logic circuit. These logic gates can be used to
implement the logical operation. Some of the common logic gates are mentioned here.
AND gate: The output is high if both the inputs are high. The AND gate and its truth table is
shown in Figure 2.2.

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Figure 2.2: AND gate and its truth table.

OR gate: The output is high if any one of the inputs is high. The OR gate and its truth table is
shown in Figure 2.3.

Figure 2.3: OR gate and its truth table.

EX-OR gate: The output is high if either of the input is high. The EX-OR gate and its truth table
is given in Figure 2.4.

Figure 2.4: EX-OR gate and its truth table.

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If we want to construct a circuit which will perform the AND operation on two 4-bit number, the
implementation of the 4-bit AND operation is shown in the Figure-2.5.

Figure2.5: 4-bit AND operator

Arithmetic Circuit
Binary Adder:
Binary adder is used to add two binary numbers.
In general, the adder circuit needs two binary inputs and two binary outputs. The input variables
designate the augends and addend bits; the output variables produce the sum and carry.
The binary addition operation of single bit is shown in the truth table.

C:

Carry Bit

S:

Sum Bit

The simplified sum of products expressions are

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The circuit implementation is

Figure 2.6: Circuit diagram and Block diagram of Half Adder

This circuit can not handle the carry input, so it is termed as half adder.The circuit diagram and
block diagram of Half Adder is shown in Figure 2.6.

Full Adder:
A full adder is a combinational circuit that forms the arithmetic sum of three bits. It consists of
three inputs and two outputs.
Two of the input variables, denoted by x and y, represent the two bits to be added. The third input
Z, represents the carry from the previous lower position.
The two outputs are designated by the symbols S for sum and C for carry.

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The simplified expression for S and C are

We may rearrange these two expressions as follows:

The circuit diagram full adder is shown in the figure.

Figure 2.7: Circuit diagram and block diagram of Full Adder

The circuit diagram and block diagram of a Full Adder is shown in the Figure 2.7. n-such single
bit full adder blocks are used to make n-bit full adder.

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To demonstrate the binary addition of four bit numbers, let us consider a specific example.
Consider two binary numbers
A =1 0 0 1

B=0011

To get the four bit adder, we have to use 4 full adder blocks. The carry output the lower bit is
used as a carry input to the next higher bit.
The circuit of 4-bit adder shown in the Figure 2.8.

Figure 2.8: A 4-bit adder circuit.

Binary Subtractor:
The subtraction operation can be implemented with the help of binary adder circuit, because

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We know that 2's complement representation of a number is treated as a negative number of the
given number.
We can get the 2's complements of a given number by complementing each bit and adding 1 to
it.
The circuit for subtracting A-B consist of an added with inverter placed between each data input
B and the corresponding input of the full adder. The input carry
performing subtraction.

must be equal to 1 when

The operation thus performed becomes A , plus the 1's complement of B , plus 1. This is equal to
A plus 2's complement of B.
With this principle, a single circuit can be used for both addition and subtraction. The 4 bit adder
subtractor circuit is shown in the figure. It has got one mode ( M ) selection input line, which will
determine the operation,
If
If

then
then
1's complement of

Figure 2.9: 4-bit adder subtractor

The circuit diagram of a 4-bit adder substructures shown in the Figure 2.9.
The operation of OR gate:

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if
if

Implemental issue of some operations

Multiplication
Multiplication of two numbers in binary representation can be performed by a process of SHIFT
and ADD operations. Since the binary number system allows only 0 and 1's, the digit
multiplication can be replaced by SHIFT and ADD operation only, because multiplying by 1
gives the number itself and multiplying by 0 produces 0 only.
The multiplication process is illustrated with a numerical example.

The process consists of looking at successive bits of the multiplier, least significant bit first. If
the multiplier bit is a 1, the multiplicand is copied down, otherwise, zeros are copied down. The
numbers copied down in successive lines are shifted one position to the left from the previous
number. Finally, the numbers are added and their sum forms the product.
When multiplication is implemented in a digital computer, the process is changed slightly.
Instead of providing registers to store and add simultaneously as many binary numbers as there
are bits in the multiplier, it is convenient to provide an adder for the summation of only two
binary numbers and successively accumulate the partial products in a register. It will reduce the
requirements of registers.
Instead of sifting the multiplicand to the left, the partial product is shifted to right.

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When the corresponding bit of the multiplier is 0, there is no need to add all zeros to the partial
product.
An algorithm to multiply two binary numbers. Consider that the ALU does not provide the
multiplication operation, but it is having the addition operation and shifting operation. Then we
can write a micro program for multiplication operation and provide the micro program code in
memory. When a multiplication operation is encountered, it will execute this micro code to
perform the multiplication.

Binary Multiplier, Hardware Implementation

The block diagram of binary multiplier is shown in the Figure 2.10..

Figure 1.10: Block diagram of binary multiplier

The multiplicand is stored in register B and the multiplier is stored in register Q.
The partial product is formed in register A and stored in A and Q
The counter P is initially set to a number equal to the number of bits in the multiplier. The
counter is decremented by 1 after forming each partial product. When the content of the counter
reaches zero, the product is formed and the process stops.
Initially, the multiplicand is in register B and the multiplier in Q. The register A is reset to 0.
The sum of A and B forms a partial product- which is transferred to the EA register.
Both partial product and multiplier are shifted to the right. The least significant bit of A is shifted

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into the most significant position of Q; and 0 is shifted into E.

After the shift, one bit of the partial product is shifted into Q, pushing the multiplier bits one
position to the right.
The right most flip flop in register Q, designated by Q0 will hold the bit of the multiplier which
must be inspected next. If the content of this bit is 0, then it is not required to add the
multiplicand, only shifting is needed. If the content of this bit is 1, then both addition and shifting
are needed.
After each shifter, value of counter P is decremented and the process continues till the counter
value becomes 0.
The final result is available in ( EAQ ) registers combination.
To control the operation, it is required to design the appropriate control logic that is shown in the
block diagram.

The flow chart of the multiplication operation is given in the Figure 2.11.

Figure 2.11: Flow chart of the multiplication operation

The working of multiplication algorithm is shown here with the help of an example.
Multiplicand

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Problems
Q: Assume that the EX-OR gate has a propagation delay of 20ns and that the AND and OR
gate has a propagation delay of 10ns. What is the propagation delay of the full adder circuit?
What is the propagation delay of an 8-bit adder, which is constructed by connecting 8 full adder
in cascading manner.
Ans:
The propagation delay of the full adder circuit is 40ns, i.e. if we provide both the input and carry
at time ti, then after 40ns we will get stable output at sum and carry_out bit.

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Since the 8-bit adder is constructed by connecting 8 full adder in cascading manner, there will be
some delay in propagating the carry bit.
Since the carry output of i-th full adder is provided as an input to the (i+1)-th full adder, the
addition operation of (i+1)-th full adder cannot be performed until there is a stable output from ith full adder and which will appear after 40ns.
The first bit takes 40ns to provide the carry output. Similarly, second bit will take another 40ns
to produce the stable output.
Therefore, the total propagation delay is 40 X 8 = 320ns.

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