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Light-Weight Encryption Processor Verilog Code

This module implements a substitution box (S-Box) that maps 8-bit input values to 8-bit output values through a lookup table. The module was created by Waheeb Al-Rafati and Ahmad Shdifat. It contains a 256-entry case statement that defines the specific mapping between each possible 8-bit input and its corresponding 8-bit output.

Uploaded by

Ahmad Shdifat
Copyright
© © All Rights Reserved
Available Formats
Download as PDF or read online on Scribd
322 views

Light-Weight Encryption Processor Verilog Code

This module implements a substitution box (S-Box) that maps 8-bit input values to 8-bit output values through a lookup table. The module was created by Waheeb Al-Rafati and Ahmad Shdifat. It contains a 256-entry case statement that defines the specific mapping between each possible 8-bit input and its corresponding 8-bit output.

Uploaded by

Ahmad Shdifat
Copyright
© © All Rights Reserved
Available Formats
Download as PDF or read online on Scribd
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/*

"-----------------------------------" Light-Weight Encryption Processor "


"
S_Box.v
"
"
By :
"
" Waheeb Al-Rafati
"
" Ahmad Shdifat
"
----------------------------------*/
module S_Box
(
output [7:0] S_Box_Out,
input
[7:0] Data
);
reg
[7:0] S_Box_Output;
assign S_Box_Out = S_Box_Output;
always @(Data) begin
case(Data)
8'h00: S_Box_Output <=
8'h01: S_Box_Output <=
8'h02: S_Box_Output <=
8'h03: S_Box_Output <=
8'h04: S_Box_Output <=
8'h05: S_Box_Output <=
8'h06: S_Box_Output <=
8'h07: S_Box_Output <=
8'h08: S_Box_Output <=
8'h09: S_Box_Output <=
8'h0a: S_Box_Output <=
8'h0b: S_Box_Output <=
8'h0c: S_Box_Output <=
8'h0d: S_Box_Output <=
8'h0e: S_Box_Output <=
8'h0f: S_Box_Output <=
8'h10: S_Box_Output <=
8'h11: S_Box_Output <=
8'h12: S_Box_Output <=
8'h13: S_Box_Output <=
8'h14: S_Box_Output <=
8'h15: S_Box_Output <=

8'h63;
8'h7c;
8'h77;
8'h7b;
8'hf2;
8'h6b;
8'h6f;
8'hc5;
8'h30;
8'h01;
8'h67;
8'h2b;
8'hfe;
8'hd7;
8'hab;
8'h76;
8'hca;
8'h82;
8'hc9;
8'h7d;
8'hfa;
8'h59;

8'h16:
8'h17:
8'h18:
8'h19:
8'h1a:
8'h1b:
8'h1c:
8'h1d:
8'h1e:
8'h1f:
8'h20:
8'h21:
8'h22:
8'h23:
8'h24:
8'h25:
8'h26:
8'h27:
8'h28:
8'h29:
8'h2a:
8'h2b:
8'h2c:
8'h2d:
8'h2e:
8'h2f:
8'h30:
8'h31:
8'h32:
8'h33:
8'h34:
8'h35:
8'h36:
8'h37:
8'h38:
8'h39:
8'h3a:
8'h3b:
8'h3c:
8'h3d:
8'h3e:
8'h3f:

S_Box_Output
S_Box_Output
S_Box_Output
S_Box_Output
S_Box_Output
S_Box_Output
S_Box_Output
S_Box_Output
S_Box_Output
S_Box_Output
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S_Box_Output
S_Box_Output
S_Box_Output
S_Box_Output
S_Box_Output
S_Box_Output
S_Box_Output
S_Box_Output
S_Box_Output
S_Box_Output

<=
<=
<=
<=
<=
<=
<=
<=
<=
<=
<=
<=
<=
<=
<=
<=
<=
<=
<=
<=
<=
<=
<=
<=
<=
<=
<=
<=
<=
<=
<=
<=
<=
<=
<=
<=
<=
<=
<=
<=
<=
<=

8'h47;
8'hf0;
8'had;
8'hd4;
8'ha2;
8'haf;
8'h9c;
8'ha4;
8'h72;
8'hc0;
8'hb7;
8'hfd;
8'h93;
8'h26;
8'h36;
8'h3f;
8'hf7;
8'hcc;
8'h34;
8'ha5;
8'he5;
8'hf1;
8'h71;
8'hd8;
8'h31;
8'h15;
8'h04;
8'hc7;
8'h23;
8'hc3;
8'h18;
8'h96;
8'h05;
8'h9a;
8'h07;
8'h12;
8'h80;
8'he2;
8'heb;
8'h27;
8'hb2;
8'h75;

8'h40:
8'h41:
8'h42:
8'h43:
8'h44:
8'h45:
8'h46:
8'h47:
8'h48:
8'h49:
8'h4a:
8'h4b:
8'h4c:
8'h4d:
8'h4e:
8'h4f:
8'h50:
8'h51:
8'h52:
8'h53:
8'h54:
8'h55:
8'h56:
8'h57:
8'h58:
8'h59:
8'h5a:
8'h5b:
8'h5c:
8'h5d:
8'h5e:
8'h5f:
8'h60:
8'h61:
8'h62:
8'h63:
8'h64:
8'h65:
8'h66:
8'h67:
8'h68:
8'h69:

S_Box_Output
S_Box_Output
S_Box_Output
S_Box_Output
S_Box_Output
S_Box_Output
S_Box_Output
S_Box_Output
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S_Box_Output

<=
<=
<=
<=
<=
<=
<=
<=
<=
<=
<=
<=
<=
<=
<=
<=
<=
<=
<=
<=
<=
<=
<=
<=
<=
<=
<=
<=
<=
<=
<=
<=
<=
<=
<=
<=
<=
<=
<=
<=
<=
<=

8'h09;
8'h83;
8'h2c;
8'h1a;
8'h1b;
8'h6e;
8'h5a;
8'ha0;
8'h52;
8'h3b;
8'hd6;
8'hb3;
8'h29;
8'he3;
8'h2f;
8'h84;
8'h53;
8'hd1;
8'h00;
8'hed;
8'h20;
8'hfc;
8'hb1;
8'h5b;
8'h6a;
8'hcb;
8'hbe;
8'h39;
8'h4a;
8'h4c;
8'h58;
8'hcf;
8'hd0;
8'hef;
8'haa;
8'hfb;
8'h43;
8'h4d;
8'h33;
8'h85;
8'h45;
8'hf9;

8'h6a:
8'h6b:
8'h6c:
8'h6d:
8'h6e:
8'h6f:
8'h70:
8'h71:
8'h72:
8'h73:
8'h74:
8'h75:
8'h76:
8'h77:
8'h78:
8'h79:
8'h7a:
8'h7b:
8'h7c:
8'h7d:
8'h7e:
8'h7f:
8'h80:
8'h81:
8'h82:
8'h83:
8'h84:
8'h85:
8'h86:
8'h87:
8'h88:
8'h89:
8'h8a:
8'h8b:
8'h8c:
8'h8d:
8'h8e:
8'h8f:
8'h90:
8'h91:
8'h92:
8'h93:

S_Box_Output
S_Box_Output
S_Box_Output
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<=
<=
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<=
<=
<=
<=
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<=
<=
<=
<=
<=
<=
<=
<=
<=
<=
<=
<=
<=
<=
<=
<=
<=
<=
<=
<=
<=
<=
<=
<=
<=
<=
<=
<=
<=
<=
<=
<=
<=

8'h02;
8'h7f;
8'hf0;
8'h3c;
8'h9f;
8'ha8;
8'h51;
8'ha3;
8'h40;
8'h8f;
8'h92;
8'h9d;
8'h38;
8'hf5;
8'hbc;
8'hb6;
8'hda;
8'h21;
8'h10;
8'hff;
8'hf3;
8'hd2;
8'hcd;
8'h0c;
8'h13;
8'hec;
8'h5f;
8'h97;
8'h44;
8'h17;
8'hc4;
8'ha7;
8'h7e;
8'h3d;
8'h64;
8'h5d;
8'h19;
8'h73;
8'h60;
8'h81;
8'h4f;
8'hdc;

8'h94:
8'h95:
8'h96:
8'h97:
8'h98:
8'h99:
8'h9a:
8'h9b:
8'h9c:
8'h9d:
8'h9e:
8'h9f:
8'ha0:
8'ha1:
8'ha2:
8'ha3:
8'ha4:
8'ha5:
8'ha6:
8'ha7:
8'ha8:
8'ha9:
8'haa:
8'hab:
8'hac:
8'had:
8'hae:
8'haf:
8'hb0:
8'hb1:
8'hb2:
8'hb3:
8'hb4:
8'hb5:
8'hb6:
8'hb7:
8'hb8:
8'hb9:
8'hba:
8'hbb:
8'hbc:
8'hbd:

S_Box_Output
S_Box_Output
S_Box_Output
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S_Box_Output
S_Box_Output

<=
<=
<=
<=
<=
<=
<=
<=
<=
<=
<=
<=
<=
<=
<=
<=
<=
<=
<=
<=
<=
<=
<=
<=
<=
<=
<=
<=
<=
<=
<=
<=
<=
<=
<=
<=
<=
<=
<=
<=
<=
<=

8'h22;
8'h2a;
8'h90;
8'h88;
8'h46;
8'hee;
8'hb8;
8'h14;
8'hde;
8'h5e;
8'h0b;
8'hdb;
8'he0;
8'h32;
8'h3a;
8'h0a;
8'h49;
8'h06;
8'h24;
8'h5c;
8'hc2;
8'hd3;
8'hac;
8'h62;
8'h91;
8'h95;
8'he4;
8'h79;
8'he7;
8'hc8;
8'h37;
8'h6d;
8'h8d;
8'hd5;
8'h4e;
8'ha9;
8'h6c;
8'h56;
8'hf4;
8'hea;
8'h65;
8'h7a;

8'hbe:
8'hbf:
8'hc0:
8'hc1:
8'hc2:
8'hc3:
8'hc4:
8'hc5:
8'hc6:
8'hc7:
8'hc8:
8'hc9:
8'hca:
8'hcb:
8'hcc:
8'hcd:
8'hce:
8'hcf:
8'hd0:
8'hd1:
8'hd2:
8'hd3:
8'hd4:
8'hd5:
8'hd6:
8'hd7:
8'hd8:
8'hd9:
8'hda:
8'hdb:
8'hdc:
8'hdd:
8'hde:
8'hdf:
8'he0:
8'he1:
8'he2:
8'he3:
8'he4:
8'he5:
8'he6:
8'he7:

S_Box_Output
S_Box_Output
S_Box_Output
S_Box_Output
S_Box_Output
S_Box_Output
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S_Box_Output
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S_Box_Output
S_Box_Output
S_Box_Output
S_Box_Output
S_Box_Output
S_Box_Output
S_Box_Output

<=
<=
<=
<=
<=
<=
<=
<=
<=
<=
<=
<=
<=
<=
<=
<=
<=
<=
<=
<=
<=
<=
<=
<=
<=
<=
<=
<=
<=
<=
<=
<=
<=
<=
<=
<=
<=
<=
<=
<=
<=
<=

8'hae;
8'h08;
8'hba;
8'h78;
8'h25;
8'h2e;
8'h1c;
8'ha6;
8'hb4;
8'hc6;
8'he8;
8'hdd;
8'h74;
8'h1f;
8'h4b;
8'hbd;
8'h8b;
8'hba;
8'h70;
8'h3e;
8'hb5;
8'h66;
8'h48;
8'h03;
8'hf6;
8'h0e;
8'h61;
8'h35;
8'h57;
8'hb9;
8'h86;
8'hc1;
8'h1d;
8'h9e;
8'he1;
8'hf8;
8'h98;
8'h11;
8'h69;
8'hd9;
8'h8e;
8'h94;

8'he8: S_Box_Output <= 8'h9b;


8'he9: S_Box_Output <= 8'h1e;
8'hea: S_Box_Output <= 8'h87;
8'heb: S_Box_Output <= 8'he9;
8'hec: S_Box_Output <= 8'hce;
8'hed: S_Box_Output <= 8'h55;
8'hee: S_Box_Output <= 8'h28;
8'hef: S_Box_Output <= 8'hdf;
8'hf0: S_Box_Output <= 8'h8c;
8'hf1: S_Box_Output <= 8'ha1;
8'hf2: S_Box_Output <= 8'h89;
8'hf3: S_Box_Output <= 8'h0d;
8'hf4: S_Box_Output <= 8'hbf;
8'hf5: S_Box_Output <= 8'he6;
8'hf6: S_Box_Output <= 8'h42;
8'hf7: S_Box_Output <= 8'h68;
8'hf8: S_Box_Output <= 8'h41;
8'hf9: S_Box_Output <= 8'h99;
8'hfa: S_Box_Output <= 8'h2d;
8'hfb: S_Box_Output <= 8'h0f;
8'hfc: S_Box_Output <= 8'hb0;
8'hfd: S_Box_Output <= 8'h54;
8'hfe: S_Box_Output <= 8'hbb;
8'hff: S_Box_Output <= 8'h16;
default: S_Box_Output <= 8'hxx;
endcase
end
endmodule
//end S_Box.v

/*
"-----------------------------------" Light-Weight Encryption Processor "
"
Sixteen_Bytes_S_Box.v
"
"
By :
"
" Waheeb Al-Rafati
"
" Ahmad Shdifat
"
----------------------------------*/
module Sixteen_Bytes_S_Box(
output [127:0] Output_Wires,
input
[127:0] Input_Wires
);
S_Box
Byte01 (Output_Wires
ires [007:000]);
S_Box
Byte02 (Output_Wires
ires [015:008]);
S_Box
Byte03 (Output_Wires
ires [023:016]);
S_Box
Byte04 (Output_Wires
ires [031:024]);
S_Box
Byte05 (Output_Wires
ires [039:032]);
S_Box
Byte06 (Output_Wires
ires [047:040]);
S_Box
Byte07 (Output_Wires
ires [055:048]);
S_Box
Byte08 (Output_Wires
ires [063:056]);
S_Box
Byte09 (Output_Wires
ires [071:064]);
S_Box
Byte10 (Output_Wires
ires [079:072]);
S_Box
Byte11 (Output_Wires
ires [087:080]);
S_Box
Byte12 (Output_Wires
ires [095:088]);
S_Box
Byte13 (Output_Wires
ires [103:096]);
S_Box
Byte14 (Output_Wires
ires [111:104]);

[007:000],

Input_W

[015:008],

Input_W

[023:016],

Input_W

[031:024],

Input_W

[039:032],

Input_W

[047:040],

Input_W

[055:048],

Input_W

[063:056],

Input_W

[071:064],

Input_W

[079:072],

Input_W

[087:080],

Input_W

[095:088],

Input_W

[103:096],

Input_W

[111:104],

Input_W

S_Box
Byte15 (Output_Wires [119:112],
ires [119:112]);
S_Box
Byte16 (Output_Wires [127:120],
ires [127:120]);
endmodule
//end
Sixteen_Bytes_S_Box.v

Input_W
Input_W

/*
"-----------------------------------" Light-Weight Encryption Processor "
"
Shift_Rows.v
"
"
By :
"
" Waheeb Al-Rafati
"
" Ahmad Shdifat
"
----------------------------------*/
module Shift_Rows(
output [127:0] Output_Wires,
input
[127:0] Input_Wires,
input
CLK
);
reg [127:0] Output;
assign Output_Wires = Output;
always @ (posedge CLK) begin
Output <= {Input_Wires[95:88],Input_Wires[
55:48],Input_Wires[15:8],Input_Wires[103:96],Input
_Wires[63:56],Input_Wires[23:16],Input_Wires[111:1
04],Input_Wires[71:64],Input_Wires[31:24],Input_Wi
res[119:112],Input_Wires[79:72],Input_Wires[39:32]
,Input_Wires[127:120],Input_Wires[87:80],Input_Wir
es[47:40],Input_Wires[7:0]};
end
endmodule
// end Shift_Rows.v

/*
"-----------------------------------" Light-Weight Encryption Processor "
"
Add_Key.v
"
"
By :
"
" Waheeb Al-Rafati
"
" Ahmad Shdifat
"
----------------------------------*/
module Mix_Columns(
output [127:0] Output_Wires,
input
[127:0] Input_Wires,
input
CLK
);
reg [127:0] Output;
assign Output_Wires = Output;
always @ (posedge CLK ) begin
Output [007:000]
<= (Input_Wires [7] ?
{Input_Wires [6:0], 1'b0} ^ 8'h1B : {Input_Wires
[6:0], 1'b0}) ^ ( Input_Wires [15] ? {Input_Wires
[14:8], 1'b0} ^ Input_Wires [15:8] ^ 8'h1b : {Inpu
t_Wires [14:8], 1'b0} ^ Input_Wires [15:8]) ^ Inpu
t_Wires [23:16] ^ Input_Wires [31:24];
Output [015:008]
<= Input_Wires [7:0]
^ (Input_Wires [15] ? {Input_Wires [14:8], 1'b0} ^
8'h1B : {Input_Wires [14:8], 1'b0}) ^ (Input_Wire
s [23] ? {Input_Wires [22:16], 1'b0} ^ Input_Wires
[23:16] ^ 8'h1B : {Input_Wires [22:16], 1'b0} ^ I
nput_Wires [23:16]) ^ Input_Wires [31:24];
Output [023:016]
<= Input_Wires [7:0]
^ Input_Wires [15:8] ^ (Input_Wires [23] ? {Input_
Wires [22:16], 1'b0} ^ 8'h1B : {Input_Wires [22:16
], 1'b0}) ^ (Input_Wires [31] ? {Input_Wires [30:2
4], 1'b0} ^ Input_Wires [31:24] ^ 8'h1B : {Input_W
ires [30:24], 1'b0} ^ Input_Wires [31:24]);
Output [031:024]
<= (Input_Wires [7] ?
{Input_Wires [6:0], 1'b0} ^ Input_Wires [7:0] ^ 8
'h1B : {Input_Wires [6:0], 1'b0} ^ Input_Wires [7:
0]) ^ Input_Wires [15:8] ^ Input_Wires [23:16] ^ (
Input_Wires [31] ? {Input_Wires [30:24], 1'b0} ^ 8
'h1B : {Input_Wires [30:24], 1'b0});

Output [039:032]
<= (Input_Wires [39]
? {Input_Wires [38:32], 1'b0} ^ 8'h1B : {Input_Wir
es [38:32], 1'b0}) ^ ( Input_Wires [47] ? {Input_W
ires [46:40], 1'b0} ^ Input_Wires [47:40] ^ 8'h1b
: {Input_Wires [46:40], 1'b0} ^ Input_Wires [47:40
]) ^ Input_Wires [55:48] ^ Input_Wires [63:56];
Output [047:040]
<= Input_Wires [39:32
] ^ (Input_Wires [47] ? {Input_Wires [46:40], 1'b0
} ^ 8'h1B : {Input_Wires [46:40], 1'b0}) ^ (Input_
Wires [55] ? {Input_Wires [54:48], 1'b0} ^ Input_W
ires [55:48] ^ 8'h1B : {Input_Wires [54:48], 1'b0}
^ Input_Wires [55:48]) ^ Input_Wires [63:56];
Output [055:048]
<= Input_Wires [39:32
] ^ Input_Wires [47:40] ^ (Input_Wires [55] ? {Inp
ut_Wires [54:48], 1'b0} ^ 8'h1B : {Input_Wires [54
:48], 1'b0}) ^ (Input_Wires [63] ? {Input_Wires [6
2:56], 1'b0} ^ Input_Wires [63:56] ^ 8'h1B : {Inpu
t_Wires [62:56], 1'b0} ^ Input_Wires [63:56]);
Output [063:056]
<= (Input_Wires [39]
? {Input_Wires [38:32], 1'b0} ^ Input_Wires [39:32
] ^ 8'h1B : {Input_Wires [38:32], 1'b0} ^ Input_Wi
res [39:32]) ^ Input_Wires [47:40] ^ Input_Wires [
55:48] ^ (Input_Wires [63] ? {Input_Wires [62:56],
1'b0} ^ 8'h1B : {Input_Wires [62:56], 1'b0});
Output [071:064]
<= (Input_Wires [71]
? {Input_Wires [70:64], 1'b0} ^ 8'h1B : {Input_Wir
es [70:64], 1'b0}) ^ ( Input_Wires [79] ? {Input_W
ires [78:72], 1'b0} ^ Input_Wires [79:72] ^ 8'h1b
: {Input_Wires [78:72], 1'b0} ^ Input_Wires [79:72
]) ^ Input_Wires [87:80] ^ Input_Wires [95:88];
Output [079:072]
<= Input_Wires [71:64
] ^ (Input_Wires [79] ? {Input_Wires [78:72], 1'b0
} ^ 8'h1B : {Input_Wires [78:72], 1'b0}) ^ (Input_
Wires [87] ? {Input_Wires [86:80], 1'b0} ^ Input_W
ires [87:80] ^ 8'h1B : {Input_Wires [86:80], 1'b0}
^ Input_Wires [87:80]) ^ Input_Wires [95:88];
Output [087:080]
<= Input_Wires [71:64
] ^ Input_Wires [79:72] ^ (Input_Wires [87] ? {Inp
ut_Wires [86:80], 1'b0} ^ 8'h1B : {Input_Wires [86
:80], 1'b0}) ^ (Input_Wires [95] ? {Input_Wires [9

4:88], 1'b0} ^ Input_Wires [95:88] ^ 8'h1B : {Inpu


t_Wires [94:88], 1'b0} ^ Input_Wires [95:88]);
Output [095:088]
<= (Input_Wires [71]
? {Input_Wires [70:64], 1'b0} ^ Input_Wires [72:64
] ^ 8'h1B : {Input_Wires [70:64], 1'b0} ^ Input_Wi
res [71:64]) ^ Input_Wires [79:72] ^ Input_Wires [
87:80] ^ (Input_Wires [95] ? {Input_Wires [94:88],
1'b0} ^ 8'h1B : {Input_Wires [94:88], 1'b0});
Output [103:096]
<= (Input_Wires [103]
? {Input_Wires [102:96], 1'b0} ^ 8'h1B : {Input_W
ires [102:96], 1'b0}) ^ ( Input_Wires [111] ? {Inp
ut_Wires [110:104], 1'b0} ^ Input_Wires [111:104]
^ 8'h1b : {Input_Wires [110:104], 1'b0} ^ Input_Wi
res [111:104]) ^ Input_Wires [119:112] ^ Input_Wir
es [127:120];
Output [111:104]
<= Input_Wires [103:9
6] ^ (Input_Wires [111] ? {Input_Wires [110:104],
1'b0} ^ 8'h1B : {Input_Wires [110:104], 1'b0}) ^ (
Input_Wires [119] ? {Input_Wires [118:112], 1'b0}
^ Input_Wires [119:112] ^ 8'h1B : {Input_Wires [11
8:112], 1'b0} ^ Input_Wires [119:112]) ^ Input_Wir
es [127:120];
Output [119:112]
<= Input_Wires [103:9
6] ^ Input_Wires [111:104] ^ (Input_Wires [119] ?
{Input_Wires [118:112], 1'b0} ^ 8'h1B : {Input_Wir
es [118:112], 1'b0}) ^ (Input_Wires [127] ? {Input
_Wires [126:120], 1'b0} ^ Input_Wires [127:120] ^
8'h1B : {Input_Wires [126:120], 1'b0} ^ Input_Wire
s [127:120]);
Output [127:120]
<= (Input_Wires [103]
? {Input_Wires [102:96], 1'b0} ^ Input_Wires [103
:96] ^ 8'h1B : {Input_Wires [102:96], 1'b0} ^ Inpu
t_Wires [103:96]) ^ Input_Wires [111:104] ^ Input_
Wires [119:112] ^ (Input_Wires [127] ? {Input_Wire
s [126:120], 1'b0} ^ 8'h1B : {Input_Wires [126:120
], 1'b0});
end
endmodule
//end Mix_Columns.v

/*
"-----------------------------------" Light-Weight Encryption Processor "
"
Add_Key.v
"
"
By :
"
" Waheeb Al-Rafati
"
" Ahmad Shdifat
"
----------------------------------*/
module Add_Key(
output [127:0] Output_Wires,
input
[127:0] Input_Wires,
input
[7:0]
Key
);
assign Output_Wires [007:000] =
Input_Wires
7:000]
^
Key;
assign Output_Wires [015:008] =
Input_Wires
5:008]
^
Key;
assign Output_Wires [023:016] =
Input_Wires
3:016]
^
Key;
assign Output_Wires [031:024] =
Input_Wires
1:024]
^
Key;
assign Output_Wires [039:032] =
Input_Wires
9:032]
^
Key;
assign Output_Wires [047:040] =
Input_Wires
7:040]
^
Key;
assign Output_Wires [055:048] =
Input_Wires
5:048]
^
Key;
assign Output_Wires [063:056] =
Input_Wires
3:056]
^
Key;
assign Output_Wires [071:064] =
Input_Wires
1:064]
^
Key;
assign Output_Wires [079:072] =
Input_Wires
9:072]
^
Key;
assign Output_Wires [087:080] =
Input_Wires
7:080]
^
Key;
assign Output_Wires [095:088] =
Input_Wires
5:088]
^
Key;
assign Output_Wires [103:096] =
Input_Wires
3:096]
^
Key;
assign Output_Wires [111:104] =
Input_Wires
1:104]
^
Key;

[00
[01
[02
[03
[03
[04
[05
[06
[07
[07
[08
[09
[10
[11

assign Output_Wires [119:112]


9:112]
^
Key;
assign Output_Wires [127:120]
7:120]
^
Key;
endmodule
//end Add_Key.v

Input_Wires [11

Input_Wires [12

/*
"-----------------------------------" Light-Weight Encryption Processor "
"
Processor.v
"
"
By :
"
" Waheeb Al-Rafati
"
" Ahmad Shdifat
"
----------------------------------*/
module Processor(
output [127:0] Round_1_Output_Wires,
output [127:0] Round_2_Output_Wires,
input
[127:0] Input_Wires,
input
[7:0]
Key_Wires,
input
CLK,
input
Reset_Processor,
input
Start_Wire,
output Encryption_Done_Wire
);
parameter
3'b000;
parameter
3'b001;
parameter
3'b010;
parameter
3'b011;
parameter
3'b100;
parameter
3'b101;
parameter
3'b110;
reg
reg
reg
reg

IDLE_State

Shift_Rows_State

Mix_Columns_State

Buffer_Round_1_Result_State

Buffer_Round_2_Result_State

Prepare_Round_2_State

Encryption_Done_State

wire

[127:0] Input_Buffer;
[127:0] Round_1_Output_Buffer;
[127:0] Round_2_Output_Buffer;
Encryption_Done;
[127:0] S_Box_Input_Wires;

wire
wire
wire
wire

[127:0]
[127:0]
[127:0]
[127:0]

S_Box_Output_Wires;
Shift_Rows_Output_Wires;
Mix_Columns_Output_Wires;
Add_Key_Output_Wires;

assign S_Box_Input_Wires
uffer;
assign Round_1_Output_Wires
_Output_Buffer;
assign Round_2_Output_Wires
_Output_Buffer;

Input_B

Round_1

Round_2

reg [2:0]
Next_State;
reg Round;
assign Encryption_Done_Wire = Encryption_Done;
Sixteen_Bytes_S_Box Block00 (S_Box_Output_Wires, S_
Box_Input_Wires);
Shift_Rows
Block01 (Shift_Rows_Output_Wire
s, S_Box_Output_Wires, CLK);
Mix_Columns
Block02 (Mix_Columns_Output_Wir
es, Shift_Rows_Output_Wires, CLK);
Add_Key
Block03 (Add_Key_Output_Wires,
Mix_Columns_Output_Wires,Key_Wires);
always @(posedge CLK or posedge Reset_Processor or
posedge Start_Wire)
if (Reset_Processor) begin
Input_Buffer
<= 128'h000000
00000000000000000000000000;
Round_1_Output_Buffer
<= 128'h000000
00000000000000000000000000;
Round_2_Output_Buffer
<= 128'h000000
00000000000000000000000000;
Round
<= 1'b0;
Encryption_Done
<= 1'b0;
Next_State
<= IDLE_State;
end
else if (Start_Wire) begin
Input_Buffer
;

<=

Input_Wires

Round_1_Output_Buffer
<= 128'h000000
00000000000000000000000000;
Round_2_Output_Buffer
<= 128'h000000
00000000000000000000000000;
Round
<= 1'b0;
Encryption_Done
<= 1'b0;
Next_State
<= Shift_Rows_
State;
end
else case (Next_State)
IDLE_State
:
Next_State
<= IDLE_State;
Shift_Rows_State
:
Next_State
<= Mix_Columns_State;
Mix_Columns_State
:
Next_State
<= Round
?
Buffer_Round_2_R
esult_State :
Buffer_Round_1_Result_State;
Buffer_Round_1_Result_State
:
begin
Round_1_Out
put_Buffer
<= Add_Key_Output_Wires;
Next_State
<= Prepare_Round_2_State;
end
Prepare_Round_2_State
:
begin
Input_Buff
er
<= Round_1_Output_Buffer;
Next_State
<= Shift_Rows_State;
Round
<= 1'b1;
end
Buffer_Round_2_Result_State
:
begin
Round_2_Out
put_Buffer
<= Add_Key_Output_Wires;
Next_State
<= Encryption_Done_State;
end
Encryption_Done_State
:
Encryption_
Done
<= 1'b1;
default
:
begin
Input_Buff
er
<= 128'h00000000000000000000000

000000000;
tput_Buffer
000000000;
tput_Buffer
000000000;

<=

Round_1_Ou
128'h00000000000000000000000

<=

Round_2_Ou
128'h00000000000000000000000
Next_State

<=

IDLE_State;
end

endcase
endmodule
//end Processor.v

/*
"-----------------------------------" Light-Weight Encryption Processor "
"
Test_Bench.v
"
"
By :
"
" Waheeb Al-Rafati
"
" Ahmad Shdifat
"
----------------------------------*/
module tb;
reg
CLK,Reset;
reg
[127:0] Input_Data;
wire
[127:0] Round_1_Output;
wire
[127:0] Round_2_Output;
reg
[7:0]
Key;
reg
Start;
Processor Block(Round_1_Output, Round_2_Output
, Input_Data, Key, CLK, Reset, Start, Done);
initial CLK = 0;
initial forever #10 CLK =

~CLK;

initial begin
Reset
=
1'b1;
Start
=
1'b0;
Input_Data =
128'h1615141312111009080706
0504030201;
Key
=
8'h55;
#10 Reset
=
1'b0;
Start
=
1'b1;
#10 Start
=
1'b0;
end
always @(posedge Done)
$stop;
endmodule
//end Test_Bench.v

/*
"-----------------------------------" Light-Weight Encryption Processor "
"
Run.tcl
"
"
By :
"
" Waheeb Al-Rafati
"
" Ahmad Shdifat
"
----------------------------------*/
# TCL FILE FOR WAHTEST EXAMPLE
cd "D:/Project/"
# to delete lib
#
#vmap -del mydes
#vdel -all -lib mydes
# to create lib
#
vlib aes
vmap aes aes
# compile vlog files (must have a testbench)
vlog -reportprogress 300 -work aes \
"Sixteen_Bytes_S_Box.v"\
"Test_Bench.v"\
"Shift_Rows.v"\
"Mix_Columns.v"\
"Add_key.v"\
"S_Box.v"\
"Processor.v"\
# load the testbench
vsim -voptargs=+acc \
aes.tb
# load the signals
add wave sim:/tb/*
add wave sim:/tb/Block/Next_State
add wave sim:/tb/Block/Round

# run the simulation


run -all
//end run.tcl

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